CN210225248U - Time delay switch driving circuit and system - Google Patents
Time delay switch driving circuit and system Download PDFInfo
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- CN210225248U CN210225248U CN201921624079.XU CN201921624079U CN210225248U CN 210225248 U CN210225248 U CN 210225248U CN 201921624079 U CN201921624079 U CN 201921624079U CN 210225248 U CN210225248 U CN 210225248U
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Abstract
The application provides a delay switch drive circuit and a delay switch drive system, and relates to the technical field of switch control drive circuits. The circuit includes: the power-off control circuit comprises a control circuit, a switch circuit and a delay circuit, wherein the control circuit, the switch circuit and the delay circuit are sequentially and electrically connected, the input end of the control circuit is electrically connected with a power-off control pin, and the output end of the delay circuit is connected with a controlled switch power supply. The control circuit controls the switch circuit to be disconnected or connected with the delay circuit through a level signal output by the power-off control pin in a enabled state or a disabled state, so that the delay circuit outputs a power-off signal or a restarting signal to the controlled switch power supply to control the controlled switch power supply to be disconnected and automatically restarted. In addition, the controlled switch power supply can be powered off or restarted after reaching the preset time after the output level of the power-off control pin through the delay circuit, so that the capacitive load in the electronic equipment system before restarting can be completely discharged, and the damage of the controlled switch power supply is avoided.
Description
Technical Field
The utility model relates to a switching control drive circuit technical field particularly, relates to a time delay switch drive circuit and system.
Background
With the continuous progress and development of science and technology, people's life has been kept away from electronic equipment, and electronic equipment is in the use, when meeting the circumstances such as card machine or resource update, inevitably need restart electronic equipment system to guarantee electronic equipment's normal operating.
In an existing electronic device system, when the system is powered off and restarted, a mode of immediately powering on and starting the system after the system is powered off is often adopted.
However, the complexity of the internal architecture of the electronic device system is different, and the electronic device system cannot be normally started due to the fact that the electronic device system is powered on immediately after power failure and secondary power on is performed after incomplete discharge in the system after power failure.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a delay switch drive circuit and system to the not enough among the above-mentioned prior art to solve the electronic system that exists among the prior art and restart the in-process in the outage, adopt the outage back to go up the electricity immediately, the load is discharged incompletely before the electricity is gone up to the secondary in the system, leads to the system can not normally start, influences the problem of the performance of electronic equipment system.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a delay switch driving circuit, including: the control circuit, the switch circuit and the delay circuit;
the input end of the control circuit is electrically connected with the power-off restart control pin, the output end of the control circuit is electrically connected with the input end of the switch circuit, the output end of the switch circuit is electrically connected with the input end of the delay circuit, and the output end of the delay circuit is electrically connected with the controlled switch power supply;
the control circuit is used for controlling the switch circuit to be disconnected with the delayed circuit based on the first state of the power-off restart control pin, so that the delayed circuit outputs a power-off signal to the controlled switch power supply after delaying for a first preset time, and the controlled switch power supply powers off a system under the action of the power-off signal;
when the system is in a power-off state, the power-off restart control pin is switched from the first state to a second state; the control circuit controls the switch circuit to be in conductive connection with the delay circuit based on the second state of the power-off restart control pin, so that the delay circuit outputs a restart signal to the controlled switch power supply after delaying for a second preset time, and the controlled switch power supply powers on a system under the action of the restart signal.
Optionally, the control circuit comprises a comparison circuit;
the comparison circuit compares the level output by the power-off restart control pin in the first state or the second state with a preset threshold voltage according to the level, and controls the connection state of the switch circuit and the delay circuit according to the comparison result.
Optionally, the delay circuit is configured to discharge when the switching circuit is disconnected from the delay circuit, and output a power-off signal to the controlled switching power supply after the discharge is performed until the voltage is lower than a threshold voltage of an enable pin of the controlled switching power supply; the delay circuit is used for delaying the switching of the controlled switching power supply, and is also used for charging when the switching circuit is connected with the delay circuit in a conduction mode and outputting a restarting signal to the controlled switching power supply after the voltage reaches the threshold voltage;
the discharging duration is the first preset time, and the charging duration is the second preset time.
Optionally, the first state of the power-off restart control pin is a low level, and the second state is a high level;
when the power-off restart control pin is in the first state, the output level of the comparison circuit is high level, and the switch circuit is disconnected with the delay circuit; when the power-off restart control pin is in the second state, the output level is low level, and the switch circuit is connected with the delay circuit in a conduction mode.
Optionally, the comparison circuit comprises: the circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;
the non-inverting input end of the operational amplifier is connected with a first power supply through the fourth resistor, and the non-inverting input end of the operational amplifier is grounded through the fifth resistor; the output end of the operational amplifier is connected with the non-inverting input end of the operational amplifier through the third resistor;
the inverting input end of the operational amplifier is connected with the first power supply through the first resistor, and the inverting input end of the operational amplifier is grounded through the second resistor;
the input end of the comparison circuit is the inverting input end of the operational amplifier, and the output end of the comparison circuit is the output end of the operational amplifier.
Optionally, the comparison circuit further comprises: a filter circuit; the first power supply is grounded through the filter circuit.
Optionally, the switching circuit comprises: the switch tube, the sixth resistor and the seventh resistor; the output end of the switch circuit is the drain electrode of the switch tube;
the output end of the comparison circuit is connected with the grid electrode of the switch tube through the seventh resistor, the source electrode of the switch tube is connected with the second power supply, and the drain electrode of the switch tube is grounded through the sixth resistor.
Optionally, the delay circuit comprises: a current limiting resistor and a storage capacitor;
the output end of the delay circuit is one end of the storage capacitor;
the output end of the switch circuit is connected with one end of the storage capacitor through the current-limiting resistor, and the other end of the storage capacitor is grounded; the current limiting resistor is used for limiting the charging and discharging current of the storage capacitor.
Optionally, the switching tube is a MOSFET field effect tube.
In a second aspect, an embodiment of the present application further provides a delay switch driving system, including: a controller, the delay switch drive circuit of the first aspect, and a controlled switching power supply;
the controller is connected with the input end of the control circuit in the delay switch driving circuit through a power-off restart control pin;
and the output end of the delay circuit in the delay switch driving circuit is connected with an enabling pin of the controlled switch power supply.
The beneficial effect of this application is: the control circuit outputs a power-off signal to the controlled switch power supply for system power-off through a level signal output by the power-off restart control pin in a first state, the switch circuit is disconnected with the delay circuit, the delay circuit outputs the power-off signal to the controlled switch power supply for system power-off after delaying for a preset time, the power-off restart control pin is switched from the first state to a second state after the system power-off, the control circuit is connected with the delay circuit in a conducting manner according to the level signal output by the power-off restart control pin in the second state, and the delay circuit outputs a restart signal to the controlled switch power supply for system restart after delaying for the preset time, so that the system is automatically restarted after the preset time for power-off.
In the delay switch driving circuit, through the design of the delay circuit, a certain interval time exists before the system is powered off and powered on for the second time, so that the capacitive load in the system has enough time to discharge in the process of power-off restarting and before the secondary power-on, the capacitive load is completely discharged as far as possible, the normal starting of the system after the secondary power-on is ensured, and the use performance of the electronic equipment system is improved.
Secondly, the control circuit in the application adopts double threshold voltages to judge the logic state of the control signal, so that the jitter of the control signal can be effectively filtered, the hidden danger of repeated switching caused by the jitter of the control signal is avoided, and the logic stability and powerful driving capability of the level signal output to the switching circuit by the control circuit are ensured.
In addition, the switching circuit design is in the preceding one-level of delay circuit, has guaranteed the characteristic of the quick switch on and the shutoff of switch tube among the switching circuit, can not cause the signal of switch tube drive level to rise to lead to the fact the switch tube short time to be in the amplification area too slowly, has avoided the crossing loss of switch tube among the switching circuit, has also avoided other unpredictable's risks that parasitic parameter of switch tube self appears in the time of too slowly switching on and shutting off simultaneously.
Finally, in this application, the components and parts that adopt are conventional general type components and parts, have very high volume productibility and cost advantage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a delay switch driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another delay switch driving circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a delay switch driving system according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of another delay switch driving system according to an embodiment of the present application.
Icon: 100-time delay switch driving circuit; 10-a control circuit; 110-a comparison circuit; 120-a switching circuit; 130-a delay circuit; 200-a controller; 300-controlled switching power supply.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
Fig. 1 is a schematic structural diagram of a delay switch driving circuit according to an embodiment of the present disclosure; as shown in fig. 1, the delay switch driving circuit 100 includes: a control circuit 10, a switch circuit 120 and a delay circuit 130; the input end of the control circuit 10 is electrically connected with the power-off restart control pin, the output end of the control circuit 10 is electrically connected with the input end of the switch circuit 120, the output end of the switch circuit 120 is electrically connected with the input end of the delay circuit 130, and the output end of the delay circuit 130 is electrically connected with the controlled switch power supply; the control circuit 10 controls the switch circuit 120 and the delay circuit 130 to be turned off or on through a level signal output by the power-off restart control pin in the first state or the second state, so that the delay circuit 130 outputs a power-off signal or a restart signal to the controlled switching power supply to control the controlled switching power supply to be turned off and automatically restarted. The time delay circuit 130 can further control the time of the disconnection or the restart of the controlled switching power supply, thereby effectively avoiding the damage of the controlled switching power supply.
Optionally, the control circuit 10 is configured to disconnect the first state switch circuit 120 based on the power-off restart control pin from the delayed circuit 130, so that the delayed circuit 130 outputs a power-off signal to the controlled switching power supply after delaying for a first preset time, and the controlled switching power supply powers off the system under the action of the power-off signal; when the system is in a power-off state, the power-off restart control pin is switched from a first state to a second state; the control circuit 10 is in conductive connection with the delay circuit 130 based on the second state switch circuit 120 of the power-off restart control pin, so that the delay circuit 130 outputs a restart signal to the controlled switching power supply after delaying for a second preset time, and the controlled switching power supply powers on the system under the action of the restart signal.
It should be noted that the states of the power-off restart control pin may include an enabled state and an disabled state, and the level signal output by the power-off restart control pin is different corresponding to different states. Optionally, the first state of the power-off restart control pin may be an enabled state or an disabled state, when the first state of the power-off restart control pin is the enabled state, the second state of the corresponding power-off restart control pin may be the disabled state, and when the first state of the power-off restart control pin is the disabled state, the second state of the corresponding power-off restart control pin may be the enabled state. For different designs of the power-off restart control pin, the level signals corresponding to the enable states of the power-off restart control pin may also be different, for example: the level signal that the enabling state of outage restart control pin corresponds in this application is the low level, and the level that the disabling state of outage restart control pin corresponds is the high level. Of course, for different designs of the power-off restart control pin, the level signal corresponding to the enable state of the power-off restart control pin may also be a high level, and the level corresponding to the disable state of the power-off restart control pin may also be a low level.
It should be noted that, in the present application, the states of the power-off restart control pin include an enabled state and an disabled state, when the electronic device system needs to be powered off and restarted, that is, when the power-off restart control pin receives a power-off restart signal sent by the controller, the power-off restart control pin is in the enabled state, and when the electronic device system is in the power-off state, the restart state, and the working state after power-on, the power-off restart control pin is in the disabled state.
Optionally, the implementation principle of the delay switch driving circuit provided in this embodiment is as follows: when the electronic equipment system is jammed and the like and needs to be powered off and restarted, the power-off control pin receives a power-off restart signal and is in a first state (enabling state), the control circuit 10 controls the switch circuit 120 to be disconnected with the delay circuit 130 in the first state of the power-off control pin, and the delay circuit 130 outputs the power-off signal to the controlled switch power supply after delaying for a first preset time, so that the electronic equipment system controlled by the controlled switch power supply is powered off; at this time, the system power supply stops working and no longer provides power to the outside, so that the controller controlling the power-off restart control pin stops working, the power-off restart control pin is no longer controlled by the controller, the state of the power-off restart control pin is switched from the first state to the second state, and the level output by the power-off restart control pin is calculated according to the voltage-dividing resistor preset in the circuit structure at this time, meanwhile, the control circuit 10 controls the switch circuit 120 to be in conduction connection with the delay circuit 130 under the condition that the power-off restart control pin is in the second state, and the delay circuit 130 outputs a restart signal to the controlled switch power supply after delaying for the second preset time, so that the electronic equipment system controlled by the controlled switch power supply is restarted, namely, the process from one power-off to automatic restart is completed. And entering the next cycle process of automatic power-off restart until the power-off restart control pin receives the power-off restart signal again.
To sum up, according to the delay switch driving circuit provided in the embodiment of the present application, the control circuit outputs the power-off signal to the controlled switch power supply for system power-off through the power-off restart control pin in the first state, the control switch circuit is disconnected from the delay circuit, the delay circuit outputs the power-off signal to the controlled switch power supply after the delay preset time, after the system power-off, the power-off restart control pin is switched from the first state to the second state, the control circuit controls the switch circuit to be in conductive connection with the delay circuit according to the power-off restart control pin in the second state, and the delay circuit outputs the restart signal to the controlled switch power supply for system restart after the delay preset time, so that the system is automatically restarted after the power-off preset time. Through the design of the delay circuit, a certain interval time exists before the system is restarted after power failure, so that the capacitive load in the system can be completely discharged before the system is restarted, the damage of the controlled switching power supply is avoided, and the use performance of the electronic equipment system is improved.
Further, the control circuit 10 may include a comparison circuit 110; the comparison circuit 110 compares the level output by the power-off restart control pin in the first state or the second state with a preset threshold voltage, and controls the connection state of the switch circuit 120 and the delay circuit 130 according to the comparison result.
Optionally, the preset threshold voltage may include: the first preset threshold voltage or the second preset threshold voltage, where the first preset threshold voltage may be smaller than the second preset threshold voltage, and the first preset threshold voltage and the second preset threshold voltage may be obtained according to an actual circuit structure of the control comparison circuit 110.
Optionally, in the present application, the comparison circuit 110 uses a hysteresis comparator to determine the logic state of the control level signal output by the power-off restart control pin, so as to effectively filter jitter of the control signal, and ensure logic stability and powerful driving capability of the level signal output by the comparison circuit 110 to the switch circuit 120.
In some embodiments, the comparison circuit 110 compares the first level output by the power-off restart control pin in the first state with a first preset threshold voltage according to the first level output by the power-off restart control pin in the first state, and according to the comparison principle of the hysteresis comparator, since the first level output by the power-off restart control pin in the first state is a low level, which is smaller than the first preset threshold voltage, at this time, the output level of the comparison circuit 110 is a high level, and the switch circuit 120 is disconnected from the delay circuit 130; in other embodiments, the comparison circuit 110 compares the second level output by the power-off restart control pin in the second state with a second preset threshold voltage, and since the second level output by the power-off restart control pin in the second state is a high level, which is greater than the second preset threshold voltage, at this time, the output level of the comparison circuit 110 is a low level, and the switch circuit 120 is in conductive connection with the delay circuit 130.
The control circuit 10 controls the switch circuit 120 to be disconnected with the delay circuit 130 in a first state of the power-off restart control pin, the delay circuit 130 outputs a power-off signal to the controlled switch power supply, at this time, the controlled switch power supply is powered off and no power is supplied to the controlled switch power supply, the power-off restart control pin is switched from the first state to a second state, at this time, the control circuit 10 controls the switch circuit 120 to be connected with the delay circuit 130 in a conducting manner based on a level signal output by the power-off restart control pin, and the delay circuit 130 outputs a restart signal to the controlled switch power supply, so that the power-off and automatic restart processes of the controlled switch power supply under the actions of the power-off restart control pin, the control circuit 10, the switch circuit 120 and the delay circuit 130 are.
Optionally, the delay circuit 130 is configured to discharge when the switch circuit 120 is disconnected from the delay circuit 130, and output a power-off signal to the controlled switching power supply after discharging until the voltage is lower than the threshold voltage of the enable pin of the controlled switching power supply; and is further configured to charge when the switching circuit 120 is in conductive connection with the delayed circuit 130, and output a restart signal to the controlled switching power supply after the charging is performed until the voltage reaches the threshold voltage.
The discharging time is a first preset time, and the charging time is a second preset time. That is, when the discharge time reaches the first preset time, the voltage of the delay circuit 130 reaches the requirement that the voltage is lower than the threshold voltage of the enable pin of the controlled switching power supply, so that the delay circuit can send a power-off signal to the controlled switching power supply; when the charging time reaches the second preset time, the voltage of the delay circuit 130 reaches a requirement that the voltage is higher than the threshold voltage of the enable pin of the controlled switching power supply, so that a restart signal can be sent to the controlled switching power supply.
It should be noted that, in the present application, a delay circuit 130 is further cascaded at the next stage of the control circuit 10 and the switch circuit 120, so that when the controlled switching power supply is controlled to power off, a power-off signal is output again through a certain delay, and when the controlled switching power supply is controlled to restart, a restart signal is output again through a certain delay, so that a capacitive load in the system can be completely discharged when the system is restarted after the power off, thereby avoiding a risk that the system cannot be normally started due to incomplete system discharge before secondary power on of the system, and ensuring stability of system restart.
Optionally, in this application, the first state of the power-off restart control pin is a low level, and the second state is a high level; when the power-off restart control pin is in the first state, the output level of the comparison circuit 110 is high level, and the switch circuit 120 is disconnected from the delay circuit 130; when the power-off restart control pin is in the second state, the output level is low, and the switch circuit 120 is connected to the delay circuit 130 in a conductive manner.
It should be noted that, when the power-off restart control pin is in the first state (the enabled state, the low level), the input level of the comparison circuit 110 is the low level, and the comparison result between the low level and the first preset threshold voltage makes the output of the comparison circuit 110 be the high level, at this time, the switch circuit 120 is disconnected from the delay circuit 130, the delay circuit 130 outputs the power-off signal to the controlled switching power supply, and the controlled switching power supply is powered off and stops working. At this time, the controlled switching power supply no longer provides power to the outside, the controller controlling the power-off restart control pin stops working, the power-off restart control pin is switched from the first state to the second state (the disabled state, the high level), and the comparison result of the high level and the second preset threshold voltage enables the output of the comparison circuit 110 to be the low level, at this time, the switching circuit 120 is in conductive connection with the delay circuit 130, the delay circuit 130 outputs a restart signal to the controlled switching power supply, and the controlled switching power supply is powered off and works again. Thereby completing the power-off and automatic restart of the system.
Fig. 2 is a schematic structural diagram of another delay switch driving circuit provided in the embodiment of the present application, and as shown in fig. 2, the comparing circuit 110 includes: an operational amplifier U1A, an inverting input circuit, a non-inverting input circuit, and a feedback circuit; the input end of the comparison circuit 110 is the inverting input end of the operational amplifier U1A, and the output end of the comparison circuit 110 is the output end of the operational amplifier U1A; the input voltage of the comparator circuit 110 is the voltage at the inverting input of the operational amplifier U1A.
The inverting input terminal of the operational amplifier U1A is connected to the inverting input circuit, the non-inverting input terminal of the operational amplifier U1A is connected to the non-inverting input circuit, and the output terminal of the operational amplifier U1A is connected to the non-inverting input terminal through the feedback circuit.
Wherein, the inverting input circuit includes: a first resistor and a second resistor; the inverting input terminal of the operational amplifier U1A is connected to the first power supply through a first resistor, and the inverting input terminal of the operational amplifier U1A is also connected to ground through a second resistor. The non-inverting input circuit includes: a fourth resistor and a fifth resistor; the non-inverting input terminal of the operational amplifier U1A is connected to the first power supply through a fourth resistor, and the non-inverting input terminal of the operational amplifier U1A is further connected to ground through a fifth resistor. The feedback circuit includes: a third resistor; the output terminal of the operational amplifier U1A is connected to the non-inverting input terminal of the operational amplifier U1A through a third resistor.
As can be seen from the above description, the input terminal of the comparison circuit 110 is connected to the power-off restart control pin, and when the electronic device system has a card jamming state due to a fault, the power-off restart control pin is changed to automatically restart the system when the system is powered off, so that the system can normally operate.
Optionally, when the system triggers the power-off restart signal, the power-off restart control pin is in the first state, and outputs a low-level signal, that is, the input end of the comparison circuit 110 receives the low-level signal, the input voltage is 0V, and compares the input voltage with a first preset threshold voltage, where the input voltage is lower than the first preset threshold voltage of the reverse input end of the operational amplifier U1A, and at this time, the output of the operational amplifier U1A is at a high level, so that the switching circuit 120 is disconnected from the delay circuit 130, the delay circuit 130 outputs a power-off signal to the controlled switching power supply, and the controlled switching power supply stops working when the power-off restart signal is triggered. At this time, the controlled switching power supply does not provide power to the outside any more, the controller controlling the power-off restart control pin stops working, the power-off restart control pin is switched from the first state to the second state, at this time, the input voltage of the comparison circuit 110 is calculated according to the divided voltage of the first resistor and the second resistor, the calculated input voltage of the comparison circuit 110 is higher than the second preset threshold voltage, the level signal output by the power-off restart control pin is a high level, at this time, the output end of the comparison circuit 110 outputs a low level signal, so that the switching circuit 120 is in conductive connection with the delay circuit 130, and the delay circuit 130 outputs a restart signal to the controlled switching power supply, so that the controlled switching power supply is switched from the power-off state to the restart state.
The preset threshold voltage may be calculated according to a threshold reference voltage (reference voltage) and a jitter range of an estimated signal high-low level (i.e., signal noise amplitude) of an actual circuit, where the preset threshold voltage includes a first preset threshold voltage (low threshold voltage) or a second preset threshold voltage (high threshold voltage). When the input voltage of the comparison circuit 110 is lower than the low threshold voltage, the output level of the comparison circuit 110 is at a high level, and when the input voltage of the comparison circuit 110 is higher than the high threshold voltage, the output level of the comparison circuit 110 is at a low level. Alternatively, when the output level of the comparison circuit 110 is high level, the switch circuit 120 is disconnected from the delay circuit 130, and when the output level of the comparison circuit 110 is low level, the switch circuit 120 is connected to the delay circuit 130.
In the present application, when the logic state of the control signal is determined, the operational amplifier U1A is a hysteresis comparator, and compared with a single logic determination threshold, the hysteresis comparator uses a dual determination threshold, where the dual determination threshold includes a high threshold voltage and a low threshold voltage, which avoids frequent jitter of signals and continuous jump of the level output by the control circuit 10 during the voltage comparison process, which causes the repeated disconnection and connection of the switch circuit 120, and causes the unstable operation of the whole delay switch driving circuit 100. That is, in the present application, by using the hysteresis comparator, jitter of the control signal can be effectively filtered, and logic stability and powerful driving capability of the driving signal output to the post-stage switch circuit 120 are ensured. In addition, considering the output state of the comparator after power-off and the practical structure of the comparison circuit 110 in this embodiment, the comparator is a hysteresis comparator with a clockwise structure, and the logic of power-off and restart meets the practical requirements. Meanwhile, the basic operational amplifier U1A constituting the comparator needs to select a device with rail-to-rail voltage output characteristics, so that the switching circuit 120 of the subsequent stage partially satisfies a completely closed state under the condition of ensuring high-level output.
Of course, when the logic of the present application is implemented, it is not limited to select the clockwise hysteresis comparator, and in some cases, the counterclockwise hysteresis comparator may also be selected, and accordingly, the resistance values of the elements in the comparison circuit 110 need to be adjusted, so as to satisfy the control of the comparison circuit 110 on the connection state of the switch circuit 120 and the delay circuit 130.
Optionally, the high threshold voltage and the low threshold voltage may be calculated according to the estimated voltage noise range and the reference voltage, and further, the resistance values of the corresponding third resistor R3, the fourth resistor R4, and the fifth resistor R5 may be calculated by matching according to the calculated threshold voltage and the calculated low threshold voltage. The reference voltage may be calculated according to a preset high level voltage and a preset low level voltage. In general, the corresponding high level voltage is different for different circuit structures, and the delay switch driving circuit 100 provided by the present application sets the high level voltage VCCIs 3.3V, and has a low level voltage VEEAt 0V, the intermediate value between the high voltage and the low level voltage can be used as the reference voltage, i.e. as the reference voltageThat is, in this embodiment, the reference voltage may be 1.65V. Alternatively, for the calculation of the reference voltage, the adaptive adjustment may be performed by using the high-level voltage and the low-level voltage of the actual circuit, and is not limited herein.
Alternatively, the high and low threshold voltages may be determined based on the magnitude of noise that may be present in the circuit signal, and a reference voltage of the circuit.
Optionally, in the delay switch driving circuit 100 provided in the present application, according to an actual condition of the circuit, the estimated noise amplitude obtained from the circuit is 1V, and thus, correspondingly, the high threshold voltage U is setaCan be 2.65V, and has low threshold voltage UbMay be 0.65V.
Accordingly, the high threshold voltage U is determinedaAnd a low threshold voltage UbThen, the magnitudes of the resistances of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be further calculated, so that the magnitudes of the resistances of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be calculated to set the magnitudes of the resistances of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 in the comparison circuit 110, so that the high threshold voltage and the low threshold voltage satisfy the high threshold voltage U determined as abovea2.65V, low threshold voltage UbIt was 0.65V.
For the comparison circuit 110 in the delay switch driving circuit 100 provided in the present application, a calculation formula of the positive feedback coefficient K in the basic structure of the conventional hysteresis operational amplifier U1A can be derived according to the following equation:
in addition, according to the fluctuation range U of the threshold voltageWD＝Ua-Ub＝(VCC+VEE) K, so that K3.3 — 2 can be obtained, and the K value can be calculated, and further, the resistance values of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 can be adaptively matched according to the calculation relationship between the K value and the third resistor R3, the fourth resistor R4 and the fifth resistor R5, wherein the third resistor R3, the fourth resistor R4 and the fifth resistor R5The resistance of the resistor R5 is not unique as long as the relation is satisfied
And (4) finishing.
In addition, it should be noted that, for different circuits, the corresponding estimated noise amplitudes are different, so that the determined high threshold voltage and low threshold voltage are also different, and the resistance values of the corresponding matched third resistor R3, fourth resistor R4, and fifth resistor R5 are also different, which is specifically determined according to the actual circuit.
After the input voltages of the operational amplifier U1A corresponding to the high threshold voltage, the low threshold voltage and different control signals are obtained, the voltage values may be compared, so as to obtain an output level signal of the operational amplifier U1A according to the comparison result, and accordingly control the connection states of the switching circuit 120 and the delay circuit 130 at the subsequent stage.
Wherein, when the power-off restart control pin is in a non-enabled (high level) state, the input voltage U of the operational amplifier U1A2Calculated from the first resistor R1 and the second resistor R2 and calculated from the power supply voltage as described above. When the power-off restart control pin is in an enabling (low level) state, the input voltage U of the operational amplifier U1A2Is 0, by adding U2Respectively compared with the calculated high threshold voltage and low threshold voltage, U2When the voltage is higher than the high threshold voltage, the output level of the operational amplifier U1A is the low level, U2When the voltage is less than the low threshold voltage, the output level of the operational amplifier U1A is high.
Further, the comparison circuit 110 further includes: a filter circuit; the power supply is also connected to ground through a filter circuit.
In some embodiments, the filter circuit may include a capacitor C1 for filtering the voltage output from the power pin, and the filter capacitor C1 is an energy storage device for reducing the ripple factor of the ac voltage and smoothing the dc output. The filter capacitor C1 not only can stabilize the DC output of the power supply, reduce the influence of alternating ripple on the electronic circuit, but also can absorb the current fluctuation generated in the working process of the electronic circuit and the interference of the AC power supply in series, so that the working performance of the electronic circuit is more stable.
Further, as shown in fig. 2, the switching circuit 120 may include: a switching tube Q1, a sixth resistor R6 and a seventh resistor R7; the output end of the switching circuit 120 is the drain of the switching tube Q1; the output end of the comparison circuit 110 is connected with the grid electrode of the switching tube Q1; the output terminal of the comparator circuit 110 is connected to the gate of the switching transistor Q1 through a seventh resistor R7. The source of the switching tube Q1 is connected to the second power supply, and the drain of the switching tube Q1 is grounded through a sixth resistor R6.
Optionally, when the power-off restart control pin is in the first state, in the comparison circuit 110, when the output level of the operational amplifier U1A is a high level, the switching tube Q1 is turned off, and the switching circuit 120 is disconnected from the delay circuit 130; when the power-off restart control pin is switched from the first state to the second state, and the output level of the operational amplifier U1A is at a low level, the switch Q1 is turned on, and at this time, the switch circuit 120 is connected to the delay circuit 130 in a conductive manner. In addition, the drain of the switching tube Q1 is grounded through the sixth resistor R6, and the sixth resistor R6 plays a role in current limiting when the switching tube Q1 is turned on.
It should be noted that, with reference to the specific structure of the switching tube Q1 in fig. 2, the switching tube Q1 is turned off, that is, the source 3 and the drain 2 of the switching tube Q1 are turned off, and correspondingly, the switching tube Q1 is turned on, that is, the source 3 and the drain 2 of the switching tube Q1 are turned on.
Optionally, the seventh resistor R7 is used to perform a current limiting function, so as to make the switching circuit 120 more stable, thereby ensuring that the switching tube Q1 can be turned on or off stably.
Further, as shown in fig. 2, the delay circuit 130 may include: a current limiting resistor R8 and a storage capacitor C2; the output end of the delay circuit 130 is one end of the storage capacitor C2; the output end of the switch circuit 120 is connected with one end of a storage capacitor C2 through a current-limiting resistor R8, and the other end of the storage capacitor C2 is grounded; the current limiting resistor R8 is used for limiting the charging and discharging current of the storage capacitor C2.
The storage capacitor R8 is used for discharging when the switching circuit 120 is disconnected from the delay circuit 130, and outputting a power-off signal to the controlled switching power supply after the discharging reaches a first preset time; and is further configured to charge when the switching circuit 120 is conductively connected to the delay circuit 130, and output a restart signal to the controlled switching power supply after the charging reaches a second preset time.
Optionally, in order to enable the capacitive load in the electronic device system to be completely discharged before the controlled switching power supply is powered off and restarted, and avoid damage caused by direct restart of the controlled switching power supply, in this application, a delay circuit 130 is further cascaded at a stage subsequent to the switching circuit 120 to ensure that the controlled switching power supply is turned off or restarted at a preset time, so as to improve the service performance of the system.
The first predetermined time is the time when the capacitor C2 discharges to a voltage lower than the threshold voltage of the enabling pin of the controlled switching power supply, and the second predetermined time is the time when the capacitor C2 charges to a voltage higher than the threshold voltage of the enabling pin of the controlled switching power supply. Optionally, when the switch circuit 120 is disconnected from the delay circuit 130, the capacitor C2 discharges, and when the capacitor C2 discharges to a voltage lower than the threshold voltage value of the enable pin of the controlled switching power supply, the delay circuit 130 outputs a power-off signal to the controlled switching power supply. When the switch circuit 120 is connected to the delay circuit 130, the capacitor C2 is charged, and when the capacitor C2 is charged to a voltage higher than the threshold voltage of the enable pin of the controlled switching power supply, the delay circuit 130 outputs a restart signal to the controlled switching power supply. Thereby causing the controlled switching power supply to switch from the power-off state to the restart state. In the process of charging the capacitor C2, other capacitive loads in the electronic device system are in the process of discharging, so that it is ensured that the other loads in the system are completely discharged after the controlled switching power supply is powered off until the controlled switching power supply is restarted (secondary power-on), and further the stability of restarting the system is ensured.
Further, the switching tube Q1 is a MOSFET field effect tube.
Optionally, in this embodiment, the switching transistor Q1 is a P-type MOS transistor, which has a large load current, a fast response rate, and a small structure, and the overall structure of the delay switch driving circuit 100 of the present application is considered comprehensively, and it is more appropriate to select the MOS transistor. However, the selection of the switching transistor Q1 is not limited to the P-type MOS transistor, for example: an N-type MOS transistor, an IGBT switching transistor Q1, or the like may be used as the switching transistor Q1 in the present application.
Optionally, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the current limiting resistor R8 related to the above embodiments of the present application may be formed by an independent resistor, or formed by connecting a plurality of resistors in series or in parallel, or formed by connecting other circuit elements, where the resistance of the formed resistor satisfies a preset resistance requirement, and the present application is not limited specifically.
Similarly, the filter capacitor C1 and the storage capacitor C2 may be formed by a single capacitor, or by a plurality of capacitors connected in series or in parallel, and the formation of the filter capacitor C1 and the storage capacitor C2 is the same as that of the above resistors, and is not limited in this respect.
Optionally, the MOSFET switch Q1 is placed at the previous stage of the delay circuit 130, so that the fast turn-on and turn-off characteristics of the MOSFET used as a switch are ensured, and the short-time amplification of the power transistor in the amplification region due to the slow rise of the signal of the power transistor driving stage is avoided, and the crossover loss of the switch Q1 is increased. Meanwhile, other unpredictable risks caused by the existence of parasitic parameters of the power tube are avoided during the slow switching-on and switching-off period.
In order to solve the problem that secondary power-on is abnormal due to incomplete discharge after power failure, the power-on switch adopts the MOSFET as the main body of the switch, and combines the delay circuit 130 as the structure of the output stage of switch control, so that the large-current discharge of the output stage of the switch is well realized in the power-off state. The discharge speed is increased as much as possible, and the rapid turn-off of the controlled switching power supply is ensured. On the other hand, after the power is off, the MOSFET switch controlled by the hardware state is in the on state, the power supply controls the time when the level of the output end reaches the preset power-on enabling level value through the delay circuit 130, and during the time of the delay, the system performs the sufficient discharge process after the power is off, so as to ensure the normal power-on process of the next time.
The working process of the overall circuit of the delay switch driving circuit 100 provided by the present application is as follows:
the working process of the whole circuit is started when the comparison circuit 110 receives a control signal output by the power-off restart control pin in a first state (enabling state), and when the control signal output is in a low level (namely, the input of the input end of the comparison circuit 110 is in a low level), because the hysteresis comparator in the application adopts a clockwise hysteresis comparator, the output end of the comparison circuit 110 is in a high level at the moment. Meanwhile, the operational amplifier U1A is an amplifier with a rail-to-rail voltage output characteristic, so that the voltage difference between the high level output by the comparison circuit 110 and the source voltage of the switch tube Q1 in the switch circuit 120 is minimum, and the Q1 is in a completely turned-off state when the Q1 outputs the high level output by the comparison circuit 110, at the moment, the switch circuit 120 is disconnected from the delay circuit 130, the sixth resistor R6, the current-limiting resistor R8 and the capacitor C2 form a discharge loop, and the voltage value of the positive electrode of the capacitor C2 is continuously reduced in the continuous discharge process of the capacitor C2. When the voltage value of the positive electrode of the capacitor C2 is reduced to be lower than the threshold voltage value of the enable pin (EN pin) of the rear-stage controlled switching power supply, the delay circuit 130 outputs a power-off signal to the controlled switching power supply, the rear-stage power supply stops working and does not output externally, the controller of the power-off restart control pin is controlled to stop working when the power-off restart control pin is switched from the enable state to the disable state, and at the moment, the control signal is not controlled by the controller and is controlled by the voltage division of the first resistor R1 and the second resistor R2. The level at which the control signal is at this time belongs to the power supply obtained by the voltage division of the first resistor R1 and the second resistor R2. The values of the first resistor R1 and the second resistor R2 need to match corresponding values according to a preset threshold voltage of the non-inverting input terminal of the operational amplifier U1A, it is ensured that the input voltage value of the divided comparator circuit 110 is greater than the high threshold voltage of the operational amplifier U1A, at this time, the output of the operational amplifier U1A is at a high level, the post-stage switch circuit 120 is connected with the delay circuit 130 in a conductive manner, the delay circuit 130 can be normally charged, when the capacitor C2 in the delay circuit 130 is charged until the voltage reaches a value above the threshold voltage value of the post-stage controlled switch power enable pin (EN pin), the delay circuit 130 outputs a restart signal to the controlled switch power, the post-stage power is normally started, and thus the process of automatically restarting the system after a certain time from power-off to time delay is completed.
To sum up, the delay switch drive circuit that this application embodiment provided, the level signal that control circuit exported under the first state through outage restart control pin, switch circuit and delay circuit disconnection, delay circuit exports outage signal in the time delay after presetting time in order to carry out the system outage to the controlled switch power, after the system outage, outage restart control pin switches over to the second state from the first state, control circuit restarts the level signal that control pin exported under the second state according to the outage, switch circuit and delay circuit conducting connection, delay circuit exports restart signal in the time delay after presetting time in order to carry out the system restart to the controlled switch power, thereby make the system restart automatically after the time is preset in the outage. Through the design of the delay circuit, a certain interval time exists before the system is restarted after power failure, so that the capacitive load in the system can be completely discharged before the system is restarted, the damage of the controlled switching power supply is avoided, and the use performance of the electronic equipment system is improved. Secondly, the control circuit in the application adopts the hysteresis comparator to distinguish the logic state of the control signal, so that the jitter of the control signal can be effectively filtered, and the logic stability and powerful driving capability of the level signal output to the switching circuit by the control circuit are ensured. In addition, the switching circuit design is in the preceding level of delay circuit, has guaranteed that MOSFET field effect transistor uses as the switch fast turn-on and the characteristic of turn-off, can not cause because the signal of power tube drive level rises to lead to the fact the power tube short time to be in the amplification area too slowly, increases the crossing loss of switch tube, has also avoided simultaneously because the existence of the parasitic parameter of power tube self, in the too slow conduction with turn-off period, other unpredictable's risks appear. Finally, in this application, the components and parts that adopt are conventional general type components and parts, have very high volume productibility and cost advantage.
Fig. 3 is a schematic diagram of a delay switch driving system according to an embodiment of the present application, and fig. 4 is a schematic diagram of another delay switch driving system according to an embodiment of the present application; as shown in fig. 3, the delay switch driving system provided in the embodiment of the present application includes: a controller 200, the delay switch driving circuit 100 and a controlled switch power supply 300; as shown in fig. 4, the controller 200 is connected to the input terminal of the control circuit 10 in the delay switch driving circuit 100 through the power-off restart control pin; the output terminal of the delay circuit 130 in the delay switch driving circuit 100 is connected to the enable pin of the controlled switching power supply 300.
Specifically, the function implementation principle of the delay switch driving system has been specifically explained in the foregoing explanation of the operation principle of the delay switch driving circuit 100, and is not repeated here.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Claims (10)
1. A time delay switch drive circuit, comprising: the control circuit, the switch circuit and the delay circuit;
the input end of the control circuit is electrically connected with the power-off restart control pin, the output end of the control circuit is electrically connected with the input end of the switch circuit, the output end of the switch circuit is electrically connected with the input end of the delay circuit, and the output end of the delay circuit is electrically connected with the controlled switch power supply;
the control circuit is used for controlling the switch circuit to be disconnected with the delayed circuit based on the first state of the power-off restart control pin, so that the delayed circuit outputs a power-off signal to the controlled switch power supply after delaying for a first preset time, and the controlled switch power supply powers off a system under the action of the power-off signal;
when the system is in a power-off state, the power-off restart control pin is switched from the first state to a second state; the control circuit controls the switch circuit to be in conductive connection with the delay circuit based on the second state of the power-off restart control pin, so that the delay circuit outputs a restart signal to the controlled switch power supply after delaying for a second preset time, and the controlled switch power supply powers on a system under the action of the restart signal.
2. The circuit of claim 1, wherein the control circuit comprises a comparison circuit;
the comparison circuit compares the level output by the power-off restart control pin in the first state or the second state with a preset threshold voltage according to the level, and controls the connection state of the switch circuit and the delay circuit according to the comparison result.
3. The circuit of claim 1, wherein the delay circuit is configured to discharge when the switching circuit is disconnected from the delay circuit and output a power-down signal to the controlled switching power supply after discharging to a voltage lower than a threshold voltage of an enable pin of the controlled switching power supply; the delay circuit is used for delaying the switching of the controlled switching power supply, and is also used for charging when the switching circuit is connected with the delay circuit in a conduction mode and outputting a restarting signal to the controlled switching power supply after the voltage reaches the threshold voltage;
the discharging duration is the first preset time, and the charging duration is the second preset time.
4. The circuit of claim 2, wherein the first state of the power-down restart control pin is a low level, and the second state is a high level;
when the power-off restart control pin is in the first state, the comparison circuit outputs a high level, and the switch circuit is disconnected with the delay circuit; when the power-off restart control pin is in the second state, the output level is low level, and the switch circuit is in conductive connection with the delay circuit.
5. The circuit of claim 2, wherein the comparison circuit comprises: the circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;
the non-inverting input end of the operational amplifier is connected with a first power supply through the fourth resistor, and the non-inverting input end of the operational amplifier is grounded through the fifth resistor; the output end of the operational amplifier is connected with the non-inverting input end of the operational amplifier through the third resistor;
the inverting input end of the operational amplifier is connected with the first power supply through the first resistor, and the inverting input end of the operational amplifier is grounded through the second resistor;
the input end of the comparison circuit is the inverting input end of the operational amplifier, and the output end of the comparison circuit is the output end of the operational amplifier.
6. The circuit of claim 5, wherein the comparison circuit further comprises: a filter circuit; the first power supply is grounded through the filter circuit.
7. The circuit of claim 6, wherein the switching circuit comprises: the switch tube, the sixth resistor and the seventh resistor; the output end of the switch circuit is the drain electrode of the switch tube;
the output end of the comparison circuit is connected with the grid electrode of the switch tube through the seventh resistor, the source electrode of the switch tube is connected with the second power supply, and the drain electrode of the switch tube is grounded through the sixth resistor.
8. The circuit of any of claims 1-4, wherein the delay circuit comprises: a current limiting resistor and a storage capacitor;
the output end of the delay circuit is one end of the storage capacitor;
the output end of the switch circuit is connected with one end of the storage capacitor through the current-limiting resistor, and the other end of the storage capacitor is grounded; the current limiting resistor is used for limiting the charging and discharging current of the storage capacitor.
9. The circuit of claim 7 wherein said switching transistor is a MOSFET field effect transistor.
10. A time delay switch drive system, comprising: a controller, a time delay switch drive circuit, a controlled switching power supply as claimed in any one of claims 1 to 9;
the controller is connected with the input end of the control circuit in the delay switch driving circuit through a power-off restart control pin;
and the output end of the delay circuit in the delay switch driving circuit is connected with an enabling pin of the controlled switch power supply.
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| CN201921624079.XU CN210225248U (en) | 2019-09-26 | 2019-09-26 | Time delay switch driving circuit and system |
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| CN201921624079.XU CN210225248U (en) | 2019-09-26 | 2019-09-26 | Time delay switch driving circuit and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110535336A (en) * | 2019-09-26 | 2019-12-03 | 重庆市亿飞智联科技有限公司 | Delay switch driving circuit and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110535336A (en) * | 2019-09-26 | 2019-12-03 | 重庆市亿飞智联科技有限公司 | Delay switch driving circuit and system |
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