CN110676215A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN110676215A CN110676215A CN201910961381.2A CN201910961381A CN110676215A CN 110676215 A CN110676215 A CN 110676215A CN 201910961381 A CN201910961381 A CN 201910961381A CN 110676215 A CN110676215 A CN 110676215A
- Authority
- CN
- China
- Prior art keywords
- gate
- inversion
- heavily doped
- contact hole
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 72
- 210000000746 body region Anatomy 0.000 claims description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 10
- 230000009969 flowable effect Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000005368 silicate glass Substances 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 95
- 150000002500 ions Chemical class 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- -1 phosphorus Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供了一种半导体器件及其制造方法,以介质层为掩膜,刻蚀回刻蚀槽周围的同型重掺杂区和下方的部分厚度的反型体区,来形成所需深度的接触孔,这实质上是一种自对准接触孔刻蚀工艺,因此,基本上不会因工艺波动而产生接触孔对准偏移的问题,进而保证了接触孔和栅极沟槽有非常高的对准精度,避免了后续接触孔内注入的杂质离子在退火后会扩散到沟道区域的问题,进而改善半导体器件的性能。此外,由于是一种自对准接触孔刻蚀工艺,因此无需光罩掩膜版辅助即可刻蚀接触孔,继而可以省去一张光罩掩膜版,降低生产成本。
Description
技术领域
本发明涉及半导体制造技术领域,特别涉及一种半导体器件及其制造方法。
背景技术
目前,IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)以及VDMOS(Vertical Double-diffused MOSFET,垂直沟道双扩散型金属氧化物晶体管)的技术不断革新,在实现功率半导体器件的尺寸的不断缩小的前提下,还保证了功率半导体器件的优异性能。
在现有的沟槽型IGBT晶体管的制作过程中,需要在沟槽型栅极完成后,借助光刻工艺将接触孔的设计图形从掩膜版转移到晶圆上,但是在进行图形转移时,需要将掩膜版上的光刻对准标记与前面形成的有源区或栅极沟槽的层次上留下的光刻对准标记(alignment mark)进行对齐,以确保形成的接触孔与栅极沟槽的间距满足设计尺寸。
随着器件尺寸的不断缩小,有源区的尺寸需要不断缩小,设计端给接触孔和栅极沟槽预留的关键尺寸(CD size)也随之逐渐变小,由于接触孔对应的光刻工艺制程不可避免地需要考虑到与栅极沟槽的对准精度,因此,对于小尺寸的器件结构而言,工艺间的波动极有可能会造成接触孔到栅极沟槽的间距偏小,接触孔内注入的杂质离子在退火后会扩散到沟道区域,增强了沟道区域中的杂质掺杂浓度,继而使得IGBT晶体管的阈值电压提高,并影响了最终制得的半导体器件的性能。
发明内容
本发明的目的在于提供一种半导体器件及其制造方法,能够保证接触孔和栅极沟槽的对准精度,避免接触孔内注入的杂质离子在退火后会扩散到沟道区域,进而改善半导体器件的性能。
为实现上述目的,本发明提供了一种半导体器件的制造方法,包括以下步骤:
S1,提供半导体衬底,并刻蚀所述半导体衬底,以形成栅极沟槽于所述半导体衬底中;
S2,形成栅极于所述栅极沟槽中,并回刻蚀所述栅极至所述栅极沟槽内一定深度,以形成回刻蚀槽;
S3,形成反型掺杂区和同型重掺杂区于所述栅极沟槽周围的半导体衬底中;
S4,填充在预设温度下可流动的介质材料于所述回刻蚀槽中并回流,以形成介质层,所述介质层填满所述回刻蚀槽并露出所述回刻蚀槽周围的同型重掺杂区的表面;
S5,以所述介质层为掩膜,刻蚀所述回刻蚀槽周围的同型重掺杂区和所述同型重掺杂区下方的反型体区,以形成接触孔;
S6,形成接触插塞于所述接触孔中。
可选地,在步骤S1中,刻蚀所述半导体衬底而形成的所述栅极沟槽的数量不少于两个;在步骤S5中,形成的所述接触孔位于相应的两个相邻的所述栅极沟槽之间,且所述接触孔的顶部开口的宽度等于两个相邻的所述栅极沟槽之间的间距。
可选地,在步骤S5中,形成的所述接触孔为倒梯形结构,所述接触孔的顶部开口的宽度大于所述接触孔的底部开口的宽度。
可选地,在步骤S2中,形成栅极于所述栅极沟槽中之前,先形成栅槽底部氧化物或者多晶硅屏蔽栅填充于所述栅极沟槽的底部,当形成多晶硅屏蔽栅填充于所述栅极沟槽的底部时,所述多晶硅屏蔽栅和所述栅极之间夹有绝缘层。
可选地,在步骤S3中,先对所述栅极沟槽周围的半导体衬底进行反型离子注入,再对所述栅极沟槽周围的半导体衬底进行同型离子注入,所述同型离子注入的深度深于所述栅极沟槽中的栅极的顶面。
可选地,在步骤S3中,所述反型离子注入的工艺参数包括:注入深度为2μm~4μm,工艺温度为1000℃~1200℃;所述同型离子注入的深度为0.2μm~1μm。
可选地,在步骤S4中填充的所述可流动的介质材料包括硅酸盐玻璃、正硅酸乙酯、旋涂玻璃(SOG)和聚合物材料中的至少一种。
可选地,所述的半导体器件的制造方法,在步骤S6之前且在步骤S5之后,还包括:在所述接触孔底部再次进行反型离子注入并进行低于所述预设温度的退火处理,以在所述接触孔的底部形成反型阻挡层,所述反型阻挡层与所述反型体区同型,且将所述反型体区和所述同型重掺杂区短接。
可选地,所述的半导体器件的制造方法,在步骤S6之后,还包括:依次形成金属电极层和钝化层,所述金属电极层覆盖于所述接触插塞、所述同型重掺杂区和所述介质层上,所述钝化层覆盖于所述金属电极层上。
基于同一发明构思,本发明还提供一种半导体器件,采用本发明所述的半导体器件的制造方法制造,所述半导体器件包括:
半导体衬底,所述半导体衬底中形成有栅极沟槽;
栅极和介质层,依次填充于所述栅极沟槽中,且所述介质层位于所述栅极上方;
反型体区和同型重掺杂区,均位于所述栅极沟槽周围的半导体衬底中;
接触插塞,贯穿所述同型重掺杂区且底面伸入到所述同型重掺杂区下方的所述反型体区中。
与现有技术相比,本发明的技术方案具有以下有益效果:
1、以介质层为掩膜,刻蚀回刻蚀槽周围的同型重掺杂区和下方的部分厚度的反型体区,来形成所需深度的接触孔,这实质上是一种自对准接触孔刻蚀工艺,因此,基本上不会因工艺波动而产生接触孔对准偏移的问题,进而保证了接触孔和栅极沟槽有非常高的对准精度,避免了后续接触孔内注入的杂质离子在退火后会扩散到沟道区域的问题,进而改善半导体器件的性能。此外,由于是一种自对准接触孔刻蚀工艺,因此无需光罩掩膜版辅助即可刻蚀接触孔,继而可以省去一张光罩掩膜版,降低生产成本。
2、由于采用一定温度下可流动的介质材料填充回刻蚀槽,因此可以改善形成的介质层在各个区域的厚度一致性,降低高度差,由此,在接触孔刻蚀时,能够保证形成的接触孔的深度一致性;进一步地,当在填充接触插塞后将接触插塞的顶部平坦化至半导体衬底的顶面上,回刻蚀槽中仍有足够厚的介质层,由此保证了接触插塞及其上方的金属电极层分别与栅极之间的绝缘性。
3、形成反型体区和同型重掺杂区的操作均在将可流动的介质材料填充回刻蚀槽的操作之前进行,可以避免在介质层填满回刻蚀槽之后再做高能量注入和高温热过程,进而避免某些高能量注入和高温热过程会影响介质层的绝缘性能的问题。
4、在形成接触孔之后且在填充接触插塞之前,在所述接触孔底部再次进行反型离子注入,以在所述接触孔的底部形成反型阻挡层,通过所述反型阻挡层将所述反型体区和所述同型重掺杂区短接,以将寄生晶体管进行短路,避免器件栓锁失效,并降低接触孔内接触电阻。
附图说明
图1是本发明一实施例的半导体器件的制造方法的流程图;
图2A至2G是本发明一实施例的半导体器件的制造方法中的器件剖面结构示意图;
图3是本发明一实施例的半导体器件的器件剖面结构示意图;
图4是本发明另一实施例的半导体器件的器件剖面结构示意图。
具体实施方式
为使本发明的目的、优点和特征更加清楚,以下结合附图对本发明提出的技术方案作进一步详细说明。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1,本发明提供了一种半导体器件的制造方法,包括以下步骤:
S1,提供半导体衬底,并刻蚀所述半导体衬底,以形成栅极沟槽于所述半导体衬底中;
S2,形成栅极于所述栅极沟槽中,并回刻蚀所述栅极至所述栅极沟槽内一定深度,以形成回刻蚀槽;
S3,形成反型掺杂区和同型重掺杂区于所述栅极沟槽周围的半导体衬底中;
S4,填充在预设温度下可流动的介质材料于所述回刻蚀槽中并回流,以形成介质层,所述介质层填满所述回刻蚀槽并露出所述回刻蚀槽周围的同型重掺杂区的表面;
S5,以所述介质层为掩膜,刻蚀所述回刻蚀槽周围的同型重掺杂区和所述同型重掺杂区下方的反型体区,以形成接触孔;
S6,形成接触插塞于所述接触孔中;
S7,依次形成金属电极层和钝化层,所述金属电极层覆盖于所述接触插塞、所述同型重掺杂区和所述介质层上,所述钝化层覆盖于所述金属电极层上。
请参考图2A,在步骤S1中,首先,提供半导体衬底100,该半导体衬底100可以是本领域技术人员熟知的任意合适衬底,例如是体硅衬底、锗衬底、硅锗衬底、绝缘体上硅衬底、绝缘体上锗衬底、由基底及其上外延的单晶硅层组成的衬底、区熔硅衬底等等。然后,在所述半导体衬底100的表面上形成硬掩膜层(未图示),硬掩膜层的材质可以包括氧化硅、氮化硅和氮氧化硅中的至少一种,可以是单层结构,也可以是叠层结构。之后,借助栅极掩膜版掩膜,进行光刻结合干法刻蚀的工艺,来刻蚀硬掩膜层和半导体衬底100,以在半导体衬底100中形成至少一个栅极沟槽101,栅极沟槽101的侧壁光滑,底部圆滑,可以避免后续填充在栅极沟槽101底部的多晶硅出现尖端的问题,栅极沟槽101的深度和宽度均取决于器件性能要求,例如栅极沟槽101的深度1μm~6μm,栅极沟槽101的顶部开口的宽度为0.3μm~4μm。作为一种示例,形成的栅极沟槽101是U型沟槽,其顶部开口的宽度可以等于或大于底部开口的宽度,栅极沟槽101的侧壁与半导体衬底100的底面之间的夹角为85°~90°,由此,可以避免栅极沟槽101占用过多的芯片面积的问题,并避免后续填充在栅极沟槽101底部的多晶硅出现尖端的问题。
需要说明的是,在本发明的其他实施例中,当在步骤S1中提供的半导体衬底100包括基底(未图示)以及位于基底上的半导体外延层时,栅极沟槽101可以完全形成于半导体外延层中,从而通过半导体外延层的厚度来限定栅极沟槽101的深度,而该基底可以在后续从背面减薄,并进行重掺杂而作为漏区,在步骤S3中在栅极沟槽101周围形成的同型掺杂区作为源区,形成的反型体区作为源区和漏区之间的沟道。另外,步骤S1刻蚀形成栅极沟槽101之后,硬掩膜层可以在后续栅极填充好之前均被保留,以保护栅极沟槽101周围的半导体衬底100。此外,图2A中示出了两个栅极沟槽101,但是本发明的技术方案并不仅仅限定于此,在本发明的其他实施例中,可以根据器件需要,同时形成一个或者两个以上的栅极沟槽101,且当有两个或两个以上的栅极沟槽101时,各个栅极沟槽101的宽度可以相同,也可以不同,各个栅极沟槽101的深度可以相同,也可以不同,栅极沟槽101之间的间隔度可以相同,也可以不同。
请参考图2A和2B,在步骤S2中,首先,可以采用热氧化工艺或者化学气相沉积工艺等,在栅极沟槽101的侧壁和底壁上形成栅介质层102,该栅介质层102的材质可以包括氧化硅、氮化硅、氮氧化硅和高K栅介质层中的至少一种,该栅介质层102可以是单层结构,也可以是叠层结构,例如ONO叠层结构(即氧化硅-氮化硅-氧化硅叠层结构)。然后,使用硅烷或含氯硅烷等含硅物质作为反应气体源,并进一步采用低压化学气相沉积(LP_CVD)工艺沉积多晶硅填充于栅极沟槽101中,且至少使得沉积的多晶硅填满栅极沟槽101。之后,可以采用化学机械平坦化(CMP)工艺或湿法刻蚀工艺,将多晶硅的顶面平坦至所述硬掩膜层的顶面,以形成填满栅极沟槽101的栅极103,其中,当采用化学机械平坦化(CMP)工艺时,还可以一并去除所述硬掩膜层的顶面上的栅介质层102。接着,可以采用干法刻蚀工艺、湿法刻蚀工艺或者干法刻蚀结合湿法刻蚀的工艺,来回刻蚀所述栅极103到栅极沟槽101内的一定深度,以形成回刻蚀沟槽104,回刻蚀沟槽104的深度可以小于1μm,回刻蚀过程中,栅极沟槽101侧壁上的栅介质层102可以保护侧壁的半导体衬底100不受该回刻蚀影响。其中,回刻蚀所述栅极103的深度,可以通过控制回刻蚀工艺的过刻蚀量或者通过线上的扫描电子显微镜设备来监控。
需要说明的是,在步骤S2中,当需要在栅极沟槽101中形成掺杂的多晶硅时,可以随着低压化学气相沉积反应而进行多晶硅的掺杂植入,例如需要填充P型掺杂的多晶硅时,可以使用硼乙烷作为掺杂气体源,一方面向多晶硅中掺入硼,另一方面利用硼乙烷做催化剂,来大幅度的提升沉积多晶硅的速率;再例如需要沉积N型掺杂的多晶硅时,可以使用磷化氢作为掺杂气体源,一方面向多晶硅中掺入磷,另一方面利用磷化氢做催化剂,来大幅度的提升沉积多晶硅的速率。
请参考图2C,在步骤S3中,首先,可以借助一光罩掩膜版在具有栅极沟槽101的半导体衬底100上形成图案化的光刻胶(未图示),该图案化的光刻胶暴露出半导体衬底100用作待形成的半导体器件的有源区(即包括栅极沟槽以及栅极沟槽两侧的有源区)的区域,并覆盖半导体衬底100的其他区域;然后,以该图案化的光刻胶为掩膜,对暴露出的有源区(包括所述栅极沟槽101及其周围的半导体衬底100)进行选择性的反型离子注入,并利用高温退火工艺使得注入的反型离子注入被推进扩散至半导体衬底100内一定深度,以形成导电类型与所述半导体衬底100的导电类型相反的反型体区105。形成的反型体区105的底面深度例如是2μm~4um。反型体区105中的反型离子的浓度取决于注入剂量和高温退火工艺的温度和时间,高温退火工艺的温度例如为1000℃~1200℃。接着,继续以所述图案化的光刻胶为掩膜,对暴露出的有源区(即包括所述栅极沟槽101及其周围的半导体衬底100)进行选择性的同型离子注入,并通过调节注入能量、注入剂量,其进一步利用高温热退火工艺,将注入的同型离子推进到半导体衬底100内一定深度,以将由半导体衬底100表面至一定深度的反型体区105转变为同型重掺杂区106,由此,同型重掺杂区106相对反型体区105浅,且同型重掺杂区106的底面与反型体区105的顶面相接,或者说,反型体区105上接同型重掺杂区106,且同型重掺杂区106的底面(即反型体区105的顶面)低于栅极103的顶面,由此使得同型重掺杂区106与栅极103有重叠,以避免不能形成有效的沟道而影响器件性能。其中,当形成的半导体器件为VDMOS晶体管时,同型重掺杂区106为VDMOS晶体管的源区;当形成的半导体器件为IGBT晶体管时,栅极103为IGBT晶体管的基极,同型重掺杂区106为IGBT晶体管的发射区。此外,当半导体衬底100的导电类型为N型时,采用本领域技术人员熟知的硼等P型离子进行反型离子注入,以形成与半导体衬底100的导电类型相反的反型体区105,采用本领域技术人员熟知的磷等N型离子进行同型离子注入,以形成与半导体衬底100的导电类型相同的同型重掺杂区106;当半导体衬底100的导电类型为P型时,采用本领域技术人员熟知的磷等N型离子进行反型离子注入,以形成与半导体衬底100的导电类型相反的反型体区105,采用本领域技术人员熟知的硼等P型离子进行同型离子注入,以形成与半导体衬底100的导电类型相同的同型重掺杂区106。本实施例中,同型重掺杂区106的底面深度为0.2μm~1μm。
需要说明的是,上述实施例中,形成的反型体区105和同型重掺杂区106在半导体衬底100的表面的投影面积相同,同型重掺杂区106位于半导体衬底100的表层,反型体区105全部位于同型重掺杂区106的下方,但是本发明的技术方案并不仅仅限定于此,在本发明的其他实施例中,也可以借助合适的工艺来分别形成在半导体衬底100的表面的投影面积不同的反型体区105和同型重掺杂区106,使得半导体衬底100的表层不仅有同型重掺杂区106,还有反型体区105,且反型体区105还同时具有位于同型重掺杂区106底部的部分。另外,虽然图2C~图2G中示出的同型重掺杂区106的底面为平坦的,但是本发明的技术方案并不仅仅限定于此,在本发明的其他实施例中,也可以因退火时离子向半导体衬底中各个方向的推进深度不同而使得形成的同型重掺杂区106的底面为弯曲的,只要同型重掺杂区106紧挨栅极103的底面能够低于栅极的顶面,以保证能够形成有效的沟道即可,具体地例如同型重掺杂区106的底面为凸向半导体衬底100的上表面的凸面,或者,同型重掺杂区106的底面为凸向半导体衬底100的下表面的凹面,或者,同型重掺杂区106的底面为波浪形曲面。此外,因反型体区105位于同型重掺杂区106下方的部分与同型重掺杂区106的底面相接,因此反型体区105位于同型重掺杂区106下方的部分的顶面形状和同型重掺杂区106的底面形状相对应,而反型体区105的底面的形状也可以会因退火时离子向半导体衬底中各个方向的推进深度不同而呈现为凸面、凹面或波浪形曲面等形状。
更值得注意的是,在本发明的各个实施例中,步骤S3的操作均在步骤S4之前进行,可以避免在介质层填满回刻蚀槽之后再做高能量注入和高温热过程,进而避免某些高能量注入和高温热过程会影响介质层的绝缘性能的问题。此外,本发明的各实施例中,先形成栅极沟槽后形成反型体区105的工艺,相较于现有技术中先形成反型体区105后形成栅极沟槽的工艺而言,在同样的反型离子注入条件下,反型体区105的深度可以相对变浅,有利于改善器件的参数。
请参考图2C和2D,在步骤S4中,可以采用化学气相沉积(CVD)或者旋涂沉积工艺,填充在预设温度(例如800℃~1200℃)下可流动的介质材料于所述回刻蚀槽104中,以利用可流动的介质材料的流动性来避免填充缝隙,并在降温后形成填满所述回刻蚀槽104的介质层107,且可以进一步地通过回刻蚀工艺或者CMP工艺来将介质层107的顶面降低至同型重掺杂区106的顶面,从而使得介质层107填满回刻蚀沟槽104并露出回刻蚀沟槽104周围的同型重掺杂区106的顶面。其中,利用可流动的介质材料形成的介质层107厚的地方和介质层107薄的地方之间的高度差较低,有利于减少将介质层107的顶面降低至同型重掺杂区106的顶面的操作时间,并有利于改善后续形成的接触孔的深度一致性,且在后续形成接触插塞于接触孔中后,能使得保留的介质层107的膜厚相对均匀,以改善介质层107的绝缘性能。其中,可流动的介质材料可以是本领域中任何能够在一定温度下流动且能做绝缘介质的材料,例如包括硅酸盐玻璃、正硅酸乙酯、旋涂玻璃(SOG)和聚合物材料中的至少一种,其中硅酸盐玻璃可以包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)和硼磷硅酸盐玻璃(BPSG)中的至少一种。
请参考图2E,在步骤S5中,可以利用回刻蚀沟槽104内填充的介质层107作为掩膜层,进行选择性刻蚀(例如晶向选择性湿法刻蚀),以将相邻两个栅极沟槽101之间的半导体衬底100(即部分同型重掺杂区106和同型重掺杂区106下方对应的部分厚度的反型体区105)刻蚀至一定深度,以形成接触孔108,接触孔108的底面深度需要超过步骤S4中形成的同型重掺杂区106的底面深度。其形成的接触孔108为呈现倒梯形结构,接触孔108的侧壁与半导体衬底的底面之间的夹角小于90°,以避免影响器件同型重掺杂区106的性能。接触孔108的角可以是圆角,有利于后续材料的填充,以避免填充缝隙以及尖端放电的问题。由于该接触孔108是通过以所述介质层为掩膜的一种自对准接触孔刻蚀工艺来形成的,因此形成的所述接触孔108位于相应的两个相邻的所述栅极沟槽101之间,且所述接触孔108的顶部开口的宽度等于两个相邻的所述栅极沟槽101之间的间距。且,由于是一种自对准接触孔刻蚀工艺,因此,基本上不会因工艺波动而产生接触孔108对准偏移的问题,进而保证了接触孔108和栅极沟槽101有非常高的对准精度,避免了后续接触孔108内注入的杂质离子在退火后会扩散到沟道区域的问题,进而改善半导体器件的性能。且无需光罩掩膜版辅助即可刻蚀形成接触孔108,继而可以省去一张光罩掩膜版,降低生产成本。
可选地,请继续参考图2E,在形成接触孔108之后,可以在接触孔108的底部再次进行反型离子注入,并进行低温退火(即采用温度低于能使得介质层107流动的预设温度来进行退火),以使得注入的反型离子扩散后,在接触孔108的底部形成反型阻挡层109,所述反型阻挡层109与所述反型体区105同型(即两者的导电类型相同),且反型阻挡层109的反型离子的掺杂浓度大于反型体区105中的反型离子的掺杂浓度,反型阻挡层109和同型重掺杂区106在高度上有重叠(例如反型阻挡层109的顶面不低于所述同型重掺杂区106的底面),从而反型阻挡层109能将同型重掺杂区106和反型体区105短接,进而通过反型阻挡层109将由同型重掺杂区106、反型体区105和底部的半导体衬底100构成的寄生晶体管进行短路,避免器件栓锁失效(或者说,减小可能的栓锁现象发生概率),并且反型阻挡层109为重掺杂的,能降低后续在接触孔内形成的接触插塞的接触电阻。
请参考图2E~2G,在步骤S6中,首先,通过溅射沉积等工艺,在接触孔108的侧壁上覆盖一层金属阻挡层110,所述金属阻挡层110的材料包括钛Ti、氮化钛TiN、钽Ta和氮化钽TaN中的至少一种,可以是单层结构,可以是叠层结构,厚度可以在范围内,用于隔离后续形成的接触插塞111以及金属电极层112分别和同型重掺杂区106、反型体区105以及反型阻挡层109之间漏电。然后,通过溅射沉积等工艺淀积钨或铜等金属材料至接触孔108填满,并通过CMP工艺或回刻蚀工艺高出介质层107顶面的多余金属材料去除,以形成接触插塞111于所述接触孔108中,此时接触插塞111贯穿同型重掺杂区106且底面伸入至反型体区105中一定深度;之后,再选用铝Al、铝硅合金,铝硅铜合金等作为靶材,通过溅射沉积等工艺淀积金属电极层112覆盖于所述接触插塞111、金属阻挡层110、栅介质层102和介质层107的表面上。最后通过化学气相沉积等该工艺形成钝化层113于金属电极层112上,用于提高器件的可靠性。
需要说明的是,本发明的技术方案并不仅仅限于上述的实施例,也可以在任意两步骤中间添加一些其他步骤来改变形成的半导体器件的结构,例如,在本发明的其他实施例中,请参考图3,在步骤S2中,在形成栅极103于所述栅极沟槽101中之前,先通过热氧化工艺或者化学气相沉积工艺,填充厚度大于栅介质层102的栅槽底部氧化物102a,并通过回刻蚀工艺将栅极沟槽101中填充的栅槽底部氧化物102a回刻蚀至要求厚度,栅槽底部氧化物102a能够使得器件的栅漏间电容大大减小,从而提高沟槽式功率器件的开关速度,其中栅槽底部氧化物102a的具体厚度例如为再例如,在本发明的其他实施例中,请参考图4,在步骤S2中,在形成栅极103于所述栅极沟槽101中之前,先热氧化或者化学气相沉积等工艺,在栅极沟槽101的内表面上形成屏蔽介质层102d,再通过化学气相沉积等工艺填充多晶硅于栅极沟槽101中,并以回刻蚀的方式将该多晶硅刻蚀到需要保留住的部位,以形成多晶硅屏蔽栅102b,回刻蚀多晶硅以形成多晶硅屏蔽栅102b的同时,可以将屏蔽介质层102d回刻蚀至多晶硅屏蔽栅102b的顶面高度,然后,通过热氧化或者化学气相沉积等工艺并进一步结合回刻蚀工艺,在多晶硅屏蔽栅102b的顶部形成绝缘层102c,绝缘层102c的材料可以包括氧化硅、氮化硅和氮氧化硅中的至少一种,之后,再在绝缘层102c上方的栅极沟槽101中依次形成栅介质层102和栅极103。
请参考图2G、图3和图4,基于同一发明构思,本发明还提供一种采用上述的半导体器件的制造方法制造的半导体器件,所述半导体器件包括:半导体衬底100、栅极103、介质层107、反型体区105、同型重掺杂区106和接触插塞111。其中,所述半导体衬底100中形成有栅极沟槽,所述栅极103和介质层107依次填充于所述栅极沟槽中,且所述介质层107位于所述栅极103上方。栅极103可以是多晶硅栅极,也可以是金属栅极,栅极103和周围的半导体衬底100之间还夹有栅介质层102。反型体区105和同型重掺杂区106均位于所述栅极沟槽周围的半导体衬底100中,反型体区105的导电类型与其底部下方的半导体衬底100和同型重掺杂区106的导电类型相反。本实施例中,所述反型体区105可以完全位于所述同型重掺杂区106的下方并与同型重掺杂区106相接,所述反型体区105紧挨栅极103的区域的顶面低于所述栅极103的顶面。在本发明的其他实施例中,所述反型体区105也可以一部分位于同型重掺杂区106的下方,另一部位于同型重掺杂区106远离栅极103的一侧,以对同型重掺杂区106远离栅极的一侧和底面进行包围,且同型重掺杂区106紧挨栅极103的区域的底面低于栅极103的顶面,即同型重掺杂区106紧挨栅极103的区域与栅极103在高度上有重叠,以保证能形成有效的沟道。接触插塞111贯穿所述同型重掺杂区106且底面伸入到所述同型重掺杂区106下方的所述反型体区105中,从而保证所述接触插塞111的电连接的可靠性。
在本发明的一实施例中,请参考图3,所述栅极103和其底部的半导体衬底100之间还夹有厚度较大的栅槽底部氧化物102a,以通过栅槽底部氧化物102a使得器件的栅漏间电容大大减小,从而提高沟槽式功率器件的开关速度。
在本发明的另一实施例中,请参考图4,所述栅极103和其底部的半导体衬底100之间还夹有多晶硅屏蔽栅102b以及位于多晶硅屏蔽栅102b上方的绝缘层102c,以通过多晶硅屏蔽栅102b和绝缘层102c来使得器件的栅漏间电容大大减小,从而提高沟槽式功率器件的开关速度。多晶硅屏蔽栅102b和其周围的半导体衬底100之间还夹有屏蔽介质层102d。
另外,图2G、图3和图4中示出的底面平坦的同型重掺杂区106和反型体区105仅作为本发明的半导体器件的一种示例,在本发明的半导体器件的其他示例中,同型重掺杂区106的底面和反型体区105的底面也可以为弯曲的,且只要同型重掺杂区106紧挨栅极103的区域的底面能够低于栅极103的顶面,以保证能够形成有效的沟道即可。
综上所述,本发明的半导体器件及其制造方法,能够保证接触孔和栅极沟槽有非常高的对准精度,避免了接触孔内注入的杂质离子在退火后会扩散到沟道区域的问题,进而改善半导体器件的性能。且可以实现自对准接触孔刻蚀,进而可以省去一张光罩掩膜版,降低生产成本。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (10)
1.一种半导体器件的制造方法,其特征在于,包括以下步骤:
S1,提供半导体衬底,并刻蚀所述半导体衬底,以形成栅极沟槽于所述半导体衬底中;
S2,形成栅极于所述栅极沟槽中,并回刻蚀所述栅极至所述栅极沟槽内一定深度,以形成回刻蚀槽;
S3,形成反型掺杂区和同型重掺杂区于所述栅极沟槽周围的半导体衬底中;
S4,填充在预设温度下可流动的介质材料于所述回刻蚀槽中并回流,以形成介质层,所述介质层填满所述回刻蚀槽并露出所述回刻蚀槽周围的同型重掺杂区的表面;
S5,以所述介质层为掩膜,刻蚀所述回刻蚀槽周围露出的同型重掺杂区及所述同型重掺杂区下方的反型体区,以形成接触孔;
S6,形成接触插塞于所述接触孔中。
2.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S1中,刻蚀所述半导体衬底而形成的所述栅极沟槽的数量不少于两个;在步骤S5中,形成的所述接触孔位于相应的两个相邻的所述栅极沟槽之间,且所述接触孔的顶部开口的宽度等于两个相邻的所述栅极沟槽之间的间距。
3.如权利要求2所述的半导体器件的制造方法,其特征在于,在步骤S5中,形成的所述接触孔为倒梯形结构,所述接触孔的顶部开口的宽度大于所述接触孔的底部开口的宽度。
4.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S2中,形成栅极于所述栅极沟槽中之前,先形成栅槽底部氧化物或者多晶硅屏蔽栅填充于所述栅极沟槽的底部,当形成多晶硅屏蔽栅填充于所述栅极沟槽的底部时,所述多晶硅屏蔽栅和所述栅极之间夹有绝缘层。
5.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S3中,先对所述栅极沟槽周围的半导体衬底进行反型离子注入,再对所述栅极沟槽周围的半导体衬底进行同型离子注入,所述同型离子注入的深度深于所述栅极沟槽中的栅极的顶面。
6.如权利要求5所述的半导体器件的制造方法,其特征在于,在步骤S3中,所述反型离子注入的工艺参数包括:注入深度为2μm~4μm,工艺温度为1000℃~1200℃;所述同型离子注入的深度为0.2μm~1μm。
7.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S4中填充的所述可流动的介质材料包括硅酸盐玻璃、正硅酸乙酯、旋涂玻璃和聚合物材料中的至少一种。
8.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S6之前且在步骤S5之后,还包括:在所述接触孔底部再次进行反型离子注入并进行低于所述预设温度的退火处理,以在所述接触孔的底部形成反型阻挡层,所述反型阻挡层与所述反型体区的导电类型相同,且将所述反型体区和所述同型重掺杂区短接。
9.如权利要求1所述的半导体器件的制造方法,其特征在于,在步骤S6之后,还包括:依次形成金属电极层和钝化层,所述金属电极层覆盖于所述接触插塞、所述同型重掺杂区和所述介质层上,所述钝化层覆盖于所述金属电极层上。
10.一种半导体器件,其特征在于,采用权利要求1~9中任一项所述的半导体器件的制造方法制造,所述半导体器件包括:
半导体衬底,所述半导体衬底中形成有栅极沟槽;
栅极和介质层,依次填充于所述栅极沟槽中,且所述介质层位于所述栅极上方;
反型体区和同型重掺杂区,均位于所述栅极沟槽周围的半导体衬底中;
接触插塞,贯穿所述同型重掺杂区且底面伸入到所述同型重掺杂区下方的所述反型体区中。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910961381.2A CN110676215A (zh) | 2019-10-10 | 2019-10-10 | 半导体器件及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910961381.2A CN110676215A (zh) | 2019-10-10 | 2019-10-10 | 半导体器件及其制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110676215A true CN110676215A (zh) | 2020-01-10 |
Family
ID=69081482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910961381.2A Withdrawn CN110676215A (zh) | 2019-10-10 | 2019-10-10 | 半导体器件及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110676215A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117012817A (zh) * | 2023-09-25 | 2023-11-07 | 上海功成半导体科技有限公司 | 一种沟槽栅igbt器件及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103295907A (zh) * | 2012-02-29 | 2013-09-11 | 株式会社东芝 | 半导体装置及其制造方法 |
CN103871892A (zh) * | 2012-12-13 | 2014-06-18 | 茂达电子股份有限公司 | 凹入式晶体管的制作方法 |
CN107689328A (zh) * | 2016-08-03 | 2018-02-13 | 世界先进积体电路股份有限公司 | 半导体装置结构的形成方法 |
CN109119477A (zh) * | 2018-08-28 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | 沟槽栅mosfet及其制造方法 |
-
2019
- 2019-10-10 CN CN201910961381.2A patent/CN110676215A/zh not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103295907A (zh) * | 2012-02-29 | 2013-09-11 | 株式会社东芝 | 半导体装置及其制造方法 |
CN103871892A (zh) * | 2012-12-13 | 2014-06-18 | 茂达电子股份有限公司 | 凹入式晶体管的制作方法 |
CN107689328A (zh) * | 2016-08-03 | 2018-02-13 | 世界先进积体电路股份有限公司 | 半导体装置结构的形成方法 |
CN109119477A (zh) * | 2018-08-28 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | 沟槽栅mosfet及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117012817A (zh) * | 2023-09-25 | 2023-11-07 | 上海功成半导体科技有限公司 | 一种沟槽栅igbt器件及其制作方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9911840B2 (en) | Self aligned trench MOSFET with integrated diode | |
US8330200B2 (en) | Super-self-aligned trench-DMOS structure and method | |
US7799642B2 (en) | Trench MOSFET and method of manufacture utilizing two masks | |
CN110911281B (zh) | 具有沟槽型栅极的半导体器件及其制造方法 | |
TWI470790B (zh) | 溝渠式閘極金氧半場效電晶體 | |
TWI405270B (zh) | 低閘極電荷的溝槽式功率半導體之製造方法及其結構 | |
US7494876B1 (en) | Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same | |
US7687352B2 (en) | Trench MOSFET and method of manufacture utilizing four masks | |
US11574840B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US9991378B2 (en) | Trench power semiconductor device | |
US20090085099A1 (en) | Trench mosfet and method of manufacture utilizing three masks | |
JP3965027B2 (ja) | トレンチ底部に厚いポリシリコン絶縁層を有するトレンチゲート型misデバイスの製造方法 | |
CN112820645B (zh) | 一种功率半导体器件及其制备方法 | |
CN110676215A (zh) | 半导体器件及其制造方法 | |
CN113809148B (zh) | 功率元件及其制造方法 | |
CN106601811B (zh) | 沟槽式功率晶体管 | |
TWI546956B (zh) | 溝渠式閘極金氧半場效電晶體 | |
CN213816161U (zh) | 一种具有沟槽型栅极的半导体器件 | |
CN216389378U (zh) | 一种沟槽型功率器件 | |
TWI802320B (zh) | 半導體結構以及閘極結構的製造方法 | |
CN112838007B (zh) | 一种沟槽栅功率器件及其制备方法 | |
CN111312809B (zh) | 功率器件及其制造方法 | |
CN115910795B (zh) | 一种屏蔽栅功率器件及其制备方法 | |
US20230077336A1 (en) | Method for manufacturing conducting path in doped region, trench-type mosfet device and manufacturing method thereof | |
TW201507154A (zh) | 溝渠式閘極金氧半場效電晶體 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200110 |