CN110673023B - Testing device and testing method for detecting stability of core board - Google Patents
Testing device and testing method for detecting stability of core board Download PDFInfo
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- CN110673023B CN110673023B CN201911237903.0A CN201911237903A CN110673023B CN 110673023 B CN110673023 B CN 110673023B CN 201911237903 A CN201911237903 A CN 201911237903A CN 110673023 B CN110673023 B CN 110673023B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a testing device and a testing method for testing the stability of core boards, wherein the testing device comprises a power supply input interface, a power supply output interface and a power supply output interface, wherein the power supply input interface is used for connecting a working power supply to provide electric energy for each core board; the voltage detection circuit is used for detecting the voltage value of the accessed working power supply; each current detection circuit is connected with the output current of one core board and is used for measuring the current value of each core board after being started; each serial data interface is connected with a core board and used for acquiring the starting process of the core board. A plurality of electric current detection circuits gather the electric current that a plurality of nuclear core plate exported in starting simultaneously, and whether the current value of intelligent detection each nuclear core plate is in respective standard value scope, avoids adopting instruments such as ampere meter or universal meter to detect the trouble of a plurality of nuclear core plates one by one. The testing device can realize the parallel testing of a plurality of core boards, simplifies the testing model, improves the testing efficiency and lightens the testing burden.
Description
Technical Field
The invention belongs to the technical field of instrument testing, and particularly relates to a testing device and a testing method for testing the stability of a core board.
Background
The core board packages the core functions of the processor on an electronic mainboard, and most of the core boards integrate a CPU, a memory, universal functional pins and the like, and are matched with the bottom board in a patch, golden finger or direct insertion mode to meet the performance requirements of various products. In addition, the development difficulty is greatly reduced after the core board is embedded into a product, the development time of the product is shortened, and the stability and maintainability of the system are greatly improved. Core boards therefore take an increasingly important position in the development of products.
Due to the flexibility, non-standard property and importance in project development of the core board, quality inspection of the core board becomes a very important link. However, the core board has a hidden quality problem due to the difference of the mounting process and the quality difference of the components in the same batch. These implicit quality problems often do not show up immediately, but only through long-term full-load operation, and these implicit quality problems often bring enormous loss, even irreparable loss, to product development in volume production.
Disclosure of Invention
The invention aims to solve the technical problem of the hidden quality problem of a core board, and provides a testing device and a testing method for testing the stability of the core board.
In order to solve the problems, the invention is realized according to the following technical scheme:
the invention provides a testing device for detecting the stability of a core board, which comprises:
the power supply input interface is used for connecting a working power supply to provide electric energy for each core board;
the voltage detection circuit is used for detecting the voltage value of the accessed working power supply;
each current detection circuit is connected with the output current of one core board and is used for measuring the current value of each core board after being started;
each serial data interface is connected with one core board and is used for acquiring the time T1 from the start-up of each core board to the uboot command, the time T2 from the uboot command to the system command and the time T3 from the system command to the shutdown of each core board;
the micro processing unit is connected with the current detection circuit and the serial data interface, and acquires the current detected by each core board, the time T1, the time T2 and the time T3;
the micro processing unit respectively compares the current, the time T1, the time T2 and the time T3 of each core board with set parameter values, specifically, the micro processing unit judges whether one detection value of the current, the time T1, the time T2 and the time T3 of the core board is not in the range of the parameter values, if yes, the current core board does not pass through the current test;
the micro-processing unit is preset with total test time or total test times to obtain the number m of non-passing times and the total number n of times of each core board; and when the total test time or the total test times are met, the micro-processing unit calculates the failure rate p of each core board based on the number m of failed times and the total number n of times.
Further, each current detection circuit comprises a three-way switching circuit, a current detection chip U1, a coupling resistor R5, an operational amplifier chip U2B, a clamping chip U3 and a filter capacitor C3, wherein,
the three switching circuits of each current detection circuit are connected with the current output end of the same core board; one end of the three-way switching circuit of each current detection circuit is connected with an RS + pin of the current detection chip U1 in parallel, and the other end of the three-way switching circuit is connected with an RS-pin of the current detection chip U1 in parallel;
one end of the coupling resistor R5 is connected with an OUT pin of the current detection chip U1, and the other end of the coupling resistor R5 is connected with a 2IN + pin of the operational amplifier chip U2B and used for filtering noise clutter;
the clamping chip U3 and the filter capacitor C3 are connected in parallel and then connected with the 2OUT pin of the operational amplifier chip U2B.
Furthermore, each switching circuit comprises a signal relay and a sampling resistor, and the sampling resistor is arranged in a working circuit of the signal relay;
the resistance values of the sampling resistors of each switching circuit are different;
one end of a working circuit of a signal relay of each switching circuit is connected with the current output end of the core board, and the other end of the working circuit is connected into the testing device, so that the output current of the core board passes through the sampling resistor;
two ends of a working circuit of a signal relay of each switching circuit are respectively connected with an RS + pin and an RS-pin of a current detection chip U1.
Further, the voltage detection circuit comprises an operational amplifier chip U2A, a resistor R10 and a resistor R11;
one end of the resistor R11 is connected with a working power supply, and the other end of the resistor R11 is connected with a 1IN + pin of the operational amplifier chip U2A;
one end of the resistor R10 is connected with the 1IN + pin of the operational amplifier chip U2A, and the other end is connected with digital ground.
Furthermore, a power relay is arranged between each core board and the power input interface, and each power relay is used for controlling the start or stop of the core board on the circuit where the power relay is arranged.
Furthermore, the micro-processing unit is provided with a plurality of ADC pins, a plurality of serial data pins, a plurality of I/O pins, an SD card pin and an internet access pin;
the ADC pins are connected with the 1OUT pin of the operational amplifier chip U2A and the 2OUT pins of the operational amplifier chip U2B one by one, and are used for receiving a voltage signal of a voltage detection circuit and a current signal of a plurality of current detection circuits by the micro-processing unit and converting the voltage signal and the current signal into digital signals;
the plurality of serial data pins are connected with the plurality of serial data interfaces one by one and used for the micro-processing unit to acquire the starting state of each core board;
each I/O pin is connected with a power relay and used for controlling the work of each power relay by the micro-processing unit.
A testing method using the testing apparatus for testing the stability of the core board, comprising the steps of:
s1, respectively connecting the core boards to the testing device, connecting the core boards with the serial data interfaces one by one, and respectively setting the parameter value of each core board on the testing device;
s2, the test device respectively controls the working power supply to electrify a plurality of core boards, the test device detects the current I after the system of each core board is successfully started, and records the time T1 from the start of each core board to the uboot command, the time T2 from the uboot command to the system command and the time T3 from the system command to the shutdown;
s3, the testing device respectively compares the current I, the time T1, the time T2 and the time T3 obtained by the detection of each core board with set parameter values, if one detection value of one core board is not in the range of the parameter values, the core board is indicated to fail in the current test, and the failure times m and the total times n of the core board are recorded or updated;
and S4, after the core board is started, the testing device cuts off the power supply of the core board, the steps S2 and S3 are repeated after a period of time, and after the total testing time or the total testing times set by the tester, the number m of non-passing times of each core board is divided by the total number n of non-passing times of each core board to obtain the failure rate p.
Further, the test device in step S2 detects the current I after each core board system is successfully started, and specifically obtains the current I according to the following formula:
the PPI represents an ADC value detected by the microprocessor unit through an ADC pin, the SNR represents an ADC sampling resolution of the microprocessor unit, β represents an amplification factor of the operational amplifier chip U2B, RX represents a resistance value of a sampling resistor, and Vref represents a reference voltage of the microprocessor unit.
Further, the process of obtaining the PPI is: the micro-processing unit obtains a plurality of ADC values in unit time through ADC pins, removes peak values and valley values of the ADC values, and then takes an average value as the PPI.
Further, the step S2 includes the testing device detecting and recording whether the system of each core board is successfully started and the power consumption of the core board.
Compared with the prior art, the invention has the beneficial effects that:
1. the inside a plurality of current detection circuits that are equipped with of testing arrangement, it gathers the electric current of a plurality of nuclear core boards output in starting simultaneously, feeds back to testing arrangement's the control unit behind the digital signal with this electric current conversion, and whether the current value of each nuclear core board of intellectual detection system is in respective standard value scope, avoids adopting instruments such as ampere meter or universal meter to detect the trouble of a plurality of nuclear core boards one by one, realizes a plurality of nuclear core board synchronous detection. The testing device can realize the parallel testing of a plurality of core boards, simplifies the testing model, improves the testing efficiency and lightens the testing burden.
2. The method comprises the steps of carrying out thousands of times of starting detection on each core board by adopting a testing device, detecting current generated by the core board in each starting and response time of each stage, counting the number of times of failure m and the total number of times n of each core board, and dividing the number of times of failure m and the total number of times n to obtain the reject ratio p to reflect the quality condition of the core board. According to the detection mode, results are obtained after huge testing times are adopted, the test contingency caused by few testing times is avoided, the detection accuracy is further improved, the quality condition of each core board is reflected to the maximum extent, and the large loss caused by the quality problem of the core boards is avoided.
Drawings
Embodiments of the invention are described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a system diagram of a test apparatus for testing the stability of a core board according to the present invention;
FIG. 2 is a schematic diagram of the voltage detection circuit of the present invention;
FIG. 3 is a schematic diagram of the current sensing circuit of the present invention;
FIG. 4 is a schematic flow chart of the detection method of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1
As shown in fig. 1 to 3, a preferred structure of the testing apparatus for testing the stability of the core board according to the present invention is shown.
As shown in fig. 1, the testing apparatus includes a power input interface, a voltage detection circuit, a plurality of current detection circuits, a plurality of serial data interfaces, and a micro-processing unit. The power input interface is connected with an external stable working power supply, and the working power supply is connected with the core boards in parallel and used for providing stable electric energy for the core boards. The voltage detection circuit is connected with the power input interface and used for detecting the voltage value of the working power supply connected to the testing device. Each current detection circuit is connected with one core board and used for detecting the current value of each core board after the system is successfully started. Each serial data interface is connected with a core board and used for monitoring and acquiring the starting state of the core board and the response time of each stage in the starting process. Preferably, the serial data interface is a 232 level or TTL level serial communication interface. The micro-processing unit is used for receiving analog signals output by the voltage detection circuit and the current detection circuits, converting the analog signals into digital signals, and controlling the work of other components in the testing device.
Further, as shown in fig. 2, the voltage detection circuit includes an operational amplifier chip U2A, a resistor R10, and a resistor R11. One end of the resistor R11 is connected to a working power supply, and the other end of the resistor R11 is connected with a 1IN + pin of the operational amplifier chip U2A; one end of the resistor R10 is connected with the 1IN + pin of the operational amplifier chip U2A, and the other end is connected with digital ground. The working power supply divides voltage after passing through a 1/4 voltage division circuit consisting of R10 and R11, and the micro processing unit acquires the voltage value after voltage division as the reference voltage of each current detection circuit, so that inaccurate detection of high current or low current is avoided. And a 1OUT pin of the operational amplifier chip U2A is connected to the micro-processing unit, and the micro-processing unit converts the amplified voltage value into a corresponding digital signal and controls the work of other components in the testing device according to the digital signal of the voltage.
Further, as shown in fig. 3, each current detection circuit includes a three-way switching circuit, a current detection chip U1, a coupling resistor R5, an operational amplifier chip U2B, a clamp chip U3, and a filter capacitor C3.
The micro-processing unit selects one of the switching circuits to be connected into the current detection circuit according to the reference voltage obtained by the detection so as to finish the detection of the output current of the core board. Preferably, each switching circuit comprises a signal relay and a sampling resistor, the sampling resistor is arranged in an operating circuit of the signal relay, and the resistance values of the sampling resistors of each switching circuit are different. The signal relay one end of three routes switching circuit of each current detection circuit connects the current output end of same nuclear core plate simultaneously, and the inside of testing arrangement is inserted to the other end, specifically is: the power output interface J1 of the core board is respectively connected in parallel with one end of the working circuit of the three signal relays of the current detection circuit, and the other end of the working circuit of the three signal relays is connected to the power interface J2 of the testing device to form a closed current loop, so that the output current of the core board passes through the sampling resistor.
As an embodiment, the auxiliary circuit of the signal relay includes an NPN type triode and a current limiting resistor, the I/O port of the micro processing unit is connected in series with the current limiting resistor and then connected to the base B of the NPN type triode, the collector C is connected to the electromagnet of the signal relay, the collector E is connected to a digital ground, the micro processing unit pre-determines the range of the core board output current according to the reference voltage, and intelligently controls the conduction of the NPN type triode to control the switching of the sampling resistor, so that the most suitable sampling resistor is connected to the current detection circuit, and the collection accuracy of the current detection circuit is improved.
Preferably, the three sampling resistors are preferably 0.05 Ω, 0.15 Ω and 1.5 Ω, and each detect currents in the range of 1-3A (large current step), 0.1-1A (medium current step) and less than 0.1A (small current step), and generally, each current detection circuit is set by default to adopt a small current step which detects the current of the core board to be less than 0.1A. When the micro-processing unit detects that the reference voltage is larger than or equal to 3.1V, the maximum current of the core board is judged to exceed 0.1A in advance, the micro-processing unit controls the signal relay to select a medium current gear, and the current detection range is 0.1-1A. And when the reference voltage is detected to be more than or equal to 3.1V in the medium current stage, the maximum current of the core board is judged to exceed 1A in advance, and the micro-processing unit controls the signal relay to select the large current stage. The testing device selects the sampling resistors with different resistance values by intelligently prejudging the output current of the core board, realizes high-precision detection of the output current of the core board, can avoid detection errors of small current output by the core board in a large range, and improves detection precision.
Furthermore, two ends of a working circuit of a signal relay of the three-way switching circuit of each current detection circuit are respectively connected with an RS + pin and an RS-pin of a current detection chip U1, so that the current detection chip U1 can obtain sampling voltages at two ends of a sampling resistor. One end of the coupling resistor R5 is connected with an OUT pin of the current detection chip U1, and the other end of the coupling resistor R5 is connected with a 2IN + pin of the operational amplifier chip U2B and used for filtering noise clutter. The clamp chip U3 and the filter capacitor C3 are connected in parallel and then connected with the 2OUT pin of the operational amplifier chip U2B, and the clamp chip U3 is used for limiting a voltage signal between 0V and 3.3V, so that the voltage signal of the working voltage is prevented from exceeding the bearing range of the testing device.
As an embodiment, the operational amplifier chip U2B is made into a level-emitting follower, which can increase the driving capability of the operational amplifier chip U2B, improve the anti-interference performance of signals, and limit the power supply range of the operational amplifier chip U2B, thereby avoiding the micro-processing unit from being burned due to overload caused by an over-voltage working power supply.
Preferably, the model of the current detection chip U1 is MAX4080TASA, the models of the operational amplifier chip U2A and the operational amplifier chip U2B are both LM258, and the model of the clamping chip U3 is BAT 54S. It should be noted that, in this embodiment, the types of the current detecting chip U1, the operational amplifier chip U2A, the operational amplifier chip U2B, and the clamp chip U3 are not further limited, and all types of chips satisfying the respective functions are within the protection scope of the present invention.
Furthermore, a power relay is arranged between each core board and the power input interface, and a working circuit of each power relay is respectively connected with the power input interface and a power supply end of one core board and used for controlling the start or stop of each core board.
Furthermore, the micro-processing unit is provided with a plurality of ADC pins, a plurality of serial data pins, a plurality of I/O pins, an SD card pin and an internet access pin. Preferably, the model of the micro processing unit is TQIMX6UL — COREB, which can detect the stability of the 7-way core board in parallel.
The ADC pins are connected with the 1OUT pin of the operational amplifier chip U2A and the 2OUT pin of the operational amplifier chip U2B one by one, and are used for receiving voltage signals of the voltage detection circuit and current signals of the current detection circuits by the micro processing unit, converting the voltage signals and the current signals into digital signals, and feeding the digital signals back to a control center of the micro processing unit to prepare for subsequent detection. The plurality of serial data pins are connected with the plurality of serial data interfaces one by one and used for the micro-processing unit to acquire the starting state of each core board and feed back the starting state to the control center of the micro-processing unit. Each I/O pin is connected with a control signal end of a power relay and used for controlling the work of each power relay so as to intelligently control the start or stop of the core board. The SD card pins are used for inserting the SD card so as to extract the detection data of the core board and then analyze the detection data. The net gape pin is used for external net twine to acquire the detection data of nuclear core plate in order long-rangely, is convenient for monitor each nuclear core plate's the detection condition anytime and anywhere.
Furthermore, the testing device also comprises a system power supply input end and an LCD, wherein a voltage conversion circuit is arranged in the system power supply input end and is used for converting a high-voltage power supply into low-voltage direct current to supply to the micro-processing unit for operation; the LCD is used for displaying the detection data of each core board and controlling the detection steps of each core board by a tester through touching the LCD.
Other structures of the testing apparatus for detecting the stability of the core board in this embodiment are shown in the prior art.
Example 2
As shown in fig. 4, the detection method using the test apparatus of embodiment 1 includes the following steps:
s1, respectively connecting the core boards to the testing device, connecting the core boards with the serial data interfaces one by one, and respectively setting the parameter value of each core board on the testing device;
the core boards (the number of the core boards in this embodiment is 7 at most) are connected to the testing end of the testing device one by one, and the core boards are connected to the serial data interfaces one by one. The testing device automatically reads technical parameters of each core board through a serial data interface, such as rated voltage, rated current, rated power, maximum instantaneous current and the like, and then testers set detection means and parameters to be detected, such as baud rate, a selected platform, heartbeat detection time (used when the core board is subjected to System aging test), heartbeat timeout time (used when the System aging test is carried out, when the value is greater than the heartbeat detection time, the System is in a running or blocking state), a Uboot characteristic value (Uboot start normal judgment flag bit), a System characteristic value (System start normal judgment flag bit), the maximum switch times of core board detection, and a standard current range ImaxThe maximum time T1 from the startup of the core board to the uboot commandmaxMaximum time from core board uboot command to system command T2maxThe maximum time from the system command of the core board to shutdown T3maxAnd the like.
S2, the test device respectively controls the working power supply to electrify a plurality of core boards, the test device detects the current I after the system of each core board is successfully started, and records the time T1 from the start of each core board to the uboot command, the time T2 from the uboot command to the system command and the time T3 from the system command to the shutdown;
specifically, a tester controls the starting process of each core board through an LCD or remotely, such as starting time, starting sequence and the like, and a micro-processing unit in the testing device realizes the electrifying action of the working power supply to each core board through an intelligent control power relay. The output current I of each core board flows to the sampling resistor on each circuit in the testing device, and the output current I of the core board is calculated by the current detection chip U1 after measuring the sampling voltage at two ends of the sampling resistor and is transmitted to the micro processing unit to be converted into a corresponding digital signal.
Further, the current detection circuit obtains the output current I of the core board by measuring the current values at the two ends of the sampling resistor, and can know according to ohm's law:
wherein, V is the sampling voltage at both ends of the sampling resistor, and RX is the resistance value of the sampling resistor.
The technical parameters of the ADC pin of the micro-processing unit comprise reference voltage Vref and resolution SNR, the amplification factor of the operational amplifier chip U2B is β, and the micro-processing unit detects that the ADC value is PPI through the ADC pin, so that the sampling voltage at two ends of the sampling resistor is PPI
Combining the above two formulas, the output current I of the core board is obtained by the following formula:
the PPI is obtained by obtaining a plurality of ADC values obtained by the micro-processing unit in unit time through the ADC pins, removing peak values and valley values of the plurality of ADC values, and then taking an average value as the PPI, wherein the number of the unit time and the ADC values is determined according to the internal performance of the micro-processing unit, and the description is omitted here.
As a specific example, a preferred micro-processing unit according to embodiment 1 is model TQIMX6UL — COREB, with an ADC resolution of 12-bit, i.e., a SNR of 4096 and a reference voltage Vref of 3V. Assuming that the micro-processing unit detects that the ADC value PPI is 2048, the amplification factor of the operational amplifier chip U2B is 20, and the sampling resistor is 0.05 Ω, the output current of the core board is 1.5A (2048 × 3)/(4096 × 20 × 0.05).
Through the output current of each nuclear core plate of current detection circuit intellectual detection system, avoid adopting a lot of measurements such as ampere meter or universal meter, simplified the test model, let a plurality of nuclear core plate parallel test, greatly improve efficiency of software testing, alleviate the test burden.
The serial data interface reads the starting process of the core boards which are oppositely connected, and records the time T1 from the starting of the respective core boards to the uboot command, the time T2 from the uboot command to the system command, and the time T3 from the system command to the shutdown.
In addition, the test device detects and records whether the system of each core board is successfully started and the power consumption of the core board, and is used for detecting the running state of the core board.
S3, the testing device respectively compares the current I, the time T1, the time T2 and the time T3 obtained by the detection of each core board with set parameter values, if one detection value of one core board is not in the range of the parameter values, the core board is indicated to fail in the current test, and the failure times m and the total times n of the core board are recorded or updated;
specifically, the micro-processing unit determinesWhether the output current I of a core board is at the standard current ImaxAnd the time T1 is less than the maximum time T1maxTime T2 being less than maximum time T2maxAnd time T3 is less than maximum time T3maxIf so, the core board passes through the detection; and if one detection value does not accord with the judgment, the core board does not pass the current detection, and the number m of times of non-passing and the total number n of times of the core board are recorded or updated.
And S4, after the core board is started, the testing device cuts off the power supply of the core board, the steps S2 and S3 are repeated after a period of time, and after the total testing time or the total testing times set by the tester, the number m of non-passing times of each core board is divided by the total number n of non-passing times of each core board to obtain the failure rate p.
The tester pre-judges the time of normal complete start according to the technical parameters of each core board, and then sets the interval time of the two starts of the core board, wherein the interval time is properly set according to the technical parameters of the core board. And finally calculating the reject ratio p by dividing the number m of failed passes of each core board by the number n of total passes of each core board after the total testing time set by the tester or the maximum number of switching times detected by the core boards set in the step S1, wherein the reject ratio p is classified and judged according to the performance of each core board and the total number n.
During the inspection process, the testing device can edit and generate a relevant graph by displaying the technical parameters and the set parameter values of each core board on the LCD, the real-time failure rate p, the total testing times n and the details of each failure of the core board (the overtime times of the time T1 or the time T2 or the time T3 and the inspection process).
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, so that any modification, equivalent change and modification made to the above embodiment according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.
Claims (10)
1. The utility model provides a test device for detecting core plate stability which characterized in that includes:
the power supply input interface is used for connecting a working power supply to provide electric energy for each core board;
the voltage detection circuit is used for detecting the voltage value of the accessed working power supply;
each current detection circuit is connected with the output current of one core board and is used for measuring the current value of each core board after being started;
each serial data interface is connected with one core board and is used for acquiring the time T1 from the start-up of each core board to the uboot command, the time T2 from the uboot command to the system command and the time T3 from the system command to the shutdown of each core board;
the micro processing unit is connected with the current detection circuit and the serial data interface, and acquires the current detected by each core board, the time T1, the time T2 and the time T3;
the micro processing unit respectively compares the current, the time T1, the time T2 and the time T3 of each core board with set parameter values, specifically, the micro processing unit judges whether one detection value of the current, the time T1, the time T2 and the time T3 of the core board is not in the range of the parameter values, if yes, the current core board does not pass through the current test;
the micro-processing unit is preset with total test time or total test times to obtain the number m of non-passing times and the total number n of times of each core board; and when the total test time or the total test times are met, the micro-processing unit calculates the failure rate p of each core board based on the number m of failed times and the total number n of times.
2. The apparatus for testing the stability of a core board according to claim 1, wherein:
each current detection circuit comprises a three-way switching circuit, a current detection chip U1, a coupling resistor R5, an operational amplifier chip U2B, a clamping chip U3 and a filter capacitor C3, wherein,
the three switching circuits of each current detection circuit are connected with the current output end of the same core board; one end of the three-way switching circuit of each current detection circuit is connected with an RS + pin of the current detection chip U1 in parallel, and the other end of the three-way switching circuit is connected with an RS-pin of the current detection chip U1 in parallel;
one end of the coupling resistor R5 is connected with an OUT pin of the current detection chip U1, and the other end of the coupling resistor R5 is connected with a 2IN + pin of the operational amplifier chip U2B and used for filtering noise clutter;
the clamping chip U3 and the filter capacitor C3 are connected in parallel and then connected with the 2OUT pin of the operational amplifier chip U2B.
3. The apparatus for testing the stability of a core board according to claim 2, wherein:
each switching circuit comprises a signal relay and a sampling resistor, and the sampling resistor is arranged in a working circuit of the signal relay;
the resistance values of the sampling resistors of each switching circuit are different;
one end of a working circuit of a signal relay of each switching circuit is connected with the current output end of the core board, and the other end of the working circuit is connected into the testing device, so that the output current of the core board passes through the sampling resistor;
two ends of a working circuit of a signal relay of each switching circuit are respectively connected with an RS + pin and an RS-pin of a current detection chip U1.
4. The device for testing the stability of a core board according to claim 3, wherein:
the voltage detection circuit comprises an operational amplifier chip U2A, a resistor R10 and a resistor R11;
one end of the resistor R11 is connected with a working power supply, and the other end of the resistor R11 is connected with a 1IN + pin of the operational amplifier chip U2A;
one end of the resistor R10 is connected with the 1IN + pin of the operational amplifier chip U2A, and the other end is connected with digital ground.
5. The device for testing the stability of a core board according to claim 4, wherein:
and a power relay is arranged between each core board and the power input interface, and each power relay is used for controlling the start or stop of the core board on the circuit where the power relay is arranged.
6. The device for testing the stability of a core board according to claim 5, wherein:
the micro-processing unit is provided with a plurality of ADC pins, a plurality of serial data pins, a plurality of I/O pins, an SD card pin and a network port pin;
the ADC pins are connected with the 1OUT pin of the operational amplifier chip U2A and the 2OUT pins of the operational amplifier chip U2B one by one, and are used for receiving a voltage signal of a voltage detection circuit and a current signal of a plurality of current detection circuits by the micro-processing unit and converting the voltage signal and the current signal into digital signals;
the plurality of serial data pins are connected with the plurality of serial data interfaces one by one and used for the micro-processing unit to acquire the starting state of each core board;
each I/O pin is connected with a power relay and used for controlling the work of each power relay by the micro-processing unit.
7. A testing method using the testing apparatus for testing the stability of a core board according to claim 6, comprising the steps of:
s1, respectively connecting the core boards to the testing device, connecting the core boards with the serial data interfaces one by one, and respectively setting the parameter value of each core board on the testing device;
s2, the test device respectively controls the working power supply to electrify a plurality of core boards, the test device detects the current I after the system of each core board is successfully started and records the time T1 from the start of each core board to the uboot command, the time T2 from the uboot command to the system command and the time T3 from the system command to the shutdown;
s3, the testing device respectively compares the current I, the time T1, the time T2 and the time T3 obtained by the detection of each core board with set parameter values, if one detection value of one core board is not in the range of the parameter values, the core board is indicated to fail in the current test, and the failure times m and the total times n of the core board are recorded or updated;
and S4, after the core board is started, the testing device cuts off the power supply of the core board, the steps S2 and S3 are repeated after a period of time, and after the total testing time or the total testing times set by the tester, the number m of non-passing times of each core board is divided by the total number n of non-passing times of each core board to obtain the failure rate p.
8. The method according to claim 7, wherein the current I detected by the testing device in step S2 after each core board system is successfully started is obtained by the following formula:
the PPI represents an ADC value detected by the microprocessor unit through an ADC pin, the SNR represents an ADC sampling resolution of the microprocessor unit, β represents an amplification factor of the operational amplifier chip U2B, RX represents a resistance value of a sampling resistor, and Vref represents a reference voltage of the microprocessor unit.
9. The detection method according to claim 8, characterized in that:
the process for obtaining the PPI is as follows: the micro-processing unit obtains a plurality of ADC values in unit time through ADC pins, removes peak values and valley values of the ADC values, and then takes an average value as the PPI.
10. The detection method according to claim 7, characterized in that:
the step S2 further includes the test device detecting and recording whether the system of each core board is successfully started and the power consumption of the core board.
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