CN110660733A - Photoetching process method and dual damascene process method - Google Patents
Photoetching process method and dual damascene process method Download PDFInfo
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- CN110660733A CN110660733A CN201910940017.8A CN201910940017A CN110660733A CN 110660733 A CN110660733 A CN 110660733A CN 201910940017 A CN201910940017 A CN 201910940017A CN 110660733 A CN110660733 A CN 110660733A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
Abstract
The invention discloses a photoetching process method, which comprises the following steps: forming a double-layer photoresist structure consisting of a first bottom anti-reflection coating, a first photoresist layer, a second bottom anti-reflection coating and a second photoresist layer which are sequentially stacked on the surface of a semiconductor substrate; step two, adopting a first photomask to carry out a first exposure process so as to transfer the first graph structure to the first photoresist layer; step three, adopting a second photomask to carry out a second exposure process so as to transfer the second graph structure to a second photoresist layer; and step four, developing the double-layer photoresist structure, etching the semiconductor substrate by taking the developed double-layer photoresist structure as a mask, and simultaneously transferring the first graph structure and the second graph structure to the semiconductor substrate, wherein the first graph structure is positioned at the bottom of the second graph structure. The invention also discloses a dual damascene process. The invention can form two layers of patterns by adopting one-time developing and one-time etching processes, and can improve the production efficiency and reliability.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a photolithography process.
A reworking method of a Dual Damssene (DD) through-hole (VIA) process.
Background
As shown in fig. 1A to fig. 1C, the schematic diagram of the device structure in each step of the existing dual damascene process is shown; the existing dual damascene process method comprises the following steps:
step one, as shown in fig. 1A, providing a semiconductor substrate such as a silicon wafer substrate, forming bottom metal layers 2 on the semiconductor substrate, and isolating bottom dielectric films 1 between the bottom metal layers 2. SiCOH is typically used for the bottom dielectric film 1. The bottom metal layer 2 is a bottom copper layer.
A first nitrogen Doped silicon carbide (NDC) layer 3, a first low-K dielectric layer 4 and a second DARC layer 5 are formed on the semiconductor substrate.
The material of the first low-K dielectric layer 4 comprises BD or BD ii. In the process below the 65nm node, the material of the low-K dielectric layer is generally BD and BD II, wherein BD is a dielectric material composed of elements such as C, H, O, Si and the like, and the K value is 2.5-3.3. BD ii is an improved version of BD.
The second DARC layer 5 is SiON or a nitrogen-free anti-reflective coating (NFDARC), and unlike a DARC composed of SiON, there is no nitrogen in the NFDARC.
A second NDC layer (not shown) is formed between the second DARC layer 5 and the first low K dielectric layer 4.
The first low-K dielectric layer 4 is in surface contact with the first NDC layer 3 through a TEOS layer (not shown). The TEOS layer is a silicon oxide layer formed by using TEOS as a Si source, and the K value of the TEOS layer is 3.9-4.2 and is higher than that of BD.
Step two, as shown in FIG. 1A, a third metal hard mask layer 7 is formed on the surface of the second DARC layer 5. The third metal hard mask layer 7 is made of TiN, and a Ti (Ti) layer 6 is formed between the TiN of the third metal hard mask layer 7 and the second DARC layer 5; an oxide layer 8 is formed on the top surface of the TiN of the third metallic hard mask layer 7.
And step three, as shown in fig. 1A, performing photoetching of the copper connecting line, namely, performing exposure and development to define a forming area of the copper connecting line, etching the third metal hard mask layer 7 according to the first photoetching definition, simultaneously etching the TiN layer 6 and the oxidation layer 8, and forming a graph structure consisting of a plurality of graphs 12a after etching.
Step four, as shown in fig. 1A, forming a Mask structure defining the through hole, including a three-Layer structure based on a coating, where the three-Layer structure includes an Organic underlayer structure (ODL) Layer 9, a silicon-based Hard Mask intermediate Layer structure (Si-O-based Hard Mask, SHB) Layer 10, and a Photoresist (PR) Layer 11.
Typically, the ODL layer 9 is a Carbon coating (Spin-On-Carbon, SOC), SOC is a high Carbon polymer, and the SHB layer 10 is a silicon bottom anti-reflective coating (BARC).
Step five, as shown in fig. 1A, performing photolithography development on the through hole, and opening a formation region of the through hole, that is, an area corresponding to the mark 13a in the developed PR layer 11.
And sixthly, as shown in fig. 1B, etching is carried out by taking the developed PR layer 11 as a mask until the PR layer is etched into the first low-K dielectric layer 4 and an opening 13B of the through hole is formed. The ODL layer 9, the SHB layer 10 and the PR layer 11 are then removed.
And seventhly, as shown in fig. 1C, continuing to etch by using the third metal hard mask layer 7 as a mask until the trench 12 of the copper connection line and the opening 13 of the through hole are formed in the first low-K dielectric layer 4. The opening 13 is formed to extend downward on the basis of the opening 13B in fig. 1B.
Then, the copper wiring and the via hole, which are composed of copper filled in the opening 13, are formed by simultaneously filling copper in the trench 12 and the opening 13, and the copper wiring is composed of copper filled in the trench 12. The via connects the copper interconnect to the bottom metal layer 2.
As can be seen from the above, in the conventional method, the exposure and development are performed once in the third and fifth steps, so that the copper wire and hole processes in the subsequent stage are performed twice in the prior art, and thus the silicon wafer needs to be subjected to the photolithography and etching twice, so that the alignment problem needs to be considered, the whole process also needs much time, and the productivity and the machine performance of the Fab are affected.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a photoetching process method, which can form two layers of patterns by adopting one-time developing and one-time etching processes and can improve the production efficiency and reliability. Therefore, the invention also provides a dual damascene process.
In order to solve the technical problem, the photoetching process method provided by the invention comprises the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming a double-layer photoresist structure on the surface of the semiconductor substrate, wherein the double-layer photoresist structure comprises a first bottom anti-reflection coating, a first photoresist layer, a second bottom anti-reflection coating and a second photoresist layer which are sequentially stacked.
The exposure energy of the first photoresist layer is different from that of the second photoresist layer, the first bottom anti-emission coating is used as the bottom anti-emission coating when the first photoresist layer is exposed, and the second bottom anti-emission coating is used as the bottom anti-emission coating when the second photoresist layer is exposed.
And secondly, performing a first exposure process, wherein the first exposure process is defined by a first photomask with a first graph structure, the first exposure process optically focuses on the first photoresist layer and adopts exposure energy for fully exposing the first photoresist layer, so that the first graph structure is transferred to the first photoresist layer, and the first graph structure is not displayed on the second photoresist layer by utilizing the difference value of the exposure energy of the first photoresist layer and the exposure energy of the second photoresist layer.
And step three, performing a second exposure process, wherein the second exposure process is defined by a second photomask with a second graph structure, and the second exposure process optically focuses on the second photoresist layer and adopts exposure energy for fully exposing the first photoresist layer so as to transfer the second graph structure to the second photoresist layer.
Developing the double-layer photoresist structure after the two-time exposure process, and etching the semiconductor substrate by using the developed double-layer photoresist structure as a mask, wherein the first graph structure and the second graph structure are simultaneously transferred into the semiconductor substrate by etching, and the first graph structure is positioned at the bottom of the second graph structure; and then, removing the double-layer photoresist structure.
In a further improvement, the first bottom anti-reflection coating is formed by spin coating.
In a further refinement, the second bottom antireflective coating employs a solvent that does not dissolve the first photoresist layer.
In a further improvement, the second bottom anti-reflection coating is formed by vapor deposition.
The further improvement is that the sequence of the second step and the third step can be interchanged.
In a further improvement, the pattern of the first pattern structure is located at the bottom of a partial pattern of the second pattern structure and the pattern of the first pattern structure is in contact with the corresponding pattern of the second pattern structure at the top.
The further improvement is that the first exposure process and the second exposure process are exposed by an immersion lithography machine, the second photoresist layer is provided with a waterproof layer, and the second bottom anti-reflection coating is dissolved in water.
In order to solve the technical problem, the dual damascene process method provided by the invention comprises the following steps:
providing a semiconductor substrate with an interlayer film formed on the surface, wherein a bottom layer copper connecting line is formed at the bottom of the interlayer film, and the interlayer film is used for forming the copper connecting line and a through hole.
And forming a double-layer photoresist structure on the surface of the interlayer film, wherein the double-layer photoresist structure comprises a first bottom anti-reflection coating, a first photoresist layer, a second bottom anti-reflection coating and a second photoresist layer which are sequentially stacked.
The exposure energy of the first photoresist layer is different from that of the second photoresist layer, the first bottom anti-emission coating is used as the bottom anti-emission coating when the first photoresist layer is exposed, and the second bottom anti-emission coating is used as the bottom anti-emission coating when the second photoresist layer is exposed.
Step two, performing a first exposure process, wherein the first exposure process is defined by a first photomask with a first graph structure, the first exposure process optically focuses on the first photoresist layer and adopts exposure energy for fully exposing the first photoresist layer, so that the first graph structure is transferred to the first photoresist layer, and the first graph structure is not displayed on the second photoresist layer by utilizing the difference value of the exposure energy of the first photoresist layer and the exposure energy of the second photoresist layer; the first pattern structure is a pattern structure of the through hole.
Step three, carrying out a second exposure process, wherein the second exposure process is defined by a second photomask with a second graph structure, and the second exposure process optically focuses on the second photoresist layer and adopts exposure energy for fully exposing the first photoresist layer so as to transfer the second graph structure to the second photoresist layer; the second graph structure is the graph structure of the copper connecting line.
Developing the double-layer photoresist structure after the two-time exposure process, and etching the interlayer film by using the developed double-layer photoresist structure as a mask, wherein the etching simultaneously transfers the first graph structure and the second graph structure into the interlayer film, the graph of the first graph structure is a hole-shaped opening, and the second graph structure is a groove in the interlayer film; and then, removing the double-layer photoresist structure.
And fifthly, filling copper in the first graph structure and the second graph structure of the interlayer film, forming the through hole by the copper filled in the hole-shaped opening of the first graph structure, forming the copper connecting line by the copper filled in the groove of the second graph structure, enabling the bottom of the through hole to be in contact with the bottom layer copper connecting line, and connecting the top of the through hole with the copper connecting line.
In a further improvement, the first bottom anti-reflection coating is formed by spin coating.
In a further refinement, the second bottom antireflective coating employs a solvent that does not dissolve the first photoresist layer.
In a further improvement, the second bottom anti-reflection coating is formed by vapor deposition.
The further improvement is that the sequence of the second step and the third step can be interchanged.
In a further improvement, the pattern of the first pattern structure is located at the bottom of a partial pattern of the second pattern structure and the pattern of the first pattern structure is in contact with the corresponding pattern of the second pattern structure at the top.
The further improvement is that the semiconductor substrate is a silicon substrate, and the interlayer film adopts a low-K dielectric layer.
The further improvement is that the first exposure process and the second exposure process are exposed by an immersion lithography machine, the second photoresist layer is provided with a waterproof layer, and the second bottom anti-reflection coating is dissolved in water.
The invention can form two layers of patterns by adopting a double-layer photoresist structure and adopting one-time developing and one-time etching processes, and can improve the production efficiency and the reliability. Therefore, the invention also provides a dual damascene process.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C are schematic views of device structures in steps of a conventional dual damascene process;
FIG. 2 is a flow chart of a method of a lithographic process according to an embodiment of the invention;
FIGS. 3A-3D are schematic views of device structures at various steps of a photolithography process in accordance with embodiments of the present invention;
fig. 4A to fig. 4E are schematic views of device structures in steps of a dual damascene process method according to an embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of a photolithography process according to an embodiment of the present invention; as shown in fig. 3A to fig. 3D, the schematic views of the device structure in the steps of the photolithography process method according to the embodiment of the present invention are shown, and the photolithography process method according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 101, and forming a dual-layer photoresist structure 106 on a surface of the semiconductor substrate 101, where the dual-layer photoresist structure 106 includes a first bottom anti-reflection coating 102, a first photoresist layer 103, a second bottom anti-reflection coating 104, and a second photoresist layer 105, which are sequentially stacked.
The exposure energy of the first photoresist layer 103 is different from the exposure energy of the second photoresist layer 105, the first bottom anti-emission coating is used as a bottom anti-emission coating when the first photoresist layer 103 is exposed, and the second bottom anti-emission coating is used as a bottom anti-emission coating when the second photoresist layer 105 is exposed.
The first BARC layer 102 is formed by spin coating.
The second bottom anti-reflective coating layer 104 employs a solvent that does not dissolve the first photoresist layer 103. The second BARC layer 104 is formed by vapor deposition. And when the subsequent first exposure process and the second exposure process are both exposed by adopting an immersion lithography machine, the second photoresist layer 105 is provided with a waterproof layer, and the second bottom anti-reflection coating 104 is dissolved in water.
Step two, as shown in fig. 3B, a first exposure process is performed, where the first exposure process is defined by using a first photomask with a first pattern structure, the first exposure process focuses light on the first photoresist layer 103 and uses exposure energy for fully exposing the first photoresist layer 103 to transfer the first pattern structure to the first photoresist layer 103, and the first pattern structure is not displayed on the second photoresist layer 105 by using a difference between the exposure energy of the first photoresist layer 103 and the exposure energy of the second photoresist layer 105. In fig. 3B, a pattern 107a is a pattern of the first pattern structure transferred onto the first photoresist layer 103, i.e. an exposed region.
Step three, as shown in fig. 3B, a second exposure process is performed, where the second exposure process is defined by using a second photomask with a second pattern structure, and the second exposure process focuses light on the second photoresist layer 105 and uses exposure energy to fully expose the first photoresist layer 103, so that the second pattern structure is transferred to the second photoresist layer 105. In fig. 3B, a pattern 108a is a pattern of the first pattern structure transferred onto the first photoresist layer 103.
Step four, as shown in fig. 3C, the double-layer photoresist structure 106 after the two exposure processes is developed, and the patterns 108b and 107b are both developed patterns.
As shown in fig. 3D, etching the semiconductor substrate 101 with the developed double-layer photoresist structure 106 as a mask, wherein the etching simultaneously transfers the first pattern structure and the second pattern structure into the semiconductor substrate 101, and the first pattern structure is located at the bottom of the second pattern structure; the bilayer photoresist structure 106 is then removed.
The graph of the first graph structure is positioned at the bottom of the partial graph of the second graph structure, and the graph of the first graph structure is contacted with the graph of the second graph structure corresponding to the top.
As shown in fig. 3D, the graph 107 is a graph in the first graph structure, and actually, a plurality of graphs 107 can be included in the first graph structure, and only one graph 107 is shown in fig. 3D; the graphic 108 is a graphic in the second graphic structure, and actually, a plurality of the graphics 108 can be included in the second graphic structure, and only one graphic 108 is shown in fig. 3D. Shown in fig. 3D, the top of the graphic 107 is in contact with, i.e., in communication with, the bottom of the graphic 108. In other embodiments, the bottom of the graphic 108 can also be provided without the corresponding graphic 107.
The front and back sequences of the second step and the third step of the photoetching process method can be interchanged.
The photoetching process method provided by the embodiment of the invention can form two layers of patterns by adopting the double-layer photoresist structure 106 and adopting one-time development and one-time etching processes, and can improve the production efficiency and reliability.
Fig. 4A to 4E are schematic diagrams of device structures in steps of a dual damascene process method according to an embodiment of the present invention; the dual damascene process method provided by the embodiment of the invention comprises the following steps:
step one, as shown in fig. 4A, providing a semiconductor substrate 101 with an interlayer film 201 formed on the surface, wherein a bottom layer copper wire 202 is formed on the bottom of the interlayer film 201, and a copper wire 204 and a through hole 203 are formed in the interlayer film 201.
As shown in fig. 4A, a double-layer photoresist structure 106 is formed on the surface of the interlayer film 201, and the double-layer photoresist structure 106 includes a first bottom anti-reflective coating 102, a first photoresist layer 103, a second bottom anti-reflective coating 104, and a second photoresist layer 105, which are sequentially stacked.
The exposure energy of the first photoresist layer 103 is different from the exposure energy of the second photoresist layer 105, the first bottom anti-emission coating is used as a bottom anti-emission coating when the first photoresist layer 103 is exposed, and the second bottom anti-emission coating is used as a bottom anti-emission coating when the second photoresist layer 105 is exposed.
The first BARC layer 102 is formed by spin coating.
The second bottom anti-reflective coating layer 104 employs a solvent that does not dissolve the first photoresist layer 103. The second BARC layer 104 is formed by vapor deposition. And when the subsequent first exposure process and the second exposure process are both exposed by adopting an immersion lithography machine, the second photoresist layer 105 is provided with a waterproof layer, and the second bottom anti-reflection coating 104 is dissolved in water.
The semiconductor substrate 101 is a silicon substrate, and the interlayer film 201 is a low-K dielectric layer. A semiconductor device is formed on the semiconductor substrate 101, and a bottom dielectric film is formed on the semiconductor substrate 101 and isolated between the bottom copper wires 202. The underlying dielectric film is typically SiCOH.
Step two, as shown in fig. 4B, performing a first exposure process, where the first exposure process is defined by using a first photomask with a first pattern structure, the first exposure process focuses light on the first photoresist layer 103 and uses exposure energy to fully expose the first photoresist layer 103, so that the first pattern structure is transferred onto the first photoresist layer 103, and the first pattern structure is not displayed on the second photoresist layer 105 by using a difference between the exposure energy of the first photoresist layer 103 and the exposure energy of the second photoresist layer 105; the first pattern structure is a pattern structure of the through hole 203.
In fig. 3B, a pattern 107a is a pattern of the first pattern structure transferred onto the first photoresist layer 103, i.e. an exposed region.
Step three, as shown in fig. 4B, performing a second exposure process, where the second exposure process is defined by using a second photomask with a second pattern structure, and the second exposure process focuses light on the second photoresist layer 105 and uses exposure energy to fully expose the first photoresist layer 103, so that the second pattern structure is transferred onto the second photoresist layer 105; the second pattern structure is a pattern structure of the copper connecting line 204.
In fig. 3B, a pattern 108a is a pattern of the first pattern structure transferred onto the first photoresist layer 103.
Step four, as shown in fig. 4C, the double-layer photoresist structure 106 after the two exposure processes is developed, and the patterns 108b and 107b are both developed patterns.
As shown in fig. 4D, etching the interlayer film 201 by using the developed double-layer photoresist structure 106 as a mask, wherein the etching simultaneously transfers the first pattern structure and the second pattern structure into the interlayer film 201, in the interlayer film 201, the pattern of the first pattern structure is a hole-shaped opening 107, and the second pattern structure is a trench 108; the bilayer photoresist structure 106 is then removed.
The graph of the first graph structure is positioned at the bottom of the partial graph of the second graph structure, and the graph of the first graph structure is contacted with the graph of the second graph structure corresponding to the top.
Only one pattern 107, i.e. hole-like openings 107, and one pattern 108, i.e. trenches 108, are shown in fig. 4D. Shown in fig. 4D, the top of the graphic 107 is in contact with, i.e., in communication with, the bottom of the graphic 108. In other embodiments, the bottom of the graphic 108 can also be provided without the corresponding graphic 107.
Step five, as shown in fig. 4E, copper is filled in the first pattern structure and the second pattern structure of the interlayer film 201, the via 203 is composed of copper filled in the hole-shaped opening 107 of the first pattern structure, the copper wiring 204 is composed of copper filled in the trench 108 of the second pattern structure, the bottom of the via 203 is in contact with the bottom copper wiring 202, and the top of the via 203 is connected with the copper wiring 204.
The sequence of the second step and the third step can be interchanged.
By adopting the double-layer photoresist structure 106, the invention can form two layers of patterns by adopting one-time developing and one-time etching processes, and can improve the production efficiency and reliability. Therefore, the invention also provides a dual damascene process.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A photoetching process method is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a double-layer photoresist structure on the surface of the semiconductor substrate, wherein the double-layer photoresist structure comprises a first bottom anti-reflection coating, a first photoresist layer, a second bottom anti-reflection coating and a second photoresist layer which are sequentially stacked;
the exposure energy of the first photoresist layer is different from the exposure energy of the second photoresist layer, the first bottom anti-emission coating is used as the bottom anti-emission coating when the first photoresist layer is exposed, and the second bottom anti-emission coating is used as the bottom anti-emission coating when the second photoresist layer is exposed;
step two, performing a first exposure process, wherein the first exposure process is defined by a first photomask with a first graph structure, the first exposure process optically focuses on the first photoresist layer and adopts exposure energy for fully exposing the first photoresist layer, so that the first graph structure is transferred to the first photoresist layer, and the first graph structure is not displayed on the second photoresist layer by utilizing the difference value of the exposure energy of the first photoresist layer and the exposure energy of the second photoresist layer;
step three, carrying out a second exposure process, wherein the second exposure process is defined by a second photomask with a second graph structure, and the second exposure process optically focuses on the second photoresist layer and adopts exposure energy for fully exposing the first photoresist layer so as to transfer the second graph structure to the second photoresist layer;
developing the double-layer photoresist structure after the two-time exposure process, and etching the semiconductor substrate by using the developed double-layer photoresist structure as a mask, wherein the first graph structure and the second graph structure are simultaneously transferred into the semiconductor substrate by etching, and the first graph structure is positioned at the bottom of the second graph structure; and then, removing the double-layer photoresist structure.
2. A lithographic process as in claim 1, wherein: the first bottom anti-reflection coating is formed in a spin coating mode.
3. A lithographic process as in claim 1, wherein: the second bottom antireflective coating employs a solvent that does not dissolve the first photoresist layer.
4. A lithographic process as in claim 3, wherein: the second bottom anti-reflection coating is formed by adopting a vapor deposition mode.
5. A lithographic process as in claim 1, wherein: the sequence of the second step and the third step can be interchanged.
6. A lithographic process as in claim 1, wherein: the graph of the first graph structure is positioned at the bottom of the partial graph of the second graph structure, and the graph of the first graph structure is contacted with the graph of the second graph structure corresponding to the top.
7. A lithographic process as in claim 4, wherein: and the first exposure process and the second exposure process are exposed by adopting an immersion lithography machine, the second photoresist layer is provided with a waterproof layer, and the second bottom anti-reflection coating is dissolved in water.
8. A dual damascene process method is characterized by comprising the following steps:
providing a semiconductor substrate with an interlayer film formed on the surface, wherein a bottom layer copper connecting wire is formed at the bottom of the interlayer film, and the interlayer film is used for forming the copper connecting wire and a through hole;
forming a double-layer photoresist structure on the surface of the interlayer film, wherein the double-layer photoresist structure comprises a first bottom anti-reflection coating, a first photoresist layer, a second bottom anti-reflection coating and a second photoresist layer which are sequentially stacked;
the exposure energy of the first photoresist layer is different from the exposure energy of the second photoresist layer, the first bottom anti-emission coating is used as the bottom anti-emission coating when the first photoresist layer is exposed, and the second bottom anti-emission coating is used as the bottom anti-emission coating when the second photoresist layer is exposed;
step two, performing a first exposure process, wherein the first exposure process is defined by a first photomask with a first graph structure, the first exposure process optically focuses on the first photoresist layer and adopts exposure energy for fully exposing the first photoresist layer, so that the first graph structure is transferred to the first photoresist layer, and the first graph structure is not displayed on the second photoresist layer by utilizing the difference value of the exposure energy of the first photoresist layer and the exposure energy of the second photoresist layer; the first graph structure is a graph structure of the through hole;
step three, carrying out a second exposure process, wherein the second exposure process is defined by a second photomask with a second graph structure, and the second exposure process optically focuses on the second photoresist layer and adopts exposure energy for fully exposing the first photoresist layer so as to transfer the second graph structure to the second photoresist layer; the second graph structure is a graph structure of the copper connecting line;
developing the double-layer photoresist structure after the two-time exposure process, and etching the interlayer film by using the developed double-layer photoresist structure as a mask, wherein the etching simultaneously transfers the first graph structure and the second graph structure into the interlayer film, the graph of the first graph structure is a hole-shaped opening, and the second graph structure is a groove in the interlayer film; then, removing the double-layer photoresist structure;
and fifthly, filling copper in the first graph structure and the second graph structure of the interlayer film, forming the through hole by the copper filled in the hole-shaped opening of the first graph structure, forming the copper connecting line by the copper filled in the groove of the second graph structure, enabling the bottom of the through hole to be in contact with the bottom layer copper connecting line, and connecting the top of the through hole with the copper connecting line.
9. The dual damascene process of claim 8, wherein: the first bottom anti-reflection coating is formed in a spin coating mode.
10. The dual damascene process of claim 8, wherein: the second bottom antireflective coating employs a solvent that does not dissolve the first photoresist layer.
11. The dual damascene process of claim 10, wherein: the second bottom anti-reflection coating is formed by adopting a vapor deposition mode.
12. The dual damascene process of claim 8, wherein: the sequence of the second step and the third step can be interchanged.
13. The dual damascene process of claim 8, wherein: the graph of the first graph structure is positioned at the bottom of the partial graph of the second graph structure, and the graph of the first graph structure is contacted with the graph of the second graph structure corresponding to the top.
14. The dual damascene process of claim 1, wherein: the semiconductor substrate is a silicon substrate, and the interlayer film adopts a low-K dielectric layer.
15. The dual damascene process of claim 11, wherein: and the first exposure process and the second exposure process are exposed by adopting an immersion lithography machine, the second photoresist layer is provided with a waterproof layer, and the second bottom anti-reflection coating is dissolved in water.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312657A (en) * | 2020-03-24 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for forming dual damascene pattern through double exposure |
| CN112382611A (en) * | 2020-11-13 | 2021-02-19 | 上海华力集成电路制造有限公司 | Dual damascene process |
| CN112713084A (en) * | 2020-12-29 | 2021-04-27 | 中国科学院微电子研究所 | Method for manufacturing semiconductor structure |
| CN113394080A (en) * | 2021-05-10 | 2021-09-14 | 上海华力集成电路制造有限公司 | Method for reducing photoresist poisoning by double patterning process |
| CN114686057A (en) * | 2020-12-28 | 2022-07-01 | 中国科学院微电子研究所 | Anti-reflection coating composition for patterning and patterning method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050277064A1 (en) * | 2004-06-14 | 2005-12-15 | Bae Systems Information & Electronic Systems Integration, Inc. | Lithographic semiconductor manufacturing using a multi-layered process |
| CN101546727A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Process for Damascus |
| CN104155844A (en) * | 2013-05-14 | 2014-11-19 | 台湾积体电路制造股份有限公司 | Photomask with three states for forming multiple layer patterns with a single exposure |
| CN106468859A (en) * | 2015-08-21 | 2017-03-01 | 台湾积体电路制造股份有限公司 | Method in order to define multiple layer patterns using re-expose |
-
2019
- 2019-09-30 CN CN201910940017.8A patent/CN110660733B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050277064A1 (en) * | 2004-06-14 | 2005-12-15 | Bae Systems Information & Electronic Systems Integration, Inc. | Lithographic semiconductor manufacturing using a multi-layered process |
| CN101546727A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Process for Damascus |
| CN104155844A (en) * | 2013-05-14 | 2014-11-19 | 台湾积体电路制造股份有限公司 | Photomask with three states for forming multiple layer patterns with a single exposure |
| CN106468859A (en) * | 2015-08-21 | 2017-03-01 | 台湾积体电路制造股份有限公司 | Method in order to define multiple layer patterns using re-expose |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312657A (en) * | 2020-03-24 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for forming dual damascene pattern through double exposure |
| CN112382611A (en) * | 2020-11-13 | 2021-02-19 | 上海华力集成电路制造有限公司 | Dual damascene process |
| CN114686057A (en) * | 2020-12-28 | 2022-07-01 | 中国科学院微电子研究所 | Anti-reflection coating composition for patterning and patterning method |
| CN112713084A (en) * | 2020-12-29 | 2021-04-27 | 中国科学院微电子研究所 | Method for manufacturing semiconductor structure |
| CN113394080A (en) * | 2021-05-10 | 2021-09-14 | 上海华力集成电路制造有限公司 | Method for reducing photoresist poisoning by double patterning process |
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