CN110660542B - Chip resistor element and chip resistor element assembly - Google Patents

Abstract

The invention provides a chip resistor element and a chip resistor element assembly. The invention provides a chip resistor element, comprising: an insulating substrate having a first surface and a second surface that face each other; a resistive layer disposed on the first face; a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; and a third terminal which is arranged on the insulating substrate between the first terminal and the second terminal, is connected to the resistive layer, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the first terminal and the third terminal, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the second terminal and the third terminal.

Description

Chip resistor element and chip resistor element assembly

The present application is a divisional application of the invention patent application "chip resistor and chip resistor element assembly" filed on 2016, 26 and 201610738091.8.

Technical Field

The invention relates to a chip resistor element and a chip resistor element assembly.

Background

Chip resistors (chip resistors) are chip components for realizing precision resistors, and have functions of regulating current and reducing voltage in an electronic circuit.

In a circuit design using a resistor, if the resistor is damaged by an external impact (Surge), static electricity, or the like to cause a failure (e.g., a short circuit), all circuits of a power supply flow into an Integrated Circuit (IC), and thus a serious secondary damage may occur in the IC.

To prevent these defects from occurring, a plurality of resistors may be used in designing a circuit. However, these circuit designs will inevitably increase the amount of space used by the circuit substrate.

In particular, in the case of mobile devices that are becoming smaller and more precise, it is not preferable to increase the space usage of the circuit board too much in order to ensure the above-mentioned circuit stability, and therefore, it is necessary to develop a chip resistor element that more effectively regulates the current.

[ Prior art documents ]

[ patent document ]

(patent document 1) U.S. patent publication No. 2008/0303627

Disclosure of Invention

An object of one embodiment of the present invention is to provide a chip resistor element capable of ensuring stable connection with a circuit board even when the chip resistor element is miniaturized, and a chip resistor element assembly.

In one aspect of the present invention, there is provided a chip resistor element including: an insulating substrate having a first surface and a second surface that face each other; a resistive layer disposed on the first face; a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; and a third terminal which is arranged on the insulating substrate between the first terminal and the second terminal, is connected to the resistive layer, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the first terminal and the third terminal, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the second terminal and the third terminal.

In an embodiment, the spacing at the edge position of the first face may be 0.01mm to 0.10mm greater than the spacing at the center of the first face.

In one embodiment, the first to third electrodes may respectively include: first to third internal electrodes arranged on the resistive layer; and first to third external electrodes covering the first to third internal electrodes, respectively.

In an embodiment, the method may further include: and resistive protection layers disposed on the resistive layer between the first and third terminals and between the second and third terminals, respectively.

In an embodiment, the resistive protection layer may have a region overlapping with a region of the first to third internal electrodes disposed at the center of the first face.

In one embodiment, the resistive protective layer may have a raised area.

In an embodiment, at least one of the first to third external electrodes may have a recessed region corresponding to the protruding region.

In one embodiment, the resistive layer may include a first resistive layer and a second resistive layer separated from each other, and the third internal electrode is disposed between the first resistive layer and the second resistive layer.

In one embodiment, the first and second terminals respectively include: a first rear surface electrode and a second rear surface electrode arranged on a second surface of the insulating substrate facing the first surface; and first and second side electrodes connected to the first and second back electrodes and the first and second internal electrodes.

In one aspect of the present invention, there is provided a chip resistor element including: an insulating substrate having a first surface and a second surface that face each other; a resistive layer disposed on the first face; a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; a third terminal arranged on the insulating substrate between the first terminal and the second terminal and connected to the resistive layer; and a resistive protection layer disposed on the resistive layer between the first and third terminals and between the second and third terminals, respectively, and having a length at a center of the first face longer than a length at an edge position of the first face.

In an embodiment, the length at the center of the resistive protection layer may be 0.01mm to 0.10mm longer than the length at the edge position.

In one aspect of the present invention, there is provided a chip resistor element assembly including: a printed circuit board having a plurality of electrode pads; and a chip resistor element disposed on the printed circuit board and electrically connected to the plurality of electrode substrates, and the chip resistor element includes: an insulating substrate having a first surface and a second surface that face each other; a resistive layer disposed on the first face; a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; and a third terminal which is arranged on the insulating substrate between the first terminal and the second terminal, is connected to the resistive layer, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the first terminal and the third terminal, and has a longer interval at a center of the first surface than at an edge position of the first surface with respect to an interval between the second terminal and the third terminal.

According to one aspect of the present invention, it is possible to provide a resistor element and a chip resistor element assembly which are excellent in space efficiency when mounting a substrate and which can realize stable connection with a circuit board.

The various advantageous advantages and effects of the present invention are not limited to the above-described contents, which can be more easily understood in the course of describing the embodiments of the present invention.

Drawings

Fig. 1 is a perspective view showing a chip resistor element according to an embodiment of the present invention.

Fig. 2 is a plan view showing the chip resistance element illustrated in fig. 1 as viewed from the I direction.

Fig. 3 is a side sectional view taken along ii-ii' of the chip resistance element illustrated in fig. 1.

Fig. 4 is a cross-sectional view showing a chip resistor element according to an embodiment of the present invention.

Fig. 5 and 6 are plan views showing another form of the first to third terminals that can be used in one embodiment of the present invention.

Fig. 7 is a perspective view showing a chip resistor element assembly including a substrate on which a chip resistor element according to an embodiment of the present invention is mounted.

Fig. 8 is a side sectional view taken along iii-iii' of the chip resistance element assembly illustrated in fig. 7.

Description of the symbols

10: circuit boards 11, 12, and 13: first to third electrode pads

14: solder 100: chip resistor element

110: insulating substrates 120, 121, 122: resistance layer

131. 132, 133: first to third terminals 140: resistor protection layer

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. However, the embodiment of the present invention may be modified into various different forms, and the scope of the present invention is not limited to the embodiment described below. Further, the embodiments of the present invention are provided to explain the present invention more fully to those having average knowledge in the technical field to which the present invention pertains. Therefore, the shapes, sizes, and the like of the elements in the drawings may be exaggerated for clarity of explanation.

Fig. 1 is a perspective view showing a chip resistance element according to an embodiment of the present invention; fig. 2 is a plan view showing the chip resistance element illustrated in fig. 1 as viewed from the I direction; fig. 3 is a side sectional view taken along ii-ii' of the chip resistance element illustrated in fig. 1.

Referring to fig. 1 and 3, a chip resistor element 100 according to an embodiment of the present invention may include an insulating substrate 110, a resistive layer 120, and first to third terminals 131, 132, and 133.

The insulating substrate 110 includes a resistive layer 120 disposed on one surface thereof. The insulating substrate 110 supports the thin resistive layer 120 and can secure the rigidity of the resistive element 100. The insulating substrate 110 may be made of a material having excellent thermal conductivity. The insulating substrate 110 may effectively release heat generated from the resistive layer 120 during use to the outside.

For example, the insulating substrate 110 may be, for example, alumina (Al)₂O₃) Such as a ceramic or polymer substrate. In a specific example, the insulating substrate 110 may be an alumina substrate obtained by anodizing (anodizing) a surface of thin aluminum.

The resistive layer 120 is disposed on one surface of the insulating substrate 110. The resistive layer 120 may be connected to first to third terminals 131, 132, and 133 isolated from each other to serve as two resistive elements. As the resistive layer 120, various compounds such as metals, alloys, or oxides can be used. For example, it may contain at least one of a Cu-Ni alloy, a Ni-Cr alloy, a Ru oxide, a Si oxide, Mn and a Mn alloy.

The resistance value of the resistive layer 120 may be determined by trimming (trimming). The trimming refers to a partial removal process such as fine cutting (trimming) performed after the resistive layer 120 is formed to obtain a resistance value required for circuit design.

As shown in fig. 1, the first terminal 131 and the second terminal 132 are disposed at both ends of the insulating substrate 110 and may be connected to both sides of the resistive layer 120. The third terminal 133 may be disposed on the resistive layer 120 between the first terminal 131 and the second terminal 132 separately from the first terminal 131 and the second terminal 132. In such an arrangement, two resistance elements can be realized in which the third terminal 133 is a common terminal and the first and second terminals 131 and 132 are independent terminals. Unlike the present embodiment, the resistive layer 120 may be provided separately from each other as two resistive elements (refer to fig. 4).

As shown in fig. 2, when viewed from the lower surface (I direction) of the chip resistance element 100, the first to third terminals 131, 132, and 133 have a longer interval W1 at the center C in the longitudinal direction L of the chip resistance element 100 than an interval W2 at the edge position E. Specifically, as for the interval between the first terminal 131 and the third terminal 133, the interval at the center C is longer than the interval W2 at the edge position E, and the interval between the second terminal 132 and the third terminal 133 is also arranged in such a manner that the interval at the center C is longer than the interval W2 at the edge position E.

In order to realize the arrangement as described above, in the present embodiment, the regions where the first terminal 131 and the second terminal 132 are in contact with the resistive protection layer 140 are formed in a concave curved shape so that the first terminal 131 and the second terminal 132 have a concave region at the center C, but the present invention is not limited thereto, and the region where the third terminal 133 and the resistive protection layer 140 are in contact may be formed to have a concave region so that the third terminal 133 has a concave region. Specific examples relating to this will be described below.

As the size of the chip resistance element is gradually miniaturized, the distance between the terminals of the chip resistance element is also gradually reduced. Therefore, when the chip resistor element is soldered to the circuit board, an extra solder may be generated due to a process error, and the extra solder may electrically connect the adjacent terminals to cause a short circuit (short) or the like.

In the first terminal and the second terminal disposed at both ends of the chip resistance element, even if there is an excess solder, the excess solder can be discharged from the side surfaces of the chip resistance element, but in the third terminal disposed at the center of the chip resistance element, there is a lack of space for discharging the excess solder compared to the first terminal and the second terminal, and therefore the following problems are likely to occur: the excess solder is pushed to the center of the chip resistor element, and the first electrode and the third electrode or the second electrode and the third electrode are connected by the solder, thereby causing a failure.

In the present embodiment, the distance between the first to third terminals 131, 132, 133 is set to be larger at the center C than at the edge position E, so that even if excess solder occurs at one terminal during mounting, the excess solder can be discharged to an adjacent terminal, and thus the problem of short circuit can be solved.

At this time, the interval W1 at the center C in the length direction L of the chip resistance element 100 may be arranged to be 0.01mm to 0.10mm larger than the interval W2 at the edge position E. Table 1 below is an experimental example of testing whether a failure occurs according to a change in the interval between the first terminal and the third terminal and the interval between the second terminal and the third terminal. In the following experimental example, in which the width of the third terminal 133 of the chip resistive element having the length of 0.7mm and the width of 0.4mm was fixed to 0.15mm, and the interval between the first terminal 131 and the third terminal 133 and the interval between the second terminal 132 and the third terminal 133 were changed according to the center C and the edge position E, the experimental example shows the result of manufacturing 1000 resistive elements per group. In each group, when one or more defects occur, the result value is indicated as a fail. It can be seen that a failure occurred in the case where the difference W1-W2 between the spacing W1 at the center and the spacing W2 at the edge position was less than 0.01mm or more than 0.10 mm. In particular, the following were found: when the difference W1-W2 is less than 0.01mm, the solder is not discharged enough; if the difference between the intervals exceeds 0.10mm, the sizes of the first and second terminals 131 and 132 become too small, and therefore, poor welding occurs.

[ TABLE 1 ]

Group (Lot)	W1	W2	W1-W2	Results
					1	0.12㎜	0.12㎜	0.00㎜	Fail to be qualified
2	0.12㎜	0.115㎜	0.005㎜	Fail to be qualified
					3	0.12㎜	0.11㎜	0.01㎜	Qualified
4	0.12㎜	0.10㎜	0.02㎜	Qualified
					5	0.12㎜	0.80㎜	0.05㎜	Qualified
6	0.12㎜	0.06㎜	0.06㎜	Qualified
					7	0.12㎜	0.05㎜	0.07㎜	Qualified
8	0.12㎜	0.04㎜	0.08㎜	Qualified
					9	0.12㎜	0.03㎜	0.09㎜	Qualified
10	0.12㎜	0.02㎜	0.10㎜	Qualified
					11	0.12㎜	0.01㎜	0.11㎜	Fail to be qualified

As shown in fig. 3, the first to third terminals 131, 132, 133 respectively include first to third internal electrodes 131a, 132a, 133a disposed on the resistive layer 120 and first to third external electrodes 131b, 132b, 133b covering the first to third internal electrodes 131a, 132a, 133a, respectively. The internal electrodes include upper surface electrodes 131a, 132a, 133a arranged on the resistive layer 120. The internal electrodes of the first and second terminals 131 and 132 may include side electrodes 131c and 132c formed on both side surfaces of the insulating substrate 110 and rear electrodes 131d and 132d disposed on a second surface opposite to the first surface, in addition to the upper surface electrodes 131a and 132 a.

The first to third internal electrodes 131a, 132a, 133a may be formed through a printing process (firing after printing) or a deposition process using a conductive paste. The internal electrodes may function as seeds (seeds) in a plating metal process for forming the external electrodes 131b, 132b, 133 b. For example, the internal electrode may include at least one of silver (Ag), copper (Cu), nickel (Ni), platinum (Pt). The present invention is not limited thereto, and the first to third external electrodes 131b, 132b, and 133b may be formed by a barrel plating (barrel plating) method.

The external electrodes 131b, 132b, 133b of the first to third terminals may be formed by a plating metal process. The external electrodes 131b, 132b, 133b may include one of nickel (Ni), tin (Sn), lead (Pd), and chromium (Cr). For example, the external electrodes 131b, 132b, 133b may have a double layer of a nickel plating layer and a tin plating layer. The nickel plating layer may prevent a component (e.g., Ag) of the internal electrode from being leached into a solder component (leach) during component mounting, and the tin plating layer may be provided in order to be more easily combined with the solder component when mounting the component.

In addition, according to the chip resistor element 100 according to an embodiment of the present invention, the resistive layer 120 is first formed on one surface of the insulating substrate 110, and then the first to third terminals 131, 132, and 133 are formed by forming the first to third internal electrodes 131a, 132a, and 133a on the resistive layer 120, whereby the area of the resistive layer can be increased as compared with a case where the resistive layer is formed so as to overlap with the internal electrodes after the internal electrodes are first formed on the insulating substrate.

According to an embodiment of the present invention, the power of the chip resistor element 100 can be increased by increasing the area of the resistive layer 120, and the overlapping area of the resistive layer 120 and the first to third internal electrodes 131a, 132a, and 133a can be formed to a predetermined area by disposing the first to third internal electrodes 131a, 132a, and 133a on the resistive layer 120, whereby dispersion (unevenness) of the resistance value can be improved.

According to an embodiment of the present invention, alternatively, a first rear surface electrode 131d and a second rear surface electrode 132d are disposed on the other surface of the insulating substrate 110 so as to face the first internal electrode 131a and the second internal electrode 132 a. As described above, in the case where the first and second back electrodes 131d and 132d are disposed on the other surface of the insulating substrate 110, the first and second internal electrodes 131a and 132a and the first and second back electrodes 131d and 132d counteract the force of the resistive layer on the insulating substrate during the firing process, and thus the insulating substrate can be prevented from being bent due to the resistive layer.

Although not limited thereto, the first and second rear surface electrodes 131d and 132d may be formed by printing a conductive paste.

According to an embodiment of the present invention, a pair of side electrodes 131c and 132c connected to the first internal electrode and the second internal electrode, respectively, may be selectively disposed on both end surfaces of the laminate formed by disposing the insulating substrate 110, the resistive layer 120, and the first to third internal electrodes 131a, 132a, and 133 a.

The side electrodes 131c and 132c may be disposed in such a manner as to connect the first internal electrode 131a and the first back surface electrode 131d and the second internal electrode 132a and the second back surface electrode 132d, respectively. Therefore, a problem that current is concentrated on one surface of the insulating substrate 110 can be improved.

The pair of side electrodes 131c and 132c may be formed by a process of sputtering a conductive substance for forming the side electrodes 131c and 132c onto the end surfaces of the stacked body, but is not necessarily limited thereto.

In the present embodiment, as shown in fig. 2, a resistor protection layer 140 may be disposed on a surface of the resistor layer 120 to prevent the resistor layer 120 from being exposed to the outside or to protect the resistor layer 120 from an external impact. The resistive protection layer 140 covers the resistive layer 120 exposed between the first and third internal electrodes 131a and 133a and between the second and third internal electrodes 132a and 133a, however, in the region where the resistive protection layer 140 is in contact with the first and second internal electrodes 131a and 132a, the resistive protection layer 140 may cover the first and second internal electrodes 131a and 132a at a predetermined region W3. The predetermined area W3 may be formed by: after the first to third inner electrodes 131a, 132a, 133a are arranged, a liquid material for forming the resistive protective layer 140 is applied to the surface of the exposed resistive layer 120, and in a rolling process using a roller, the first to third inner electrodes 131a, 132a, 133a are covered with an excessive material, thereby forming the above-described predetermined region W3. The predetermined area W3 may cover an area of the third internal electrode 133a according to a direction in which the material substance is rolled by the roller, a surface of the roller, and a pattern in which the liquid material substance is applied, and the predetermined area W3 may cover an area of the first to third internal electrodes 131a, 132a, 133a, respectively. As described above, in the case where the surfaces of the first to third internal electrodes 131a, 132a, 133a are covered with the resistance protection layer 140, the plated metal layer is formed only at the portions not covered with the resistance protection layer 140, thereby forming the first to third external electrodes 131b, 132b, 133 b. Therefore, the shapes of the first to third terminals 131, 132, 133 can be changed by changing the shape of the resistive protection layer 140.

The shapes of the first to third terminals 131, 132, 133 may be deformed in a manner as shown in fig. 5 and 6. Fig. 5 and 6 are plan views showing another form of the first to third terminals that can be used in one embodiment of the present invention.

The chip resistor element 100A in fig. 5 is an example in which the shape of the third terminal 133' is changed; the patch resistive element 100B in fig. 6 is an example in which the shapes of all of the first to third terminals 131 ", 132", and 133 "are changed.

The resistive protection layer 140 may include Silicon (SiO)₂) Glass or polymer. In a specific example, the resistance protection layer 140 may be composed of a first layer as glass and a second layer as polymer, and the two layers may be formed before and after the resistance trimming process, respectively, according to requirements.

As one embodiment of the present invention, if the first to third internal electrodes 131a, 132a, 133a are disposed on the resistive layer 120, the first to third terminals 131, 132, 133 have a convex shape compared to the protective layer 140 even though the resistive protective layer 140 is disposed on the resistive layer 120, and thus, contact of the first to third terminals 131, 132, 133 with electrode pads disposed on a substrate can be more easily achieved when the substrate is mounted.

Fig. 4 is a cross-sectional view showing a chip resistor element 200 according to an embodiment of the present invention.

The patch resistive element 200 illustrated in fig. 4 may be understood to be similar to the patch resistive element 100 illustrated in fig. 1 to 3 except that the resistive layer 220 is separated into a first resistive layer 221 and a second resistive layer 222. Note that, if not specifically stated to the contrary, the components of the present embodiment can be understood with reference to the description of the same or similar components as those of the chip resistance element 100 shown in fig. 1 to 3.

In the chip resistor element 200 shown in fig. 4, the first terminal 231 and the second terminal 232 may include a first inner electrode 231a and a second inner electrode 232a, a first outer electrode 231b and a second outer electrode 232b, a first side electrode 231c and a second side electrode 232c, and a first back electrode 231d and a second back electrode 232 d. The third terminal 233 may include a third inner electrode 233a and a third outer electrode 233 b. The first to third internal electrodes 231a, 232a, 233a may be arranged in such a manner that one region is in direct contact with the insulating substrate 210.

The resistive layer 220 is disposed on one side of the insulating substrate 210, and includes: a first resistance layer 221 connected to the first electrode 231 and the third electrode 233 to form a resistance; and a second resistance layer 222 connected to the second electrode portions 232 and the third electrode portions 233 to form a resistance, and the first resistance portion and the second resistance portion may be arranged as the first resistance layer 221 and the second resistance layer 222 separated from each other. By disposing the first resistance portion and the second resistance portion separately from the first resistance layer 221 and the second resistance layer 222, there can be an advantage that substances constituting the first resistance portion and the second resistance portion can be made different.

Fig. 7 is a perspective view showing a chip resistance element assembly including a substrate on which a chip resistance element according to an embodiment of the present invention is mounted; fig. 8 is a cross-sectional side view taken along iii-iii' of the chip resistance element assembly illustrated in fig. 7.

Referring to fig. 7 and 8, a chip resistor element assembly 1000 according to the present embodiment includes the chip resistor element 100 shown in fig. 1 and the circuit board 10 on which the chip resistor element 100 is mounted.

The resistor substrate 10 includes first to third electrode pads 11, 12, 13 in a component mounting area. The first to third electrode pads 11, 12, and 13 represent pad patterns (land patterns) that are connected to a circuit pattern embodied on the circuit board 10 and are provided for mounting components.

The chip resistance element 100 illustrated in fig. 7 may be understood as a chip resistance element similar to the chip resistance element 100 illustrated in fig. 1 to 3. Unless otherwise specified, the components of the present embodiment may be understood with reference to the description of the same or similar components as those of the chip resistance element 100 shown in fig. 1 to 3.

As shown in fig. 7, the chip resistance element 100 may include: an insulating substrate 110; a resistive layer 120 disposed on one side of the insulating substrate; a first terminal 131 and a second terminal 132 which are arranged on the resistive layer in a spaced-apart manner; and a third terminal 133 disposed between the first and second terminals in a spaced apart relationship from the first and second terminals.

The circuit board 10 is a portion in which an electronic circuit is formed, and an Integrated Circuit (IC) or the like for specific operation or control of an electronic device is formed, so that a current supplied from an independent power source can flow.

In this case, the circuit substrate 10 may include various wirings, or may further include other kinds of semiconductor elements such as transistors. The circuit board 10 may be variously configured to include a conductive layer, a dielectric layer, or the like as required.

The first to third electrode pads 11, 12, and 13 are electrode pads arranged on the circuit board 10 at a distance from each other, and may be connected to the first to third terminals 131, 132, and 133 of the resistance element by solder 14, respectively. In the present embodiment, the distance between the first to third terminals 131, 132, 133 is set to be larger at the center than at the edge, so that even if an excess solder is generated at one terminal during mounting, the problem of short circuit due to the excess solder being discharged to an adjacent terminal can be solved.

The first to third electrode pads 11, 12, 13 are formed on the same horizontal plane, so that the surfaces to be soldered substantially share the same plane, and thus mounting can be stably performed.

The first to third terminals 131, 132, 133 are electrically connected to the electronic circuit through the first to third electrode pads 12, 13, 14, and thus, the first resistance portion and the second resistance portion formed between the first to third terminals 131, 132, 133 may be connected to the circuit.

While the embodiments of the present invention have been described in detail, it will be understood by those having ordinary skill in the art that the scope of the claims of the present invention is not limited thereto, and various modifications and variations can be made without departing from the technical matters of the present invention described in the claims.

Claims (10)

1. A chip resistance element, comprising:

an insulating substrate having a first surface and a second surface located on opposite sides of each other;

a resistive layer disposed on the first face;

a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; and

a third terminal arranged on the insulating substrate between the first terminal and the second terminal and connected to the resistive layer,

wherein a first interval between the first terminal and the third terminal gradually increases from an edge position of the first face toward a center of the first face,

a second interval between the second terminal and the third terminal gradually increases from an edge position of the first face toward a center of the first face,

the first and second intervals at the center of the first surface are 0.01 to 0.10mm larger than the first and second intervals at the edge position of the first surface, respectively.

2. A patch resistive element according to claim 1,

the first terminal includes: a first internal electrode disposed on the resistive layer; and a first external electrode covering the first internal electrode,

the second terminal includes: a second internal electrode disposed on the resistive layer; and a second external electrode covering the second internal electrode,

the third terminal includes: a third internal electrode disposed on the resistive layer; and a third external electrode covering the third internal electrode.

3. A patch resistive element according to claim 2, further comprising:

and resistive protection layers disposed on the resistive layer between the first and third terminals and between the second and third terminals, respectively.

4. A patch resistive element according to claim 3,

the resistive protection layer has a region overlapping with regions of the first to third internal electrodes arranged at the center of the first face.

5. A patch resistive element according to claim 3,

the resistive protective layer has a raised area.

6. A patch resistive element according to claim 5,

at least one of the first to third external electrodes has a recessed region corresponding to the protruding region.

7. A patch resistive element according to claim 2,

the resistive layer includes a first resistive layer and a second resistive layer separated from each other, and the third internal electrode is disposed between the first resistive layer and the second resistive layer.

8. A patch resistive element according to claim 2,

the first and second terminals respectively include:

a first rear surface electrode and a second rear surface electrode arranged on a second surface of the insulating substrate facing the first surface;

the first side electrode is connected with the first inner electrode and the first inner electrode, and the second side electrode is connected with the second inner electrode and the second inner electrode.

9. A chip resistance element, comprising:

an insulating substrate having a first surface and a second surface located on opposite sides of each other;

a resistive layer disposed on the first face;

a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer;

a third terminal arranged on the insulating substrate between the first terminal and the second terminal and connected to the resistive layer; and

resistive protection layers disposed on the resistive layer between the first and third terminals and between the second and third terminals, respectively,

a length of the resistive protection layer gradually increases from an edge position of the first face toward a center of the first face,

the length of the resistive protective layer at the center is 0.01mm to 0.10mm longer than the length at the edge position.

10. A chip resistor element assembly, comprising:

a printed circuit board having a plurality of electrode pads; and

a chip resistance element disposed on the printed circuit substrate and electrically connected to the plurality of electrode pads,

the chip resistance element includes: an insulating substrate having a first surface and a second surface that face each other; a resistive layer disposed on the first face; a first terminal and a second terminal arranged on the insulating substrate at both ends of the first surface and connected to the resistive layer; and a third terminal arranged on the insulating substrate between the first terminal and the second terminal and connected to the resistive layer,

a first interval between the first terminal and the third terminal gradually increases from an edge position of the first face toward a center of the first face,

a second interval between the second terminal and the third terminal gradually increases from an edge position of the first face toward a center of the first face,

the first and second intervals at the center of the first surface are 0.01 to 0.10mm larger than the first and second intervals at the edge position of the first surface, respectively.

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