CN110654111A - Liquid ejecting head and liquid ejecting recording apparatus - Google Patents

Abstract

To provide a liquid jet head and a liquid jet recording apparatus capable of reducing the number of signal lines. [ MEANS FOR solving PROBLEMS ] A liquid ejecting head according to an embodiment of the present disclosure includes: an ejection section having a plurality of nozzles that eject liquid; and one or more drive circuit units for generating a drive signal for ejecting the liquid from the nozzles based on a serial data signal, a clock signal, a latch signal, an emission signal, and a strobe signal supplied from an external head control unit, and outputting the drive signal to the ejection unit. The drive circuit unit includes: a serial/parallel conversion unit that performs serial/parallel conversion on the basis of a serial data signal and a clock signal, the serial data signal including m-bit (m: an integer of 2 or more) serial pixel data signals individually specified for each of the plurality of nozzles; a drive signal generation unit; and a parallel/serial conversion section that performs parallel/serial conversion based on the m-bit parallel pixel data signal and the clock signal.

Description

Liquid ejecting head and liquid ejecting recording apparatus

Technical Field

The present disclosure relates to a liquid ejection head and a liquid ejection recording apparatus.

Background

Liquid jet recording apparatuses including a liquid jet head are used in various fields, and various types of liquid jet heads have been developed as the liquid jet head. In addition, for example, patent document 1 proposes a method of data transfer in a liquid ejecting head.

[ Prior Art document ]

[ patent document ]

[ patent document 1] Japanese patent laid-open No. 2013-226765.

Disclosure of Invention

[ problem to be solved by the invention ]

In such a liquid ejecting head, it is generally required to reduce the number of signal lines when data is transmitted. It is desirable to provide a liquid jet head and a liquid jet recording apparatus capable of reducing the number of signal lines.

[ MEANS FOR solving PROBLEMS ] A method for solving the problems

A liquid ejecting head according to an embodiment of the present disclosure includes: an ejection section having a plurality of nozzles that eject liquid; and one or more driving circuit sections for generating a driving signal for ejecting the liquid from the nozzles based on a serial data signal, a clock signal, a latch signal, a fire (firing) signal, and a strobe signal supplied from an external head control section, and outputting the driving signal to the ejection section. The drive circuit unit includes: a serial/parallel conversion unit that performs serial/parallel conversion on the basis of a serial data signal including m-bit (m: an integer of 2 or more) serial pixel data signals individually specified for each of the plurality of nozzles and a clock signal to generate m-bit parallel pixel data signals; a drive signal generation section that generates a drive signal for each of the plurality of nozzles based on the m-bit parallel pixel data signal, the latch signal, the emission signal, the gate signal, and the clock signal; and a parallel/serial conversion section that performs parallel/serial conversion based on the m-bit parallel pixel data signal and the clock signal to generate a serial data signal, and outputs the serial data signal and the clock signal to the outside of the drive circuit section, respectively.

A liquid ejecting recording apparatus according to an embodiment of the present disclosure includes: the liquid ejecting head according to the embodiment of the present disclosure; and a head control unit that supplies a serial data signal, a clock signal, a latch signal, an emission signal, and a strobe signal to the liquid ejecting head, respectively.

[ Effect of the invention ]

According to the liquid ejecting head and the liquid ejecting recording apparatus according to the embodiment of the present disclosure, the number of signal lines can be reduced.

Drawings

Fig. 1 is a block diagram showing a schematic configuration example of a liquid ejecting apparatus according to an embodiment of the present disclosure.

Fig. 2 is a block diagram showing a configuration example of each drive circuit section in the liquid ejecting head shown in fig. 1.

Fig. 3 is a block diagram showing a configuration example of each drive circuit section in the liquid jet head according to the comparative example.

Fig. 4 is a timing chart schematically showing an example of operation of the liquid jet head according to the comparative example.

Fig. 5 is a timing chart schematically showing an example of operation in each of the driving circuit units shown in fig. 2.

Fig. 6 is a timing chart schematically showing a part of the operation example shown in fig. 5 in an enlarged manner.

Fig. 7 is a timing chart schematically showing an example of the operation of the entire liquid ejecting head shown in fig. 1.

Fig. 8 is a block diagram showing a configuration example of each drive circuit section in the liquid jet head according to modification 1.

Fig. 9 is a timing chart schematically showing an example of the operation of the demultiplexer shown in fig. 8.

Fig. 10 is a block diagram showing a configuration example of each drive circuit section in the liquid jet head according to modification example 2.

Fig. 11 is a block diagram showing an example of the configuration of each drive circuit unit in the liquid jet head according to modification 3.

Fig. 12 is a schematic diagram showing an example of a configuration of grouping a plurality of nozzles according to modification 3.

Fig. 13 is a timing chart schematically showing an example of operation in each of the driving circuit units shown in fig. 11.

Fig. 14 is a block diagram showing an example of the configuration of each drive circuit unit in the liquid jet head according to modification 4.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description is made in the following order.

1. Embodiment (example of data Transmission Using Single Serial data Signal)

2. Modification example

Modification 1 (example of the case where the latch signal and the transmission signal are a single composite signal)

Modification 2 (example in the case where a serial pixel data signal and another signal are not multiplexed)

Modification 3 (example in the case of data transmission using a plurality of serial data signals)

Modification 4 (modification 3, similarly to modification 2, in the case where multiplexing is not performed)

3. Other modifications

< 1. embodiment >

[ Structure of Printer 3]

Fig. 1 is a block diagram showing a schematic configuration example of a printer 3 as a liquid ejecting recording apparatus according to an embodiment of the present disclosure. Fig. 2 is a block diagram showing an example of the configuration of each of the drive circuit units ( drive circuit units 12a, 12b, and 12c described later) in the ink jet head 1 as the liquid jet head shown in fig. 1. In fig. 1 and 2, "/N" (N: an integer of 2 or more) indicated on the signal wiring indicates the number of wirings, and the same applies to the following block diagrams (fig. 3, 8, 10, 11, and 14 described later). In the drawings used in the description of the present specification, the scale of each member is appropriately changed so that each member has a size that can be recognized.

The printer 3 is an ink jet printer that performs recording (printing) of images, characters, and the like on a recording medium (for example, recording paper) with ink 9 described later. As shown in fig. 1, the printer 3 includes an inkjet head 1 and a head control unit 2.

Further, the ink-jet head 1 corresponds to a specific example of "liquid-jet head" in the present disclosure, and the printer 3 corresponds to a specific example of "liquid-jet recording apparatus" in the present disclosure. The ink 9 corresponds to a specific example of "liquid" in the present disclosure.

(A. head control part 2)

The head control section 2 supplies various information (data) to the inkjet head 1. Specifically, as shown in fig. 1, the head control unit 2 supplies 1 (single) serial data signal Ds and one clock signal CLK to a drive circuit unit 12a (the most preceding drive circuit unit) described later in the inkjet head 1.

Here, the serial data signal Ds and the clock signal CLK are respectively transmitted by, for example, LVDS (Low Voltage Differential Signaling). This enables high-speed transmission of small-amplitude signals, and improves the capability of removing in-phase noise by using a differential signal. In addition, as shown in fig. 1, the serial data signal Ds and the clock signal CLK are transmitted through 1 signal line, respectively. Further, the serial data signal Ds includes 7-bit serial data in 1 clock period (a period of one cycle T to be described later) in synchronization with the clock signal CLK. However, the serial data is not limited to 7 bits, and may be multi-bit serial data other than 7 bits.

In the present embodiment, although details will be described later (see fig. 5) in the serial data signal Ds, other signals are multiplexed together with the serial pixel data signal PDs having m bits (an integer of m: 2 or more, 4 bits in this example). Specifically, in this example, the serial data signal Ds includes a 4-bit serial pixel data signal PDs, and further includes a LATCH signal LATCH, an emission signal (ejection start signal) FIRE, and a strobe signal stb (strobe), which will be described later, respectively. In the present embodiment, such a single serial data signal Ds includes serial pixel data signals PDs individually defined in correspondence with all of a plurality of nozzles described later in the inkjet head 1.

Note that such a serial data signal Ds corresponds to a specific example of "a single serial data signal" in the present disclosure.

(B. ink-jet head 1)

As shown by broken line arrows in fig. 1 and 2, the inkjet head 1 is a head that ejects (discharges) droplet-shaped ink 9 from a plurality of nozzles described later onto a recording medium to perform recording of images, characters, and the like. As shown in fig. 1, the inkjet head 1 includes an ejection unit 11 and a plurality of drive circuit units (in this example, 3 drive circuit units 12a, 12b, and 12 c). In the ink jet head 1, ink 9 is supplied from an ink tank, not shown, through a supply tube or the like.

(B-1. injection part 11)

As shown in fig. 1, the ejection part 11 includes a plurality of (3 in this example) ejection parts 11a, 11b, and 11 c. The ejection units 11a, 11b, and 11c are arranged so as to individually correspond to the drive circuit units 12a, 12b, and 12 c. Each of the ejection units 11a, 11b, and 11c has the plurality of nozzles, and the ink 9 is ejected from the nozzles in response to the drive signal Sd (drive voltage Vd) supplied from the drive circuit units 12a, 12b, and 12c, respectively.

As shown in fig. 2, for example, each of the ejection units 11a, 11b, and 11c includes a piezoelectric actuator (actuator plate) 111 and a nozzle plate 112.

The nozzle plate 112 is a plate made of a film material such as polyimide or a metal material, and has the above-described plurality of nozzles (5 nozzle holes Hn1 to Hn5 in this example, hereinafter collectively referred to as nozzle holes Hn as appropriate) as shown in fig. 2. These nozzle holes Hn1 to Hn5 are formed in a straight line (1 column) at predetermined intervals, for example, in a circular shape.

These nozzle holes Hn1 to Hn5 (a plurality of nozzle holes Hn) correspond to a specific example of "nozzle" in the present disclosure.

The piezoelectric actuator 111 is a plate made of a piezoelectric material such as PZT (lead zirconate titanate). The piezoelectric actuator 111 is provided with a plurality of passages (pressure chambers), not shown. These channels are portions for applying pressure to the ink 9, and are arranged in parallel with each other at predetermined intervals. Each channel is divided by a driving wall (not shown) made of a piezoelectric body, and is formed as a groove portion having a concave shape in a sectional view.

Among such channels are a discharge channel for discharging the ink 9 and a dummy channel (non-discharge channel) for not discharging the ink 9. In other words, the ejection channels are filled with the ink 9, and the dummy channels are not filled with the ink 9. The ink 9 is supplied to the discharge passage through the supply tube and the predetermined flow path. Further, each discharge channel communicates with the nozzle hole Hn in the nozzle plate 112, and each dummy channel does not communicate with the nozzle hole Hn. These discharge channels and dummy channels are alternately arranged.

Drive electrodes (not shown) are provided on the inner surfaces of the drive walls facing each other. The drive electrodes include a common electrode (common electrode) provided on an inner surface facing the discharge channel and an active electrode (individual electrode) provided on an inner surface facing the dummy channel. These drive electrodes are electrically connected to drive circuit units 12a, 12b, and 12c (described later) via a plurality of lead electrodes (not shown) formed on a flexible substrate (not shown). Thus, the driving voltage Vd (driving signal Sd) is applied from the driving circuit units 12a, 12b, and 12c to the driving electrodes via the flexible substrate (see fig. 1 and 2).

(B-2. drive circuit units 12a, 12B, 12 c)

As shown in fig. 1, each of the drive circuit sections 12a, 12b, and 12c is a circuit for supplying a drive signal Sd (drive voltage Vd) for ejecting the ink 9 from each nozzle hole Hn to the corresponding ejection section 11a, 11b, or 11 c. Specifically, the drive circuit units 12a, 12b, and 12c each generate a drive signal Sd based on the serial data signal Ds and the clock signal CLK supplied from the head control unit 2, and output the drive signal Sd to the corresponding ejection units 11a, 11b, and 11c, respectively.

As shown in fig. 1, the plurality of drive circuit units 12a, 12b, and 12c are connected in series with each other in multiple stages (cascade connection) in the inkjet head 1 (on a drive circuit board (not shown)). In other words, the number of stages of cascade connection of the drive circuit units 12a, 12b, and 12c in the inkjet head 1 is 3. Specifically, as shown in fig. 1, the head control unit 2, the driver circuit unit 12a (the first stage), the driver circuit unit 12b, and the driver circuit unit 12c (the last stage) are connected in cascade from the front stage side to the rear stage side in this order, which will be described in detail later, but data transfer is performed in this order.

As shown in fig. 2, the drive circuit units 12a, 12b, and 12c each include a serial/parallel converter 121, a drive signal generator 122, and a parallel/serial converter 123.

(Serial/parallel conversion section 121)

The serial/parallel converter 121 is a circuit that performs predetermined serial/parallel conversion based on a serial data signal Ds including the serial pixel data signal PDs of m bits (4 bits in this example) and a clock signal CLK. By such serial/parallel conversion, as shown in fig. 2, a parallel pixel data signal PDp (PDp [ 3: 0 ]) of m bits (4 bits in this example) is generated.

Specifically, as shown in fig. 2, the serial/parallel conversion section 121 performs such serial/parallel conversion to generate a parallel pixel data signal PDp of 4 bits, and also generates the LATCH signal LATCH, the emission signal FIRE, and the strobe signal STB, respectively. The serial/parallel converter 121 also outputs a clock signal CLK (see fig. 2).

(drive signal generating section 122)

The drive signal generation unit 122 generates the drive signal Sd (drive voltage Vd) for each of the plurality of nozzle holes Hn. Specifically, as shown in fig. 2, the drive signal generation section 122 generates such a drive signal Sd based on the m-bit (4-bit in this example) parallel pixel data signal PDp, the LATCH signal LATCH, the emission signal FIRE, the strobe signal STB, and the clock signal CLK.

As shown in fig. 2, the drive signal generation unit 122 includes a shift register unit 122A, a latch circuit unit 122B, a waveform generation circuit unit 122C, a level conversion circuit 122D, AND an AND logic circuit (AND circuit) 40.

As shown in fig. 2, the AND logic circuit 40 is a logic circuit that generates an AND signal (AND signal) Scom of the strobe signal STB AND the clock signal CLK.

The shift register section 122A is a circuit for sequentially transmitting and holding the parallel pixel data signal PDp for each of the plurality of nozzle holes Hn from the preceding stage side (nozzle hole Hn1 side) to the succeeding stage side (nozzle hole Hn5 side) in accordance with the drive signal Sd for each of the plurality of nozzle holes Hn (see fig. 2). The shift register section 122A includes D-FF (flip-flop) circuits 41 as many as (5 in this example) the number of the plurality of nozzle holes Hn, and each D-FF circuit 41 can hold a parallel pixel data signal PDp of 4 bits. As shown in fig. 2, the and signal Scom generated by the and circuit 40 is input to each D-FF circuit 41 as a shift clock when the signals are sequentially transmitted. In other words, the shift register portion 122A sequentially transfers the parallel pixel data signals PDp in synchronization with the logical sum signal Scom.

As shown in fig. 2, the LATCH circuit section 122B is a circuit that holds the 4-bit parallel pixel data signal PDp for each of the plurality of nozzle holes Hn, which is output from each D-FF circuit 41 in the shift register section 122A, in synchronization with the LATCH signal LATCH. The latch circuit portion 122B has the same number (5 in this example) of latch circuits 42 as the number of the plurality of nozzle holes Hn, so that the 4-bit parallel pixel data signals PDp can be held in each latch circuit 42.

As shown in fig. 2, the waveform generation circuit section 122C is a circuit that generates a waveform signal that is a basis of the drive signal Sd based on the 4-bit parallel pixel data signal PDp for each of the plurality of nozzle holes Hn output from each latch circuit 42 in the latch circuit section 122B. The waveform generation circuit portion 122C includes the same number (5 in this example) of waveform generation circuits 43 as the number of the plurality of nozzle holes Hn, and generates such a waveform signal in each waveform generation circuit 43 in synchronization with the emission signal FIRE.

As shown in fig. 2, the level shifter circuit 122D is a circuit that generates a drive signal Sd for each of the plurality of nozzle holes Hn based on a waveform signal for each of the plurality of nozzle holes Hn that is output from each waveform generator circuit 43 in the waveform generator circuit portion 122C. Specifically, the level shifter circuit 122D generates the driving signals Sd having the driving voltages Vd corresponding to the nozzle holes Hn, respectively, by shifting the levels (voltage values) of the waveform signals.

(parallel/serial conversion section 123)

The parallel-serial conversion section 123 is a circuit that performs predetermined parallel-serial conversion based on the m-bit (4-bit in this example) parallel pixel data signal PDp and the clock signal CLK. By such parallel/serial conversion, as shown in fig. 2, the serial data signal Ds described above is generated (regenerated) so that the serial data signal Ds and the clock signal CLK are output to the outside of the driver circuit sections 12a, 12b, and 12c, respectively.

Specifically, the parallel-serial conversion section 123 performs the above-described parallel-serial conversion based on the 4-bit parallel pixel data signal PDp, the clock signal CLK, the strobe signal STB, the LATCH signal LATCH, and the emission signal FIRE, which are output from the shift register section 122A (the last stage D-FF circuit 41) (see fig. 2).

Here, as shown in fig. 1 and 2, the serial data signal Ds and the clock signal CLK output from the parallel-to-serial conversion unit 123 of the drive circuit unit located on the front stage side are input to the serial-to-parallel conversion unit 121 of the drive circuit unit located on the rear stage side. Specifically, the serial data signal Ds and the clock signal CLK output from the driver circuit portion 12a on the relatively preceding stage are input to the driver circuit portion 12b on the relatively succeeding stage, respectively. Similarly, the serial data signal Ds and the clock signal CLK output from the driver circuit portion 12b on the relatively previous stage are input to the driver circuit portion 12c on the relatively subsequent stage. Thereby, as shown in fig. 1, the plurality of drive circuit portions 12a, 12b, 12c are connected in series with each other in multiple stages (cascade connection).

[ actions and actions/Effect ]

Basic operation of Printer 3

In the printer 3, the ink 9 is ejected by the ink jet head 1 as described below, and a recording operation (printing operation) of an image, a character, or the like on a recording medium is performed. Specifically, the inkjet head 1 according to the present embodiment performs the ejection operation of the ink 9 in the cut (share) mode by the following processing. In the printer 3, as an initial state, the ink 9 in the ink tank is filled in the discharge channel of the piezoelectric actuator 111 of the ink jet head 1 via the supply tube, the predetermined flow path, and the like.

First, each of the drive circuit units 12a, 12b, and 12c applies a drive voltage Vd (drive signal Sd) to the drive electrodes (common electrode and active electrode) in the piezoelectric actuators 111 in the corresponding ejection units 11a, 11b, and 11 c. Specifically, the drive circuit units 12a, 12b, and 12c apply the drive voltage Vd to the drive electrodes arranged on the pair of drive walls that divide the discharge channel. Thus, the pair of driving walls are deformed so as to protrude toward the dummy channel side adjacent to the discharge channel.

At this time, the driving wall is bent and deformed in a V shape around the middle position in the depth direction of the driving wall. By such bending deformation of the driving wall, the discharge path deforms as if it were inflated. In this way, the volume of the discharge channel is increased by the bending deformation due to the piezoelectric thickness slip effect on the pair of driving walls. Further, the volume of the discharge channel increases, and the ink 9 is induced into the discharge channel.

The ink 9 thus induced into the discharge channel becomes a pressure wave and is transmitted to the inside of the discharge channel. Then, at the timing when the pressure wave reaches the nozzle hole Hn of the nozzle plate 112, the driving voltage Vd applied to the driving electrode becomes 0 (zero) V. As a result, the volume of the discharge passage, which has temporarily increased as a result of the restoration of the driving wall from the state of the flexural deformation, returns to its original state again.

In this way, in the process of returning the volume of the discharge channel as it is, the pressure inside the discharge channel increases, and the ink 9 inside the discharge channel is pressurized. As a result, the droplet-like ink 9 is discharged to the outside (to the recording medium) through the nozzle hole Hn (see fig. 1 and 2). In this way, the ejection operation (discharge operation) of the ink 9 in the ink jet head 1 is completed, and as a result, the recording operation of an image, a character, or the like on the recording medium can be performed.

(B. data transfer action)

Next, referring to fig. 3 to 7 in addition to fig. 1 and 2, the data transfer operation between the head control unit 2 and the drive circuit unit 12a and between the drive circuit units 12a, 12b, and 12c will be described in detail, while comparing with the comparative example (fig. 3 and 4).

(B-1. comparative example)

Fig. 3 is a block diagram showing an example of the configuration of each of the drive circuit sections 102a, 102b, and 102c in the liquid jet head (ink jet head 101) according to the comparative example. Fig. 4 schematically shows an operation example (data transfer operation example) of the inkjet head 101 according to the comparative example in a timing chart.

In the inkjet head 101 of this comparative example, as in the inkjet head 1 of the present embodiment shown in fig. 1, the plurality of drive circuit units 102a, 102b, and 102c are connected in series with one another in multiple stages (cascade connection).

Here, in fig. 4, (a) shows the clock signal CLK; (C) LATCH signal LATCH is shown; (D) the transmit signal FIRE is shown; (E) a strobe signal STB is shown. In fig. 4, (B), (F), and (G) show parallel pixel data signals PDp [ 3: 0] of 4 bits which are input to the driving circuit sections 102a, 102B, and 102c, respectively. The horizontal axis in fig. 4 represents time t, and the same applies to the following timing chart.

In fig. 4 (B), 4 (F), and 4 (G), "n", "a", and "B" in "Dn _ a _ B" indicated in the parallel pixel data signal PDp [ 3: 0] are the following numbers, respectively. Further, "N/a" means a missing value (Not Available). These meanings are basically the same in the later timing charts.

"n": bit numbering in parallel pixel data signals PDp

"a": numbering of nozzle bores Hn

"b": the number of the plurality of driving circuit units (3 driving circuit units 12a, 12b, 12c in this example) connected in cascade.

The drive circuit units 102a, 102b, and 102c in the inkjet head 101 correspond to the following modifications of the drive circuit units 12a, 12b, and 12c (see fig. 2) in the inkjet head 1. That is, as shown in fig. 3, the respective drive circuit units 102a, 102b, and 102c correspond to the configuration in which the serial-to-parallel converter 121 and the parallel-to-serial converter 123 are not provided (omitted) in the respective drive circuit units 12a, 12b, and 12c, and the other configurations are basically the same.

Since the serial/parallel converter 121 and the parallel/serial converter 123 are not provided, the 4-bit parallel pixel data signal PDp (see fig. 3) is input to and output from each of the driving circuit units 102a, 102b, and 102 c. In each of the driving circuit portions 102a, 102b, and 102c, the clock signal CLK, the strobe signal STB, the LATCH signal LATCH, and the emission signal FIRE are also input and output in parallel with the parallel pixel data signal PDp, respectively (see fig. 3).

In the data transfer operation of the comparative example shown in fig. 4, a shift clock (and signal Scom) is input to each D-FF circuit 41 only during a period (a period from timing t101 to timing t 104) in which the strobe signal STB is "1". Therefore, this period becomes an effective period for data input to the shift register section 122A (input of the parallel pixel data signal PDp) (see fig. 4B, 4F, and 4G).

In this period, first, the parallel pixel data signals PDp corresponding to the nozzle holes Hn1 to Hn5 corresponding to the 3 driver circuit sections 102A, 102B, and 102c are sequentially input to the shift register section 122A in the driver circuit section 102A at the first stage (see fig. 4B). Next, in the shift register section 122A, the parallel pixel data signals PDp sequentially transferred and held are held in the LATCH circuits 42 in the LATCH circuit section 122B at a timing (timing t 105) at which the LATCH signal LATCH changes from "0" to "1" (see fig. 4C). Next, at the timing when the emission signal FIRE changes from "0" to "1" (timing t 106), each waveform generation circuit 43 in the waveform generation circuit portion 125C starts generating a waveform signal that is the basis of the drive signal Sd based on the parallel pixel data signal PDp held in each latch circuit 42 (see fig. 4D). Then, the level shift circuit 122D generates a drive signal Sd corresponding to each nozzle hole Hn based on each waveform signal, and drives the drive wall based on the drive signal Sd (as a result, for example, ink 9 is discharged from each nozzle hole Hn) (see fig. 3).

At this time, the 4-bit parallel pixel data signal PDp output from the D-FF circuit 41 at the final stage of the shift register unit 122A in the driver circuit unit 102A is output to the driver circuit unit 102b at the subsequent stage of the driver circuit unit 102A (see fig. 3). Similarly, the 4-bit parallel pixel data signal PDp output from the D-FF circuit 41 at the final stage of the shift register unit 122A in the driver circuit unit 102b is output to the driver circuit unit 102c at the subsequent stage (final stage) of the driver circuit unit 102b (see fig. 3). At this time, the parallel pixel data signals PDp corresponding to the respective driver circuit units 102a, 102B, and 102c are sequentially transferred from the driver circuit unit 102a to the driver circuit units 102B and 102c while being sequentially shifted (see fig. 4B, 4F, and 4G).

In this way, in the ink jet head 101 of the comparative example, the input signal and the output signal in the drive circuit units 102a, 102b, and 102c are respectively configured by parallel data signals including the parallel pixel data signal PDp, and the like. Therefore, in this comparative example, the number of signals (the number of signal lines) between the head control unit 2 and the drive circuit unit 102a or between the drive circuit units 102a, 102b, and 102c is increased (the number of signal lines is increased). As a result of increasing the number of signal lines in this way, the comparative example may increase the size of the inkjet head 101, increase the time lag between signals, and reduce the degree of freedom in designing the inkjet head 101.

(B-2. this embodiment mode)

In contrast, as shown in fig. 2, the drive circuit units 12a, 12b, and 12c of the present embodiment are provided with a serial-to-parallel converter 121 and a parallel-to-serial converter 123, respectively. The data transfer operation is performed in the following manner in each of the drive circuit units 12a, 12b, and 12c and the entire inkjet head 1.

Fig. 5 schematically shows an operation example (data transfer operation example) in each of the drive circuit units 12a, 12b, and 12c shown in fig. 2 in a timing chart, and fig. 6 schematically shows a part of the operation example shown in fig. 5 in an enlarged scale in the timing chart. Fig. 7 schematically shows a timing chart of the data transfer operation over the entire inkjet head 1 shown in fig. 1. Note that, in fig. 5 to 7, 1 cycle of the clock signal CLK is shown as a period T, and the same applies to the following timing charts.

Here, in fig. 5 and 6, (a), (B), and (C) show the clock signal CLK, the serial data signal Ds, and 7-bit parallel data (including the parallel pixel data signal PDp [ 3: 0] of 4 bits) obtained by serial/parallel conversion of the serial data signal Ds, which are input to (the serial/parallel conversion unit 121 in) the drive circuit units 12a, 12B, and 12C, respectively.

On the other hand, in fig. 5, (D), (E), and (F) show the clock signal CLK, the serial data signal Ds, and the 7-bit parallel data before the parallel/serial conversion (including the parallel pixel data signal PDp [ 3: 0] of 4 bits) output from (the parallel/serial conversion section 123 in) the drive circuit sections 12a, 12b, and 12c, respectively.

In fig. 7, (a) shows the clock signal CLK, and (B) to (E), (F) to (I), and (J) to (M) respectively show 7-bit parallel data (including 4-bit parallel pixel data signals PDp [ 3: 0 ]) in the drive circuit units 12a, 12B, and 12 c. Specifically, (B), (F), (J) show parallel pixel data signals PDp [ 3: 0] of 4 bits, respectively, and (C), (G), (K) show LATCH signals LATCH, respectively. In addition, (D), (H), (L) show the transmission signal FIRE, respectively, (E), (I), (M) show the strobe signal STB, respectively.

Further, in this FIG. 7, for convenience, the contents of each bit in the 4-bit parallel pixel data signal PDp [ 3: 0] are summarized and the notation is simplified, shown as "Dab" rather than "Dn _ a _ b" as previously defined.

The data transfer operation according to the present embodiment is as follows in the drive circuit units 12a, 12b, and 12c, as shown in fig. 5 and 6, for example. That is, first, the serial data signal Ds is synchronized with the clock signal CLK, and 7-bit serial data is included in the period (1 clock period) of the cycle T (see fig. 5a, 5B, 6a, and 6B). The serial data signal Ds is serial/parallel converted in the serial/parallel conversion section 121, thereby generating a parallel pixel data signal PDp [ 3: 0], a LATCH signal LATCH, an emission signal FIRE, and a strobe signal STB of 4 bits, respectively (see a dotted arrow in fig. 6). In this example, as shown in fig. 6, the first 4 bits of the serial data signal Ds become the serial pixel data signal PDs, and then the LATCH signal LATCH, the emission signal FIRE, and the strobe signal STB are arranged in this order.

Here, only during a period (a period from the timing t11 to the timing t 16) in which the strobe signal STB thus generated is "1", a shift clock (and signal Scom) is input to each D-FF circuit 41 in the shift register section 122A. Therefore, this period becomes an effective period for data input to the shift register section 122A (input of the parallel pixel data signal PDp) (see fig. 5C and 6C).

In this period, first, the parallel pixel data signals PDp corresponding to the nozzle holes Hn1 to Hn5 are sequentially input to the shift register section 122A. Next, in the shift register section 122A, the parallel pixel data signals PDp sequentially transferred and held are held in the LATCH circuits 42 in the LATCH circuit section 122B at a timing (timing t 17) at which the LATCH signal LATCH changes from "0" to "1" (see fig. 5C). Next, at the timing when the emission signal FIRE changes from "0" to "1" (timing t 19), the waveform generation circuits 43 in the waveform generation circuit section 122C start generating a waveform signal that serves as a basis of the drive signal Sd based on the parallel pixel data signal PDp held in the latch circuits 42 (see fig. 5C). Then, the level conversion circuit 122D generates a drive signal Sd corresponding to each nozzle hole Hn based on each waveform signal, and drives the drive wall (as a result, for example, ink 9 is discharged from each nozzle hole Hn) based on the drive signal Sd (see timings t19 to t20 in fig. 1, 2, and 5).

At this time, the parallel/serial conversion section 123 performs parallel/serial conversion on the 4-bit parallel pixel data signal PDp [ 3: 0] output from the D-FF circuit 41 at the final stage of the shift register section 122A. Specifically, the serial data signal Ds is regenerated by performing parallel-to-serial conversion based on the 4-bit parallel pixel data signal PDp [ 3: 0], the LATCH signal LATCH, the transmission signal FIRE, and the strobe signal STB (see fig. 5D to 5F). The serial data signal Ds thus regenerated is output from the parallel-to-serial converter 123 to the outside of the driver circuit units 12a, 12b, and 12c together with the clock signal CLK (see fig. 5D and 5E). Note that, since the strobe signal STB is set to "0" at timings t16 to 23 IN "PDp [ 3: 0 ]" (IN) IN fig. 5 (C), the above-described sequential transmission is not performed. Thus, as shown at timings t18 to t23 on "PDp [ 3: 0 ]" (OUT) in FIG. 5 (F), the parallel pixel data signal PDp [ 3: 0] is kept "Dn-5 _ 1" at all times.

In this case, as indicated by broken-line arrows P10 and P11 in fig. 5, for example, the data in the drive circuit sections 12a, 12b, and 12c are sequentially shifted by a period of 7 cycles T (7 cycles). Specifically, the parallel pixel data signal PDp included in the serial data signal Ds input until the timing t11 is included in the serial data signal Ds and output during the period from the timing t13 to the timing t18 (see a dotted arrow P10). Similarly, the parallel pixel data signal PDp included in the serial data signal Ds input from the timing t11 to the timing t16 is included in the serial data signal Ds and output from the timing t18 to the timing t23 (see a dotted arrow P11).

As shown in fig. 7, for example, the data transfer operation of the entire inkjet head 1 is as follows. That is, first, the 4-bit parallel pixel data signal PDp in the driver circuit unit 12a becomes the serial data signal Ds as described above, and is output to the driver circuit unit 12b at the subsequent stage of the driver circuit unit 12a (see arrows P21 to P23 in fig. 7). Similarly, the 4-bit parallel pixel data signal PDp in the driver circuit unit 12b becomes the serial data signal Ds as described above, and is output to the driver circuit unit 12c of the subsequent stage (the last stage) of the driver circuit unit 12b (see arrows P31 to P33 in fig. 7). In fig. 7, the parallel pixel data signal PDp [ 3: 0] is kept unchanged at "D _5_ 1" or "D _5_ 2" without performing the above-described sequential transfer even while the strobe signal STB is set to "0".

At this time, the parallel pixel data signals PDp corresponding to the respective driver circuit units 12a, 12b, and 12c are sequentially transmitted from the driver circuit unit 12a to the driver circuit units 12b and 12c while being sequentially shifted (see arrows P21 to P23, P31 to P33 in fig. 7).

(B-3. action/Effect)

In this way, in the ink jet head 1 of the present embodiment, the parallel pixel data signals PDp for each of the plurality of nozzle holes Hn are generated in the respective drive circuit sections 12a, 12b, and 12c based on the serial data signal Ds (including the serial pixel data signal PDs for each of the plurality of nozzle holes Hn) and the clock signal CLK supplied from the outside (head control section 2). In each of the drive circuit units 12a, 12b, and 12c, a drive signal Sd for each of the plurality of nozzle holes Hn is generated based on the parallel pixel data signal PDp and the like. Then, the serial data signal Ds is generated again in each of the driver circuit units 12a, 12b, and 12c based on the parallel pixel data signal PDp and the like, and is output to the outside of each of the driver circuit units 12a, 12b, and 12c together with the clock signal CLK.

In this way, in the inkjet head 1, the input signal and the output signal in each of the drive circuit units 12a, 12b, and 12c are configured to include the serial data signal Ds and the clock signal CLK. Therefore, the ink jet head 1 is, for example, as follows, compared with the ink jet head 101 of the comparative example described above, in which the input signal and the output signal in each of the drive circuit sections 102a, 102b, and 102b are respectively configured by parallel data signals including the parallel pixel data signal PDp. That is, since serial data transmission is performed in the present embodiment, the number of signals (the number of signal lines) between the head control unit 2 and the drive circuit unit 12a or between the drive circuit units 12a, 12b, and 12c may be reduced (the number of signal lines may be reduced) compared to the comparative example (parallel data transmission).

As described above, the ink jet head 1 of the present embodiment can reduce the number of signal lines, and as a result, it is possible to reduce the size of the ink jet head 1, reduce the time lag between signals, and improve the degree of freedom in design of the ink jet head 1, as compared with the above comparative example. Specifically, by increasing the degree of freedom in design, for example, the number of nozzles (the number of nozzle holes Hn) can be expanded without changing hardware in the printer 3. In addition, for example, high-speed data transmission can be performed by using a low-speed clock signal CLK.

In the present embodiment, the serial data signal Ds and the clock signal CLK output from the parallel-to-serial converter 123 of the driver circuit section located on the front stage side are input to the serial-to-parallel converter 121 of the driver circuit section located on the rear stage side, and the plurality of driver circuit sections 12a, 12b, and 12c are connected in series with each other in multiple stages (cascade connection). In this way, the signal connection is performed between the driver circuit portions on the front stage side and the rear stage side as described above, and the following is performed. That is, it is possible to easily realize cascade connection of the plurality of driving circuit units 12a, 12b, and 12c, and it is also possible to easily increase the number of stages of cascade connection.

Further, in the present embodiment, the LATCH signal LATCH, the transmission signal FIRE, and the strobe signal STB are each further included in the serial data signal Ds (multiplexed), and therefore the following is made. That is, the input signal and the output signal of each of the driving circuit units 12a, 12b, and 12c are composed of only the serial data signal Ds and the clock signal CLK. Therefore, the number of signals (the number of signal lines) between the head control unit 2 and the drive circuit unit 12a or between the drive circuit units 12a, 12b, and 12c can be further reduced (the number of signal lines can be further reduced). Therefore, the inkjet head 1 can be further miniaturized, the time lag between signals can be further reduced, and the degree of freedom in design of the inkjet head 1 can be further improved.

Further, in the present embodiment, since a single serial data signal Ds is used, the number of serial data signals Ds (the number of signal lines) may be one. Therefore, the inkjet head 1 can be further miniaturized, the time lag between signals can be further reduced, and the degree of freedom in design of the inkjet head 1 can be further improved.

In the present embodiment, the shift register portion 122A sequentially transfers the parallel pixel data signals PDp in synchronization with the logic and signal Scom of the strobe signal STB and the clock signal CLK, and therefore, the following is performed. That is, the clock signal CLK does not need to be defined as an intermittent signal, and may be a continuous signal. Therefore, serial-to-parallel conversion is performed in the serial-to-parallel converter 121 based on the continuous clock signal CLK, and the parallel pixel data signal PDp can be generated. Further, for example, in the serial/parallel converter 121, by multiplying the continuous clock signal CLK, it is possible to handle a serial data signal Ds which is increased in speed and includes a plurality of bits (for example, 7 bits) in 1 clock period (period of the period T).

Further, the present embodiment can reduce the circuit scale around the serial/parallel converter 121 or the parallel/serial converter 123, compared to the case of the so-called "8B/10B system" data transmission method.

< 2. modification example >

Next, modifications (modifications 1 to 4) of the above embodiment will be described. The liquid ejecting heads according to these modifications 1 to 4 may be provided in a liquid ejecting recording apparatus (printer) as in the above-described embodiment. In the following, the same components as those in the above embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

[ modification 1]

Fig. 8 is a block diagram showing an example of the configuration of each of the drive circuit units 13a, 13b, and 13c in the liquid jet head (ink jet head 1A) according to modification 1. In the inkjet head 1A of modification 1, as in the inkjet head 1 of the embodiment shown in fig. 1, the plurality of drive circuit units 13a, 13b, and 13c are connected in series with one another in multiple stages (cascade connection). That is, the number of stages of cascade connection of the drive circuit units 13a, 13b, and 13c in the inkjet head 1A is 3.

The drive circuit units 13a, 13b, and 13c in the inkjet head 1A correspond to the following modifications of the drive circuit units 12a, 12b, and 12c (see fig. 2) in the inkjet head 1. That is, as shown in fig. 8, the respective drive circuit units 13A, 13b, and 13c have substantially the same configuration as the configuration in which the serial/parallel converter 121A and the parallel/serial converter 123A are provided in place of the serial/parallel converter 121 and the parallel/serial converter 123 in the respective drive circuit units 12a, 12b, and 12c, and the demultiplexer 124A is further provided.

The ink jet head 1A corresponds to a specific example of the "liquid jet head" in the present disclosure.

(Serial/parallel conversion section 121A)

The serial/parallel converter 121A is a circuit that performs predetermined serial/parallel conversion based on a serial data signal Ds including a serial pixel data signal PDs of m bits (4 bits in this example) and a clock signal CLK, as in the serial/parallel converter 121. By such serial/parallel conversion, as shown in fig. 8, a parallel pixel data signal PDp (PDp [ 3: 0 ]) of m bits (4 bits in this example) is generated.

However, the serial/parallel converter 121A is different from the serial/parallel converter 121 in that the following signals are generated by performing such serial/parallel conversion. That is, as shown in fig. 8, the serial/parallel conversion section 121A generates the above-described 4-bit parallel pixel data signal PDp, and also generates the strobe signal STB and the LATCH/FIRE signal LATCH/FIRE, respectively. The LATCH/FIRE signal LATCH/FIRE will be described in detail later (see fig. 9), but a single composite signal is defined by the LATCH signal LATCH and the FIRE signal FIRE individually. The serial/parallel converter 121A also outputs a clock signal CLK (see fig. 8).

Here, such LATCH/FIRE signal LATCH/FIRE corresponds to an example of "single composite signal" in the present disclosure.

(parallel/serial conversion section 123A)

The parallel-serial converter 123A is a circuit that performs predetermined parallel-serial conversion based on the m-bit (4-bit in this example) parallel pixel data signal PDp and the clock signal CLK, as in the parallel-serial converter 123. By such parallel/serial conversion, as shown in fig. 8, the serial data signal Ds is generated (regenerated), and the serial data signal Ds and the clock signal CLK are output to the outside of the driver circuit units 13a, 13b, and 13c, respectively.

However, the parallel-to-serial converter 123A is different from the parallel-to-serial converter 123, and specifically performs parallel-to-serial conversion as follows. That is, the parallel-serial conversion section 123A performs parallel-serial conversion based on the 4-bit parallel pixel data signal PDp output from the shift register section 122A, the clock signal CLK, the strobe signal STB, and the LATCH/FIRE signal LATCH/FIRE described above (see fig. 8).

The serial data signal Ds and the clock signal CLK output from the parallel-to-serial converter 123A of the drive circuit section located on the front stage side are input to the serial-to-parallel converter 121A of the drive circuit section located on the rear stage side (see fig. 8).

(branching filter 124A)

The demultiplexer 124A is a circuit that demultiplexes (separates) the LATCH/transmit signal LATCH/FIRE, which is the single composite signal described above, into a LATCH signal LATCH and a transmit signal FIRE. Similarly to the drive circuit units 12a, 12B, and 12C (see fig. 2), the LATCH signal LATCH and the transmission signal FIRE generated in this manner are output to the LATCH circuit unit 122B and the waveform generation circuit unit 122C (see fig. 8), respectively.

Here, fig. 9 schematically shows an operation example (an example of the above-described demultiplexing operation) in the demultiplexer 124A in a timing chart.

First, in the example shown in fig. 9 (a), the LATCH signal LATCH and the FIRE signal FIRE are individually defined as follows in the LATCH/FIRE signal LATCH/FIRE. That is, the LATCH signal LATCH and the transmission signal FIRE are individually defined by the rising timing of the LATCH/transmission signal LATCH/FIRE and the timing after the predetermined time Δ t has elapsed from the rising timing. The demultiplexer 124A thus demultiplexes the LATCH/transmit signal LATCH/FIRE into a LATCH signal LATCH and a transmit signal FIRE using such a difference in timing.

On the other hand, in the example shown in fig. 9 (B), the LATCH signal LATCH and the FIRE signal FIRE are individually defined as follows in the LATCH/FIRE signals LATCH/FIRE. That is, the LATCH signal LATCH and the transmission signal FIRE are individually defined by the rising timing and the falling timing of the LATCH/transmission signal LATCH/FIRE. The demultiplexer 124A thus demultiplexes the LATCH/transmit signal LATCH/FIRE into a LATCH signal LATCH and a transmit signal FIRE using such a difference in timing.

(action/Effect)

In modification 1 having such a configuration, the same effects can be obtained by basically the same operations as in the embodiment.

In particular, in modification 1, since 2 kinds of control signals (LATCH signal LATCH and FIRE signal FIRE) can be defined by being integrated into a single composite signal (LATCH/FIRE signal LATCH/FIRE), for example, the following effects can be obtained. That is, the number of control signals can be reduced, and the overhead (overhead) of the control signals can be reduced.

[ modification 2]

Fig. 10 is a block diagram showing an example of the configuration of each of the drive circuit sections 14a, 14B, and 14c in the liquid jet head (ink jet head 1B) according to modification 2. In the inkjet head 1B according to this modification 1, as in the inkjet head 1 according to the embodiment shown in fig. 1, the plurality of drive circuit units 14a, 14B, and 14c are connected in series with one another in multiple stages (cascade connection). That is, the number of stages of cascade connection of the drive circuit units 14a, 14B, and 14c in the inkjet head 1B is 3.

The drive circuit units 14a, 14B, and 14c in the inkjet head 1B correspond to the following modifications of the drive circuit units 12a, 12B, and 12c (see fig. 2) in the inkjet head 1. That is, as shown in fig. 10, each of the drive circuit units 14a, 14B, and 14c corresponds to the configuration in which the serial-to-parallel converter 121B and the parallel-to-serial converter 123B are provided in place of the serial-to-parallel converter 121 and the parallel-to-serial converter 123 in each of the drive circuit units 12a, 12B, and 12c, and the other configurations are basically the same.

The ink jet head 1B corresponds to a specific example of the "liquid jet head" in the present disclosure.

(Serial/parallel conversion section 121B)

The serial/parallel converter 121B is a circuit that performs predetermined serial/parallel conversion based on various signals supplied from the external head control unit 2, as in the serial/parallel converter 121 (see fig. 2) of the embodiment. By such serial/parallel conversion, as shown in fig. 10, a parallel pixel data signal PDp (PDp [ 3: 0 ]) of m bits (4 bits in this example) is generated.

However, the serial/parallel converter 121B performs serial/parallel conversion as follows, unlike the serial/parallel converter 121. That is, as shown in fig. 10, the serial/parallel converter 121B performs serial/parallel conversion based on a serial data signal Ds including a serial pixel data signal PDs, a clock signal CLK, a strobe signal STB, a LATCH signal LATCH, and an emission signal FIRE. The serial/parallel converter 121B also outputs a clock signal CLK, a strobe signal STB, a LATCH signal LATCH, and a transmission signal FIRE (see fig. 10).

(parallel/serial conversion section 123B)

The parallel-serial converter 123B is a circuit that performs predetermined parallel-serial conversion based on the m-bit (4-bit in this example) parallel pixel data signal PDp and the clock signal CLK, as in the parallel-serial converter 123. Specifically, the parallel-serial conversion section 123B performs parallel-serial conversion based on the 4-bit parallel pixel data signal PDp, the clock signal CLK, the strobe signal STB, the LATCH signal LATCH, and the emission signal FIRE, which are output from the shift register section 122A (see fig. 10).

By such parallel/serial conversion, as shown in fig. 10, the serial data signal Ds described above is generated (regenerated). The serial data signal Ds, the clock signal CLK, the strobe signal STB, the LATCH signal LATCH, and the transmission signal FIRE are output to the outside of the drive circuit sections 14a, 14b, and 14c, respectively.

The serial data signal Ds, the clock signal CLK, the strobe signal STB, the LATCH signal LATCH, and the FIRE signal FIRE, which are output from the parallel-to-serial conversion section 123B of the drive circuit section located on the front stage side, are input to the serial-to-parallel conversion section 121B of the drive circuit section located on the rear stage side (see fig. 10).

Thus, unlike the embodiment and the modification 1 described above, the serial pixel data signal PDs and other signals (control signals such as the strobe signal STB, the LATCH signal LATCH, and the emission signal FIRE) may not be multiplexed. In other words, these other signals may not be included in the serial data signal Ds.

In modification 2 having such a configuration, the same effects can be obtained by basically the same operations as in the embodiment.

In modification 2, as in modification 1, the 2 types of control signals (LATCH signal LATCH and FIRE signal FIRE) may be integrated into a single composite signal (LATCH/FIRE signal LATCH/FIRE) and defined (see fig. 9).

[ modification 3]

(A. formation)

Fig. 11 is a block diagram showing an example of the configuration of each of the drive circuit units 15a, 15b, and 15C in the liquid jet head (ink jet head 1C) according to modification 3. Fig. 12 schematically shows an example of the arrangement of a plurality of nozzles (10 nozzle holes Hn1 to Hn10 described later) according to modification 3.

In the inkjet head 1C according to modification 3, as in the inkjet head 1 according to the embodiment shown in fig. 1, the plurality of drive circuit units 15a, 15b, and 15C are connected in series with one another in multiple stages (cascade connection). That is, the number of stages of cascade connection of the drive circuit units 15a, 15b, and 15C in the inkjet head 1C is 3.

Here, the ink jet head 1C corresponds to a specific example of the "liquid jet head" in the present disclosure.

As shown in fig. 11, the inkjet head 1C includes ejection units 11a, 11b, and 11C and drive circuit units 15a, 15b, and 15C.

In addition, as an example, the ejection units 11a, 11b, and 11c of modification 3 are provided with 10 nozzle holes Hn1 to Hn10 (see fig. 11). These nozzle holes Hn1 to Hn10 (a plurality of nozzle holes Hn) correspond to a specific example of "nozzle" in the present disclosure.

As shown in fig. 11, the drive circuit units 15a, 15b, and 15C respectively include a serial/parallel converter 121C, a drive signal generator 125, a parallel/serial converter 123C, and a demultiplexer 124C.

(Serial/parallel conversion section 121C)

The serial/parallel converter 121C performs predetermined serial/parallel conversion based on a plurality of (2 in this example) serial data signals Ds1 and Ds2 and a clock signal CLK, unlike the serial/ parallel converters 121, 121A, and 121B described above. That is, in the modification 3, the head control unit 2 (see fig. 1) supplies two serial data signals Ds1 and Ds2 and one clock signal CLK to the drive circuit unit 15a (the foremost drive circuit unit) in the inkjet head 1C.

As will be described in detail later, two parallel pixel data signals PDp1 and PDp2 (PDp 1[ 5: 0] and PDp2[ 5: 0 ]) and a strobe signal STB of m bits (6 bits in this example) and the LATCH/FIRE signal LATCH/FIRE are generated by the serial/parallel conversion (see fig. 11). The serial-parallel converter 121C also outputs a clock signal CLK (see fig. 11).

Here, the serial data signals Ds1 and Ds2 and the clock signal CLK are also transmitted by LVDS (low voltage differential signaling) as described above, for example. As shown in fig. 11, the serial data signals Ds1 and Ds2 and the clock signal CLK are transmitted through 1 signal line, respectively. Further, the serial data signals Ds1 and Ds2 are synchronized with the clock signal CLK, and each include 7 bits of data within 1 clock period (period of the period T). However, the data is not limited to 7 bits, and may be multi-bit data other than 7 bits. The serial pixel data signals PDs1 and PDs2 corresponding to the two nozzle holes Hn in the inkjet head 1C are transmitted for each of the 1 clock period, as will be described in detail later.

In modification 3, although details will be described later (see fig. 13) with respect to the serial data signals Ds1 and Ds2, other signals are multiplexed with the serial pixel data signals PDs having m bits (6 bits in this example). Specifically, the LATCH signal LATCH, the transmission signal FIRE, and the strobe signal STB are respectively included in any one of the 2 serial data signals Ds1 and Ds 2.

The two serial data signals Ds1 and Ds2 correspond to a specific example of "n (n: an integer of 2 or more) serial data signals" in the present disclosure.

Here, for example, as shown in fig. 12, in modification 3, a plurality of nozzle holes Hn (10 nozzle holes Hn1 to Hn 10) in the inkjet head 1C are grouped as follows. That is, in this example, the 10 nozzle holes Hn1 to Hn10 are grouped so as to belong to either one of the two nozzle groups Gp1 and Gp 2. Specifically, in the example shown in fig. 12, the nozzle holes Hn2, Hn4, Hn6, Hn8, Hn10 located at the even-numbered positions belong to the nozzle group Gp 1. On the other hand, nozzle holes Hn1, Hn3, Hn5, Hn7, Hn9 located in odd-numbered nozzle holes belong to the nozzle group Gp 2.

The two serial data signals Ds1 and Ds2 include serial pixel data signals corresponding to the nozzle hole Hn belonging to the corresponding one of the two nozzle groups Gp1 and Gp2, respectively. Specifically, as shown in fig. 12, the serial data signal Ds1 includes serial pixel data signals PDs1 corresponding to the nozzle holes Hn2, Hn4, Hn6, Hn8, and Hn10 belonging to the nozzle group Gp1 (see a dotted arrow P41). On the other hand, as shown in fig. 12, the serial data signal Ds2 includes serial pixel data signals PDs2 corresponding to the nozzle holes Hn1, Hn3, Hn5, Hn7, Hn9 belonging to the nozzle group Gp2 (see a dotted arrow P42). The method of assigning the nozzle groups or the nozzle holes Hn to the serial data signals Ds1 and Ds2 is not limited to the example shown in fig. 12, and the nozzle groups or the nozzle holes Hn may be assigned by another method.

(branching filter 124C)

The demultiplexer 124C is a circuit for demultiplexing a single combined signal, i.e., LATCH/transmit signal LATCH/FIRE, into a LATCH signal LATCH and a transmit signal FIRE, as in the demultiplexer 124A described above. In particular, as shown in fig. 11, the demultiplexer 124C is configured by a NOT circuit (NOT circuit) 45. Specifically, a logical not signal (inverted signal) of the LATCH/FIRE signal LATCH/FIRE is generated as the FIRE signal FIRE, and the LATCH/FIRE signal LATCH/FIRE is output as it is as the LATCH signal LATCH.

The LATCH signal LATCH and the transmission signal FIRE generated in this way are output to the LATCH circuit portion 125B and the waveform generation circuit portion 125C, respectively (see fig. 11).

(drive signal generating section 125)

The drive signal generation unit 125 includes a shift register unit 125A, a latch circuit unit 125B, a waveform generation circuit unit 125C, a level conversion circuit 125D, and an and logic circuit 40.

The shift register unit 125A is a circuit for sequentially transmitting and holding the two parallel pixel data signals PDp1 and PDp2 from the front stage side to the rear stage side in accordance with the drive signal Sd for each of the plurality of nozzle holes Hn (see fig. 11). The shift register section 125A includes the same number (10 in this example) of D-FF circuits 41 as the number of the plurality of nozzle holes Hn. Each D-FF circuit 41 can hold the parallel pixel data signal PDp1 with 6 bits or the parallel pixel data signal PDp2 with 6 bits.

As shown in fig. 11, the and signal Scom generated by the and circuit 40 is input to each D-FF circuit 41 as a shift clock when the signals are sequentially transferred, as in the embodiment (see fig. 2). In other words, the shift register unit 125A sequentially transfers the parallel pixel data signals PDp1 and PDp2 in synchronization with the logical sum signal Scom.

The LATCH circuit section 125B is a circuit that holds the 6-bit parallel pixel data signals PDp1 and PDp2 for each of the plurality of nozzle holes Hn, which are output from the respective D-FF circuits 41 in the shift register section 125A, in synchronization with the LATCH signal LATCH (see fig. 11). The latch circuit portion 125B includes the same number (10 in this example) of latch circuits 42 as the number of the plurality of nozzle holes Hn. Each latch circuit 42 can hold the parallel pixel data signal PDp1 with 6 bits or the parallel pixel data signal PDp2 with 6 bits.

The waveform generation circuit 125C is a circuit that generates a waveform signal that is a basis of the drive signal Sd based on the 6-bit parallel pixel data signals PDp1 and PDp2 for each of the plurality of nozzle holes Hn, which are output from the latch circuits 42 in the latch circuit 125B (see fig. 11). The waveform generation circuit 125C includes the same number (10 in this example) of waveform generation circuits 43 as the number of the plurality of nozzle holes Hn, and each waveform generation circuit 43 generates such a waveform signal in synchronization with the emission signal FIRE.

The level shifter circuit 125D is a circuit for generating a drive signal Sd for each of the plurality of nozzle holes Hn based on the waveform signal for each of the plurality of nozzle holes Hn output from each waveform generator circuit 43 in the waveform generator circuit portion 125C (see fig. 11). Specifically, the level shifter circuit 125D generates the driving signals Sd having the driving voltages Vd corresponding to the nozzle holes Hn (nozzle holes Hn1 to Hn 10) by shifting the levels (voltage values) of the waveform signals.

(parallel/serial conversion section 123C)

The parallel-serial converter 123C is a circuit that performs predetermined parallel-serial conversion based on two serial data signals Ds1 and Ds2 and a clock signal CLK, unlike the parallel- serial converters 123, 123A, and 123B described above. Specifically, the parallel-serial conversion section 123C performs parallel-serial conversion based on the 6-bit parallel pixel data signals PDp1 and PDp2, the clock signal CLK, the strobe signal STB, and the LATCH/FIRE signal LATCH/FIRE output from the shift register section 125A (see fig. 11).

By such parallel/serial conversion, as shown in fig. 11, the two serial data signals Ds1 and Ds2 are generated (regenerated) and output to the outside of the drive circuit units 15a, 15b, and 15c together with the clock signal CLK.

The serial data signals Ds1 and Ds2 and the clock signal CLK output from the parallel-to-serial converter 123C of the driver circuit section located on the front stage side are input to the serial-to-parallel converter 121C of the driver circuit section located on the rear stage side (see fig. 11).

(B. data transfer action)

Here, fig. 13 schematically shows an operation example (data transfer operation example) in each of the drive circuit units 15a, 15b, and 15c shown in fig. 11 in a timing chart.

In fig. 13, (a), (B), and (C) respectively show the clock signal CLK, the serial data signal Ds1, and the serial data signal Ds2 which are input to (the serial/parallel conversion section 121C in) the drive circuit sections 15a, 15B, and 15C. Further, (D) and (E) show 7-bit parallel data (including 6-bit parallel pixel data signals PDp1[ 5: 0] and PDp2[ 5: 0] respectively) after serial/parallel conversion of the serial data signals Ds1 and Ds2, respectively.

On the other hand, (F), (G), and (H) in fig. 13 show the clock signal CLK, the serial data signal Ds1, and the serial data signal Ds2 output from (the parallel-to-serial conversion section 123C in) the drive circuit sections 15a, 15b, and 15C, respectively. In addition, (I) and (J) show 7-bit parallel data before parallel/serial conversion (including 6-bit parallel pixel data signals PDp1[ 5: 0], PDp2[ 5: 0], respectively).

The data transfer operation in modification 3 is as follows in the drive circuit units 15a, 15b, and 15c, as shown in fig. 13, for example. That is, first, the serial data signals Ds1 and Ds2 contain 7-bit serial data in a period (1 clock period) of the cycle T in synchronization with the clock signal CLK (see fig. 13a to 13C). The serial data signal Ds1 is serial-to-parallel converted by the serial-to-parallel converter 121C, thereby generating a parallel pixel data signal PDp1[ 5: 0] of 6 bits and a strobe signal STB, respectively (see fig. 13B and 13D). On the other hand, the serial data signal Ds2 is serial-to-parallel converted by the serial-to-parallel converter 121C, thereby generating a 6-bit parallel pixel data signal PDp2[ 5: 0] and a LATCH/FIRE signal LATCH/FIRE, respectively (see fig. 13 (C) and 13 (E)).

In this example, the first 6 bits of the serial data signal Ds1 become the serial pixel data signal PDs1, and then are arranged in the order of the strobe signal STB. Similarly, in this example, the first 6 bits of the serial data signal Ds2 become the serial pixel data signal PDs2, and then are arranged in the order of LATCH/FIRE signals LATCH/FIRE.

Here, only during a period (a period from the timing t31 to the timing t 36) in which the strobe signal STB thus generated is "1", a shift clock (and signal Scom) is input to each D-FF circuit 41 in the shift register unit 125A. Therefore, this period becomes an effective period for data input to the shift register section 125A (input of the parallel pixel data signals PDp1, PDp 2) (see fig. 13D and 13E).

In this period, first, the parallel pixel data signals PDp1 and PDp2 corresponding to the nozzle holes Hn1 to Hn10 are sequentially input to the shift register unit 125A. Next, in the shift register section 125A, the parallel pixel data signals PDp1 and PDp2 sequentially transferred and held are held in the LATCH circuits 42 in the LATCH circuit section 125B at the timing when the LATCH/emission signal LATCH/FIRE changes from "0" to "1" (timing t 37), respectively (see fig. 13E). Next, at the timing when the LATCH/FIRE signal LATCH/FIRE subsequently changes from "1" to "0" (timing t 39), each waveform generation circuit 43 in the waveform generation circuit portion 125C starts generating a waveform signal that serves as a basis of the drive signal Sd based on the parallel pixel data signals PDp1 and PDp2 held in each LATCH circuit 42 (see fig. 13E). The level shifter circuit 125D generates a drive signal Sd corresponding to each nozzle hole Hn based on the waveform signals, and drives the drive wall based on the drive signal Sd (as a result, for example, ink 9 is discharged from each nozzle hole Hn) (see timings t39 to t40 in fig. 11 and 13).

At this time, the parallel-to-serial conversion of the 6-bit parallel pixel data signals PDp1[ 5: 0] and PDp2[ 5: 0] output from the D-FF circuit 41 of the last stage of the shift register unit 125A is completed in the parallel-to-serial conversion unit 123C. Specifically, the serial data signals Ds1 and Ds2 (see fig. 13 (F) to 13 (J)) are regenerated by performing parallel/serial conversion based on the 6-bit parallel pixel data signals PDp1[ 5: 0], PDp2[ 5: 0], the strobe signal STB and the LATCH/FIRE signal LATCH/FIRE. The serial data signals Ds1 and Ds2 thus regenerated are output from the parallel-to-serial converter 123C to the outside of the driver circuit units 15a, 15b, and 15C, respectively, together with the clock signal CLK (see fig. 13 (I) and 13 (J)).

In this case, as shown by broken-line arrows P51 and P52 in fig. 13, for example, the data in the drive circuit sections 15a, 15b, and 15c are sequentially shifted by a period of 7 cycles T (by 7 cycles). Specifically, the parallel pixel data signals PDp1 and PDp2 included in the serial data signals Ds1 and Ds2 input until the timing t31 are included in the serial data signals Ds1 and Ds2 and output during the timings t33 to t38, respectively (see the dotted arrow P52). Similarly, the parallel pixel data signals PDp1 and PDp2 included in the serial data signals Ds1 and Ds2 input during the period from the timing t31 to t36 are included in the serial data signals Ds1 and Ds2 and output during the period from the timing t38 to t43, respectively (see the dotted arrow P51). In fig. 13, the above-described sequential transmission is not performed during a period in which the strobe signal STB becomes "0" (timings t36 to t43 in fig. 13 (D) and (E)). Therefore, as shown by timings t38 to t43 in "PDp 1[ 5: 0 ]", "PDp 2[ 5: 0 ]" (OUT) in fig. 13 (I) and (J), the parallel pixel data signals PDp1[ 5: 0], PDp2[ 5: 0] are kept unchanged as "Dn _10_ 1" or "Dn _9_ 1", respectively.

The data transfer operation of the entire inkjet head 1C is as follows, as in the case of the above-described embodiment (data transfer operation of the entire inkjet head 1: see fig. 7). That is, first, the 6-bit parallel pixel data signals PDp1 and PDp2 in the driver circuit unit 15a become serial data signals Ds1 and Ds2, respectively, as described above, and are output to the driver circuit unit 15b at the subsequent stage of the driver circuit unit 15 a. Similarly, the 6-bit parallel pixel data signals PDp1 and PDp2 in the driver circuit unit 15b become serial data signals Ds1 and Ds2, respectively, as described above, and are output to the driver circuit unit 15c at the subsequent stage (final stage) of the driver circuit unit 15 b.

At this time, the parallel pixel data signals PDp1 and PDp2 corresponding to the drive circuit units 15a, 15b, and 15c are sequentially transferred from the drive circuit unit 15a to the drive circuit units 15b and 15c while being sequentially shifted, as in the case of the embodiment (see fig. 7).

(C. action/Effect)

In modification 3 having such a configuration, the same effects can be obtained by basically the same operations as in the embodiment.

In addition, in particular, in modification 3, since a plurality of (2 in this example) serial data signals Ds1 and Ds2 are used, the following effects can be obtained, for example. That is, in these plural (2) serial data signals Ds1, Ds2, the degree of freedom of the number of bits of the respective serial pixel data signals PDs1, PDs2 or the configuration of the control signals (LATCH signal, FIRE signal, strobe signal STB, etc.) can be improved. That is, for example, by increasing the number of bits of each of the serial pixel data signals PDs1 and PDs2, more data can be transmitted, and the overhead of the control signal can be reduced.

In modification 3, the case where two serial data signals Ds1 and Ds2 are used has been described as an example, but the present invention is not limited to this example, and 3 or more serial data signals may be used. That is, in a broad sense, the serial data signal may be constituted by n (an integer of n: 2 or more) serial data signals. In this case, as in modification 3, the plurality of nozzle holes Hn in the inkjet head may be grouped so as to belong to any one of the plurality of nozzle groups. In this case, the n serial data signals may include serial pixel data signals corresponding to the nozzle holes Hn belonging to one or more nozzle groups among the plurality of nozzle groups. That is, as for the method (regularity) of associating the serial pixel data signal corresponding to each nozzle hole Hn with each serial data signal, various methods can be used instead of the method of associating with each nozzle group.

[ modification 4]

Fig. 14 is a block diagram showing an example of the configuration of each of the drive circuit sections 16a, 16b, and 16c in the liquid jet head (ink jet head 1D) according to modification 4. In the inkjet head 1D of modification 4, as in the inkjet head 1 of the embodiment shown in fig. 1, the plurality of drive circuit units 16a, 16b, and 16c are connected in series with one another in multiple stages (cascade connection). That is, the number of stages of cascade connection of the drive circuit units 16a, 16b, and 16c in the inkjet head 1D is 3.

The drive circuit units 16a, 16b, and 16C in the inkjet head 1D correspond to the following modifications of the drive circuit units 15a, 15b, and 15C (see fig. 11) in the inkjet head 1C according to modification 3. That is, as shown in fig. 14, the respective drive circuit units 16a, 16b, and 16C correspond to the configuration in which the serial/parallel converter 121D and the parallel/serial converter 123D are provided in place of the serial/parallel converter 121C and the parallel/serial converter 123C in the respective drive circuit units 15a, 15b, and 15C, and the other configurations are basically the same.

The ink jet head 1D corresponds to a specific example of the "liquid jet head" in the present disclosure.

(Serial/parallel conversion section 121D)

The serial/parallel converter 121D is a circuit that performs predetermined serial/parallel conversion based on various signals supplied from the external head control unit 2, as in the serial/parallel converter 121C (see fig. 11) of modification 3. By such serial/parallel conversion, m-bit (6-bit in this example) parallel pixel data signals PDp1 and PDp2 are generated, respectively, as shown in fig. 14.

However, unlike the serial/parallel converter 121C, the serial/parallel converter 121D performs serial/parallel conversion as follows. That is, as shown in fig. 14, the serial/parallel conversion section 121D performs serial/parallel conversion based on serial data signals Ds1, Ds2, a clock signal CLK, a strobe signal STB, and LATCH/FIRE signals LATCH/FIRE. The serial/parallel converter 121D also outputs a clock signal CLK, a strobe signal STB, and LATCH/FIRE signals LATCH/FIRE (see fig. 14).

(parallel/serial conversion section 123D)

The parallel-serial converter 123D is a circuit for performing predetermined parallel-serial conversion based on m-bit (6-bit in this example) parallel pixel data signals PDp1 and PDp2 and a clock signal CLK, as in the parallel-serial converter 123C of modification example 3. Specifically, the parallel-serial conversion section 123D performs parallel-serial conversion based on the 6-bit parallel pixel data signals PDp1 and PDp2, the clock signal CLK, the strobe signal STB, and the LATCH/FIRE signal LATCH/FIRE output from the shift register section 125A (see fig. 14).

By such parallel/serial conversion, as shown in fig. 14, the two serial data signals Ds1 and Ds2 described above are generated (regenerated) respectively. Further, these serial data signals Ds1, Ds2, clock signal CLK, strobe signal STB, and LATCH/FIRE signal LATCH/FIRE are output to the outside of the respective driver circuit sections 16a, 16b, 16c, respectively.

Serial data signals Ds1 and Ds2, a clock signal CLK, a strobe signal STB, and LATCH/FIRE signals LATCH/FIRE, which are output from the parallel/serial conversion section 123D of the drive circuit section located on the front-stage side, are input to the serial/parallel conversion section 121D of the drive circuit section located on the rear-stage side (see fig. 14).

Thus, unlike modification 3 described above, the serial pixel data signals PDs1 and PDs2 and other signals (control signals such as the strobe signal STB and the LATCH/FIRE signal LATCH/FIRE) may not be multiplexed. In other words, as in modification 2 described above, these other signals may not be included in the serial data signals (serial data signals Ds1 and Ds 2).

In modification 4 having such a configuration, the same effects can be obtained by basically the same operations as in modification 3.

< 3. other modifications

The present disclosure has been described above by way of some embodiments and modifications, but the present disclosure is not limited to these embodiments and the like, and various modifications are possible.

For example, although the above embodiments and the like have been described with specific examples of the configuration (shape, arrangement, number, and the like) of the members in the printer 3 and the inkjet heads 1, 1A to 1D, the configuration is not limited to the configuration described in the above embodiments and the like, and other shapes, arrangements, numbers, and the like may be used.

As the structure of the inkjet head, various types of inkjet heads can be applied. That is, for example, a so-called side-shooter type ink jet head that ejects the ink 9 from the center portion in the extending direction of each ejection channel in the piezoelectric actuator 111 may be used. Alternatively, for example, a so-called edge-jet type ink jet head that ejects the ink 9 along the extending direction of each ejection channel may be used. Further, the printer system is not limited to the system described in the above embodiment and the like, and various Systems such as a thermal (bubble jet) system, a MEMS (Micro Electro Mechanical Systems) system, a thermal paper system, and a click system can be applied.

For example, the present disclosure can be applied to any of a circulation type inkjet head that circulates and uses the ink 9 between the ink tank and the inkjet head, and a non-circulation type inkjet head that does not circulate and uses the ink 9.

Further, although the above embodiments and the like have been described by specifically taking an example of a data transmission method, the present invention is not limited to the example of the above embodiments and the like, and data transmission may be performed by other methods. Specifically, for example, in a data transmission method using the so-called "8B/10B scheme", the method of the present disclosure can be applied by providing an 8B/10B decoder, an encoder, and a protocol control circuit.

The series of processing described in the above embodiments and the like may be performed by hardware (circuit) or may be performed by software (program). In the case of software, the software is constituted by a group of programs for causing a computer to execute each function. Each program may be installed in the computer and used, for example, or may be installed in the computer from a network or a recording medium and used.

In the above-described embodiments and the like, the printer 3 (ink jet printer) is described as a specific example of the "liquid jet recording apparatus" in the present disclosure, but the present disclosure is not limited to this example and can be applied to apparatuses other than ink jet printers. In other words, the "liquid ejecting head" (ink jet head) of the present disclosure may be applied to other apparatuses than an ink jet printer. Specifically, the "liquid ejecting head" of the present disclosure is applied to, for example, a device such as a 3D printer, a facsimile machine, or an on-demand printer.

Further, the various examples described above may be applied in any combination.

The effects described in the present specification are merely exemplary, and are not limited to these, and other effects may be provided.

In addition, the present disclosure may have the following configuration.

(1) A liquid ejecting head includes:

an ejection section having a plurality of nozzles that eject liquid; and

one or more drive circuit sections that generate a drive signal for ejecting the liquid from the nozzles based on a serial data signal, a clock signal, a latch signal, an emission signal, and a strobe signal supplied from an external head control section, and output the drive signal to the ejection section,

the drive circuit unit includes:

a serial/parallel conversion unit that performs serial/parallel conversion on the basis of the serial data signal including m-bit (m: an integer equal to or greater than 2) serial pixel data signals individually specified for each of the plurality of nozzles and the clock signal, thereby generating m-bit parallel pixel data signals;

a drive signal generation section that generates the drive signal for each of the plurality of nozzles based on the m-bit parallel pixel data signal, the latch signal, the emission signal, the gate signal, and the clock signal; and

a parallel/serial conversion section that performs parallel/serial conversion based on the m-bit parallel pixel data signal and the clock signal to generate the serial data signal, and outputs the serial data signal and the clock signal to the outside of the drive circuit section, respectively.

(2) The liquid jet head according to the above (1), wherein,

in each of the plurality of driving circuit sections,

the serial data signal and the clock signal output from the parallel/serial conversion section in the drive circuit section located on the front stage side relative to each other are respectively

Inputting to the serial/parallel conversion section in the drive circuit section located relatively on the rear stage side,

so that the plurality of driving circuit parts are connected to each other in series in multiple stages.

(3) The liquid jet head according to the above (1) or (2), wherein,

the serial data signal including the m-bit serial pixel data signal and further including the latch signal, the transmission signal, and the strobe signal,

the serial/parallel conversion section performs the serial/parallel conversion based on the serial data signal and the clock signal to generate the parallel pixel data signal of the m bits, the latch signal, the emission signal, and the strobe signal, respectively,

the parallel/serial conversion section performs the parallel/serial conversion based on the m-bit parallel pixel data signal, the latch signal, the transmission signal, and the strobe signal, thereby generating the serial data signal.

(4) The liquid jet head according to the above (3), wherein,

the serial data signal is formed from a single serial data signal,

the single serial data signal includes the serial pixel data signals, the latch signal, the emission signal, and the strobe signal in the number corresponding to all the nozzles.

(5) The liquid jet head according to the above (3), wherein,

the serial data signal is composed of n (integer of n: 2 or more) serial data signals, and

the plurality of nozzles are grouped so as to belong to any one of n nozzle groups,

the n serial data signals are each configured to include the serial pixel data signals corresponding to nozzles belonging to a corresponding one or more of the n nozzle groups,

the latch signal, the transmission signal, and the strobe signal are respectively included in any one of the n serial data signals.

(6) The liquid ejecting head according to any one of the above (1) to (5),

the latch signal and the transmit signal are both transmitted,

a single composite signal defined by the rising timing and falling timing of the utilization signal, or

The signal processing device is configured by a single composite signal in which the rising timing and a timing after a predetermined time from the rising timing are individually defined.

(7) The liquid ejecting head according to any one of the above (1) to (6),

the drive signal generating section has a shift register section for sequentially transferring and holding the m-bit parallel pixel data signals from a front stage side to a rear stage side in accordance with the drive signal of each of the plurality of nozzles,

the shift register section sequentially transfers the strobe signal and the clock signal from the front stage side to the rear stage side in synchronization with a logical AND signal.

(8) A liquid ejection recording apparatus includes:

the liquid ejecting head according to any one of the above (1) to (7); and

and a head control unit configured to supply the serial data signal, the clock signal, the latch signal, the emission signal, and the strobe signal to the liquid ejecting head, respectively.

Description of the reference symbols

1. 1A, 1B, 1C, 1D inkjet heads; 11. 11a, 11b, 11c ejection portions; 111 piezoelectric actuators (actuator plates); 112 a nozzle plate; 12a, 12b, 12c, 13a, 13b, 13c, 14a, 14b, 14c, 15a, 15b, 15c, 16a, 16b, 16c drive circuit sections; 121. 121A, 121B, 121C, 121D serial/parallel conversion units; 122. 125a drive signal generating section; 122A, 125A shift register sections; 122B, 125B latch circuit portions; 122C and 125C waveform generating circuit sections; 122D, 125D level shifting circuits; 123. 123A, 123B, 123C, 123D parallel/serial conversion sections; 124A, 124C wave splitters; 2a control part; 3, a printer; a 40 logical AND circuit (AND circuit); a 41D-FF circuit; a 42 latch circuit; 43 a waveform generating circuit; 45 a logical NOT circuit (NOT circuit); 9 ink; hn, Hn 1-Hn 10 nozzle holes; gp1, Gp2 nozzle group; ds, Ds1, Ds2 serial data signals; PDs, PDs1, PDs2 serial pixel data signals; PDp, PDp1, PDp2 parallel pixel data signals; a CLK clock signal; an STB strobe signal; a LATCH LATCH signal; FIRE transmit signal; LATCH/FIRE signal; a Scom logical and signal; an Sd drive signal; vd drive voltage; t time; Δ t set time; timing t 11-t 23 and t 31-t 43; and (4) T period.

Claims (8)

1. A liquid ejecting head includes:

an ejection section having a plurality of nozzles that eject liquid; and

one or more drive circuit sections that generate a drive signal for ejecting the liquid from the nozzles based on a serial data signal, a clock signal, a latch signal, an emission signal, and a strobe signal supplied from an external head control section, and output the drive signal to the ejection section,

the drive circuit unit includes:

a serial/parallel conversion unit that performs serial/parallel conversion based on the serial data signal including m-bit serial pixel data signals, where m is an integer equal to or greater than 2, individually defined for each of the plurality of nozzles, and the clock signal, and generates the m-bit parallel pixel data signals;

a drive signal generation section that generates the drive signal for each of the plurality of nozzles based on the m-bit parallel pixel data signal, the latch signal, the emission signal, the gate signal, and the clock signal; and

a parallel/serial conversion section that performs parallel/serial conversion based on the m-bit parallel pixel data signal and the clock signal to generate the serial data signal, and outputs the serial data signal and the clock signal to the outside of the drive circuit section, respectively.

2. The liquid ejection head according to claim 1,

in each of the plurality of driving circuit sections,

the serial data signal and the clock signal output from the parallel/serial conversion section in the drive circuit section located on the front stage side relative to each other are respectively

Inputting to the serial/parallel conversion section in the drive circuit section located relatively on the rear stage side,

so that the plurality of driving circuit parts are connected to each other in series in multiple stages.

3. The liquid ejection head according to claim 1 or claim 2,

the serial data signal including the m-bit serial pixel data signal and further including the latch signal, the transmission signal, and the strobe signal,

the serial/parallel conversion section performs the serial/parallel conversion based on the serial data signal and the clock signal to generate the parallel pixel data signal of the m bits, the latch signal, the emission signal, and the strobe signal, respectively,

the parallel/serial conversion section performs the parallel/serial conversion based on the m-bit parallel pixel data signal, the latch signal, the transmission signal, and the strobe signal, thereby generating the serial data signal.

4. The liquid ejection head according to claim 3,

the serial data signal is formed from a single serial data signal,

the single serial data signal includes the serial pixel data signals, the latch signal, the emission signal, and the strobe signal in the number corresponding to all the nozzles.

5. The liquid ejection head according to claim 3,

the serial data signal is composed of n serial data signals, where n is an integer of 2 or more, and

the plurality of nozzles are grouped so as to belong to any one of n nozzle groups,

the n serial data signals are each configured to include the serial pixel data signals corresponding to nozzles belonging to a corresponding one or more of the n nozzle groups,

the latch signal, the transmission signal, and the strobe signal are respectively included in any one of the n serial data signals.

6. The liquid ejection head according to claim 1 or claim 2,

the latch signal and the transmit signal are both transmitted,

a single composite signal defined by the rising timing and falling timing of the utilization signal, or

The signal processing device is configured by a single composite signal in which the rising timing and a timing after a predetermined time from the rising timing are individually defined.

7. The liquid ejection head according to claim 1 or claim 2,

the drive signal generating section has a shift register section for sequentially transferring and holding the m-bit parallel pixel data signals from a front stage side to a rear stage side in accordance with the drive signal of each of the plurality of nozzles,

the shift register section sequentially transfers the strobe signal and the clock signal from the front stage side to the rear stage side in synchronization with a logical AND signal.

8. A liquid ejection recording apparatus includes:

the liquid ejection head as claimed in claim 1 or claim 2; and

and a head control unit configured to supply the serial data signal, the clock signal, the latch signal, the emission signal, and the strobe signal to the liquid ejecting head, respectively.

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