JP7048436B2 - Liquid injection head and liquid injection recording device - Google Patents

Description

The present disclosure relates to a liquid injection head and a liquid injection recording device.

A liquid injection recording device provided with a liquid injection head is used in various fields, and various types of liquid injection heads have been developed. Further, for example, Patent Document 1 proposes a method of data transfer in a liquid injection head.

Japanese Unexamined Patent Publication No. 2013-226765

In such a liquid injection head, it is generally required to reduce the number of signal lines at the time of data transfer. It is desirable to provide a liquid injection head and a liquid injection recording device capable of reducing the number of signal lines.

The liquid injection head according to the embodiment of the present disclosure includes a serial data signal, a clock signal, a latch signal, and a firing signal supplied from an injection unit having a plurality of nozzles for injecting liquid and an external head control unit. And, based on the strobe signal, it is provided with one or a plurality of drive circuit units that generate a drive signal for injecting a liquid from a nozzle and output the drive signal to the injection unit. The drive circuit unit is serial / parallel based on a serial data signal configured to include m-bit (m: an integer of 2 or more) serial pixel data signals individually defined for each of a plurality of nozzles and a clock signal. Based on a serial / parallel conversion unit that generates an m-bit parallel pixel data signal by performing conversion, an m-bit parallel pixel data signal, a latch signal, a firing signal, a strobe signal, and a clock signal. The serial data signal is generated by performing parallel / serial conversion based on the drive signal generation unit that generates the drive signal for each of a plurality of nozzles, the m-bit parallel pixel data signal, and the clock signal. Each has a parallel / serial conversion unit that outputs the serial data signal and the clock signal to the outside of the drive circuit unit.

The liquid injection recording device according to the embodiment of the present disclosure has the liquid injection head according to the embodiment of the present disclosure, and the serial data signal, the clock signal, the latch signal, the firing signal and the strobe signal, respectively. It is provided with a head control unit that supplies a liquid injection head.

According to the liquid injection head and the liquid injection recording device according to the embodiment of the present disclosure, it is possible to reduce the number of signal lines.

It is a block diagram which shows the schematic structural example of the liquid injection apparatus which concerns on one Embodiment of this disclosure. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head shown in FIG. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head which concerns on a comparative example. It is a timing diagram schematically showing the operation example in the liquid injection head which concerns on a comparative example. It is a timing diagram schematically showing the operation example in each drive circuit part shown in FIG. It is a timing diagram schematically showing a part of the operation example shown in FIG. 5 in an enlarged manner. FIG. 3 is a timing diagram schematically showing an operation example of the entire liquid injection head shown in FIG. 1. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head which concerns on modification 1. FIG. It is a timing diagram schematically showing the operation example in the demultiplexer shown in FIG. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head which concerns on modification 2. FIG. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head which concerns on modification 3. FIG. It is a schematic diagram which shows the structural example of grouping of a plurality of nozzles which concerns on modification 3. FIG. It is a timing diagram schematically showing the operation example in each drive circuit part shown in FIG. It is a block diagram which shows the structural example of each drive circuit part in the liquid injection head which concerns on modification 4.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The explanation will be given in the following order.
1. 1. Embodiment (example of data transfer using a single serial data signal)
2. 2. Modification example Modification 1 (example when the latch signal and firing signal are used as a single composite signal)
Modification 2 (Example when the serial pixel data signal and other signals are not multiplexed)
Modification 3 (Example of data transfer using a plurality of serial data signals)
Modification 4 (Example in the case where the modification is not multiplexed in the modification 3 as in the modification 2)
3. 3. Other variants

<1. Embodiment>
[Configuration of printer 3]
FIG. 1 is a block diagram showing a schematic configuration example of a printer 3 as a liquid injection recording device according to an embodiment of the present disclosure. Further, FIG. 2 is a block diagram showing a configuration example of each drive circuit unit (drive circuit unit 12a, 12b, 12c described later) in the inkjet head 1 as the liquid injection head shown in FIG. .. In addition, in these FIGS. 1 and 2, "/ N" (N: an integer of 2 or more) shown on the wiring of the signal indicates the number of wirings, and the subsequent block diagrams (FIGS. 3 and 3 described later). The same applies to FIGS. 8, 10, 11, and 14). Further, in each drawing used in the description of the present specification, the scale of each member is appropriately changed in order to make each member a recognizable size.

The printer 3 is an inkjet printer that records (prints) images, characters, and the like on a recording medium (for example, recording paper) using ink 9, which will be described later. As shown in FIG. 1, the printer 3 includes an inkjet head 1 and a head control unit 2.

The inkjet head 1 corresponds to a specific example of the "liquid injection head" in the present disclosure, and the printer 3 corresponds to a specific example of the "liquid injection recording device" in the present disclosure. Further, the ink 9 corresponds to a specific example of the "liquid" in the present disclosure.

(A. Head control unit 2)
The head control unit 2 supplies various information (data) to the inkjet head 1. Specifically, as shown in FIG. 1, the head control unit 2 has one (single) serial data with respect to the drive circuit unit 12a (the drive circuit unit in the front stage) described later in the inkjet head 1. The signal Ds and one clock signal CLK are supplied respectively.

Here, these serial data signals Ds and clock signal CLK are each transmitted by, for example, LVDS (Low Voltage Differential Signaling). This enables high-speed transmission using a small-amplitude signal, and improves the ability to remove common-mode noise by using a differential signal. Further, the serial data signal Ds and the clock signal CLK are each transmitted by one signal line as shown in FIG. Further, the serial data signals Ds are synchronized with the clock signal CLK, and include 7 bits of serial data within one clock period (a period of one cycle T described later). However, the data is not limited to 7 bits, and may be a plurality of bits of serial data other than 7 bits.

Further, in the present embodiment, the serial data signal Ds will be described in detail later (see FIG. 5), but together with the serial pixel data signal PDs of m bits (m: an integer of 2 or more, 4 bits in this example). , Other signals are multiplexed. Specifically, in this example, the serial data signal Ds includes the latch signal LATCH, the firing signal (discharge start signal) FIRE, and the strobe signal STB (STROBE), which will be described later, together with the 4-bit serial pixel data signal PDs. It is composed of. Further, in the present embodiment, such a single serial data signal Ds is a serial pixel data signal individually defined corresponding to all the nozzles among the plurality of nozzles described later in the inkjet head 1. PDs are included.

It should be noted that such serial data signals Ds correspond to a specific example of the "single serial data signal" in the present disclosure.

(B. Inkjet head 1)
As shown by the broken line arrows in FIGS. 1 and 2, the inkjet head 1 ejects (ejects) droplet-shaped ink 9 from a plurality of nozzles, which will be described later, onto a recording medium to produce images and characters. It is a head that records such as. As shown in FIG. 1, the inkjet head 1 includes an injection unit 11 and a plurality of drive circuit units (in this example, three drive circuit units 12a, 12b, 12c). Inkjet 9 is supplied into the inkjet head 1 from an ink tank (not shown) via a supply tube or the like.

(B-1. Injection unit 11)
As shown in FIG. 1, the injection unit 11 includes a plurality of (three in this example) injection units 11a, 11b, and 11c. The injection units 11a, 11b, and 11c are arranged so as to individually correspond to the drive circuit units 12a, 12b, and 12c described above, respectively. Each of these injection units 11a, 11b, 11c has the above-mentioned plurality of nozzles, and these nozzles are according to the drive signal Sd (drive voltage Vd) individually supplied from the drive circuit units 12a, 12b, 12c. Ink 9 is ejected from.

Such injection portions 11a, 11b, and 11c are configured to include a piezoelectric actuator (actuator plate) 111 and a nozzle plate 112, respectively, as shown in FIG. 2, for example.

The nozzle plate 112 is a plate made of a film material such as polyimide or a metal material, and as shown in FIG. 2, the plurality of nozzles described above (in this example, five nozzle holes Hn1 to Hn5: in the following, as appropriate). It has a nozzle hole Hn). These nozzle holes Hn1 to Hn5 are formed, for example, in a straight line (one row) at predetermined intervals, and have, for example, a circular shape.

Each of these nozzle holes Hn1 to Hn5 (plurality of nozzle holes Hn) corresponds to a specific example of the "nozzle" in the present disclosure.

The piezoelectric actuator 111 is a plate made of a piezoelectric material such as PZT (lead zirconate titanate). The piezoelectric actuator 111 is provided with a plurality of channels (pressure chambers) (not shown). These channels are portions for applying pressure to the ink 9, and are arranged side by side so as to be parallel to each other at predetermined intervals. Each channel is defined by a drive wall (not shown) made of a piezoelectric material, and is a concave groove in a cross-sectional view.

In such a channel, there are a ejection channel for ejecting the ink 9 and a dummy channel (non-discharging channel) for not ejecting the ink 9. In other words, the ejection channel is filled with the ink 9, while the dummy channel is not filled with the ink 9. Ink 9 is supplied into the ejection channel via the above-mentioned supply tube, a predetermined flow path, and the like. Further, each discharge channel communicates with the nozzle hole Hn in the nozzle plate 112 described above, while each dummy channel does not communicate with the nozzle hole Hn. These discharge channels and dummy channels are arranged side by side alternately.

Drive electrodes (not shown) are provided on the opposite inner side surfaces of the drive wall described above. The drive electrode includes a common electrode (common electrode) provided on the inner surface facing the discharge channel and an active electrode (individual electrode) provided on the inner surface facing the dummy channel. These drive electrodes and the drive circuit units 12a, 12b, and 12c described later are electrically connected to each other via a plurality of drawer electrodes (not shown) formed on a flexible substrate (not shown). .. As a result, the drive voltage Vd (drive signal Sd) described above is applied to each drive electrode from the drive circuit units 12a, 12b, and 12c via the flexible substrate (FIGS. 1 and 2). reference).

(B-2. Drive circuit unit 12a, 12b, 12c)
As shown in FIG. 1, the drive circuit units 12a, 12b, and 12c each have a drive signal Sd (drive voltage) for injecting ink 9 from each nozzle hole Hn to the corresponding injection units 11a, 11b, 11c. It is a circuit that supplies Vd). Specifically, the drive circuit units 12a, 12b, and 12c each generate a drive signal Sd based on the serial data signal Ds and the clock signal CLK supplied from the head control unit 2 described above, and generate the drive signal Sd. It is designed to output individually to the corresponding injection units 11a, 11b, 11c.

Further, as shown in FIG. 1, these plurality of drive circuit units 12a, 12b, and 12c are connected in series (cascade connection) in the inkjet head 1 (on a drive circuit board (not shown)). There is. In other words, the number of stages of cascade connection between the drive circuit units 12a, 12b, and 12c in the inkjet head 1 is three. Specifically, as shown in FIG. 1, the cascade from the front stage side to the rear stage side in the order of the head control unit 2, the drive circuit unit 12a (front stage), the drive circuit unit 12b, and the drive circuit unit 12c (last stage). The connection is made, and the details will be described later, but the data is transferred in this order.

Here, such drive circuit units 12a, 12b, and 12c each have a serial / parallel conversion unit 121, a drive signal generation unit 122, and a parallel / serial conversion unit 123, respectively, as shown in FIG. 2, for example. ..

(Serial / Parallel Converter 121)
The serial / parallel conversion unit 121 is a predetermined serial / parallel conversion unit based on the serial data signal Ds including the above-mentioned m-bit (4 bits in this example) serial pixel data signal PDs and the clock signal CLK. It is a circuit that performs conversion. By such serial / parallel conversion, as shown in FIG. 2, an m-bit (4 bits in this example) parallel pixel data signal PDp (PDp [3: 0]) is generated.

Specifically, as shown in FIG. 2, the serial / parallel conversion unit 121 performs such serial / parallel conversion, and together with the 4-bit parallel pixel data signal PDp, the above-mentioned latch signal LATCH and firing. The signal FIRE and the strobe signal STB are generated, respectively. The clock signal CLK is also output from the serial / parallel conversion unit 121 (see FIG. 2).

(Drive signal generation unit 122)
The drive signal generation unit 122 generates the drive signal Sd (drive voltage Vd) described above for each of the plurality of nozzle holes Hn. Specifically, as shown in FIG. 2, the drive signal generation unit 122 has an m-bit (4 bits in this example) parallel pixel data signal PDp, a latch signal LATCH, a firing signal FIRE, and a strobe signal STB. And the clock signal CLK, and such a drive signal Sd is generated.

As shown in FIG. 2, such a drive signal generation unit 122 includes a shift register unit 122A, a latch circuit unit 122B, a waveform generation circuit unit 122C, a level conversion circuit 122D, and a logical product circuit (AND circuit) 40. ing.

As shown in FIG. 2, the AND circuit 40 is a logic circuit that generates a AND signal (AND signal) Com of a strobe signal STB and a clock signal CLK.

The shift register unit 122A causes the parallel pixel data signal PDp for each of the plurality of nozzle holes Hn to correspond to the drive signal Sd for each of the plurality of nozzle holes Hn from the front stage side (nozzle hole Hn1 side) to the rear stage side (nozzle hole Hn5). It is a circuit that sequentially transfers and holds to the side) (see FIG. 2). The shift register unit 122A has a D-FF (flip-flop) circuit 41 having the same number (five in this example) as the number of the plurality of nozzle holes Hn, and each D-FF circuit 41 has 4 bits. It is possible to hold the parallel pixel data signal PDp of. Further, as shown in FIG. 2, a logical AND signal Scom generated by the above-mentioned AND circuit 40 is input to each D-FF circuit 41 as a shift clock at the time of sequential transfer. There is. In other words, the shift register unit 122A sequentially transfers the parallel pixel data signal PDp described above in synchronization with the AND signal Scom described above.

As shown in FIG. 2, the latch circuit unit 122B latches the 4-bit parallel pixel data signal PDp for each of the plurality of nozzle holes Hn output from each D-FF circuit 41 in the shift register unit 122A. It is a circuit that holds in synchronization with LATCH. The latch circuit unit 122B has the same number of latch circuits 42 as the number of the plurality of nozzle holes Hn (five in this example), and each latch circuit 42 holds a 4-bit parallel pixel data signal PDp. It is possible to do.

As shown in FIG. 2, the waveform generation circuit unit 122C is driven based on a 4-bit parallel pixel data signal PDp for each of a plurality of nozzle holes Hn output from each latch circuit 42 in the latch circuit unit 122B. This is a circuit that generates a waveform signal that is the basis of the signal Sd. The waveform generation circuit unit 122C has the same number of waveform generation circuits 43 as the number of the plurality of nozzle holes Hn (five in this example), and each waveform generation circuit 43 synchronizes with the firing signal FIRE. Therefore, such a waveform signal is generated.

As shown in FIG. 2, the level conversion circuit 122D is based on the waveform signals for each of the plurality of nozzle holes Hn output from each waveform generation circuit 43 in the waveform generation circuit unit 122C, for each of the plurality of nozzle holes Hn. It is a circuit which generates the drive signal Sd of. Specifically, the level conversion circuit 122D converts the level (voltage value) of each waveform signal to generate a drive signal Sd having a drive voltage Vd corresponding to each nozzle hole Hn. ing.

(Parallel / serial conversion unit 123)
The parallel / serial conversion unit 123 is a circuit that performs predetermined parallel / serial conversion based on the above-mentioned m-bit (4 bits in this example) parallel pixel data signal PDp and the clock signal CLK. By such parallel / serial conversion, as shown in FIG. 2, the above-mentioned serial data signal Ds is generated (regenerated), and the serial data signal Ds and the clock signal CLK are generated by the respective drive circuit units 12a, respectively. It is designed to be output to the outside of 12b and 12c.

Specifically, the parallel / serial conversion unit 123 includes a 4-bit parallel pixel data signal PDp output from the shift register unit 122A (the last D-FF circuit 41), a clock signal CLK, and a strobe signal STB. , The parallel / serial conversion described above is performed based on the latch signal LATCH and the firing signal FIRE (see FIG. 2).

Here, as shown in FIGS. 1 and 2, the serial data signal Ds and the clock signal CLK output from the parallel / serial conversion unit 123 in the drive circuit unit located relatively on the front stage side are relative to each other. It is input to the serial / parallel conversion unit 121 in the drive circuit unit located on the rear stage side. Specifically, the serial data signal Ds and the clock signal CLK output from the drive circuit unit 12a on the relatively front stage side are respectively input to the drive circuit unit 12b on the rear stage side relatively. Similarly, the serial data signal Ds and the clock signal CLK output from the drive circuit unit 12b on the relatively front stage side are respectively input to the drive circuit unit 12c on the rear stage side relatively. As a result, as shown in FIG. 1, a plurality of drive circuit units 12a, 12b, and 12c are connected in series to each other in multiple stages (cascade connection).

[Operation and action / effect]
(A. Basic operation of printer 3)
In this printer 3, a recording operation (printing operation) of an image, a character, or the like on a recording medium is performed by using the ink jet operation of the ink jet head 1 as described below. Specifically, in the inkjet head 1 of the present embodiment, the ink jet operation using the shear (share) mode is performed as follows. In the printer 3, as an initial state, the ink 9 in the ink tank described above is filled in the ejection channel of the piezoelectric actuator 111 of the inkjet head 1 via the supply tube, a predetermined flow path, and the like.

First, each drive circuit unit 12a, 12b, 12c has a drive voltage Vd (drive signal Sd) with respect to the above-mentioned drive electrodes (common electrode and active electrode) in the piezoelectric actuator 111 in the corresponding injection units 11a, 11b, 11c. Is applied. Specifically, each drive circuit unit 12a, 12b, 12c applies a drive voltage Vd to each drive electrode arranged on the pair of drive walls that define the discharge channel described above. As a result, each of these pair of drive walls is deformed so as to project toward the dummy channel side adjacent to the discharge channel.

At this time, the drive wall is bent and deformed in a V shape around the intermediate position in the depth direction of the drive wall. Then, due to such bending deformation of the drive wall, the discharge channel is deformed as if it were inflated. In this way, the volume of the discharge channel increases due to the bending deformation due to the piezoelectric thickness slip effect on the pair of drive walls. Then, as the volume of the ejection channel increases, the ink 9 is guided into the ejection channel.

Then, the ink 9 thus guided into the ejection channel becomes a pressure wave and propagates inside the ejection channel. Then, at the timing when the pressure wave reaches the nozzle hole Hn of the nozzle plate 112, the drive voltage Vd applied to the drive electrode becomes 0 (zero) V. As a result, the drive wall is restored from the above-mentioned bending deformation state, and as a result, the once increased volume of the discharge channel is restored to the original volume.

In this way, in the process of returning the volume of the ejection channel to the original volume, the pressure inside the ejection channel increases, and the ink 9 in the ejection channel is pressurized. As a result, the droplet-shaped ink 9 is ejected to the outside (toward the recording medium) through the nozzle hole Hn (see FIGS. 1 and 2). In this way, the ink jet head 1 ejects the ink 9 (ejection operation), and as a result, the recording operation of images, characters, etc. on the recording medium is performed.

(B. Data transfer operation)
Next, with reference to FIGS. 3 to 7 in addition to FIGS. 1 and 2, data transfer between the head control unit 2 and the drive circuit unit 12a and between the drive circuit units 12a, 12b, and 12c. The operation will be described in detail while comparing with the comparative examples (FIGS. 3 and 4).

(B-1. Comparative example)
FIG. 3 is a block diagram showing a configuration example of each drive circuit unit 102a, 102b, 102c in the liquid injection head (inkjet head 101) according to the comparative example. Further, FIG. 4 schematically shows an operation example (data transfer operation example) of the inkjet head 101 of the comparative example in a timing diagram.

In the inkjet head 101 of this comparative example, as in the inkjet head 1 of the present embodiment shown in FIG. 1, a plurality of drive circuit units 102a, 102b, 102c are connected in series to each other in multiple stages (cascade). It is assumed that it is connected).

Here, in FIG. 4, (A) shows the clock signal CLK, (C) shows the latch signal LATCH, (D) shows the firing signal FIRE, and (E) shows the strobe signal STB. Further, in FIG. 4, (B), (F), and (G) indicate the 4-bit parallel pixel data signal PDp [3: 0] input to the drive circuit units 102a, 102b, and 102c, respectively. There is. Further, the horizontal axis in FIG. 4 indicates the time t, and the same applies to the subsequent timing diagrams.

In addition, in FIG. 4 (B), FIG. 4 (F), and FIG. 4 (G), "n", "a", "b" in "Dn_a_b" shown in the parallel pixel data signal PDp [3: 0]. "" Means the following numbers, respectively. Further, "N / A" means a missing value (Not Available). These meanings are basically the same in the subsequent timing diagrams.
"N": Bit number "a" in the parallel pixel data signal PDp: Nozzle hole Hn number "b": Multiple drive circuit units connected in cascade (three drive circuit units 12a, 12b, 12c in this example). Number in

The drive circuit units 102a, 102b, 102c in the inkjet head 101 correspond to the drive circuit units 12a, 12b, 12c (see FIG. 2) described above in the inkjet head 1 as follows. That is, as shown in FIG. 3, the drive circuit units 102a, 102b, 102c are not provided with the serial / parallel conversion unit 121 and the parallel / serial conversion unit 123 in the drive circuit units 12a, 12b, 12c. It corresponds to what was (omitted), and the other configurations are basically the same.

Further, since the serial / parallel conversion unit 121 and the parallel / serial conversion unit 123 are not provided, the 4-bit parallel pixel data signal PDp is input and output in each drive circuit unit 102a, 102b, 102c. (See Fig. 3). In each drive circuit unit 102a, 102b, 102c, the clock signal CLK, the strobe signal STB, the latch signal LATCH, and the firing signal FIRE are also input and output in parallel with the parallel pixel data signal PDp (FIG. 3). reference).

In the data transfer operation of the comparative example shown in FIG. 4, the shift clock (logical product signal Scom) is applied to each D-FF circuit 41 only during the period of strobe signal STB = "1" (period from timing t101 to t104). Is entered. Therefore, this period is the valid period of the data input (input of the parallel pixel data signal PDp) to the shift register unit 122A (see FIGS. 4 (B), 4 (F), and 4 (G)).

In this period, first, in the drive circuit unit 102a in the front stage, the parallel pixel data signal PDp corresponding to each nozzle hole Hn1 to Hn5 for the three drive circuit units 102a, 102b, 102c is transmitted to the shift register unit 122A. It is input sequentially (see FIG. 4 (B)). Next, in the shift register unit 122A, the parallel pixel data signal PDp that is sequentially transferred and held is the latch circuit unit 122B at the timing (timing t105) when the latch signal LATCH changes from “0” to “1”. It is held by each of the latch circuits 42 (see FIG. 4C). Subsequently, at the timing (timing t106) when the firing signal FIRE changes from "0" to "1", each waveform generation circuit 43 in the waveform generation circuit unit 125C is a parallel pixel held in each latch circuit 42. Based on the data signal PDp, the generation of the waveform signal that is the basis of the drive signal Sd is started (see FIG. 4D). Then, the level conversion circuit 122D generates a drive signal Sd corresponding to each nozzle hole Hn based on each such waveform signal, and the above-mentioned drive wall is driven based on the drive signal Sd (result). For example, the ink 9 is ejected from each nozzle hole Hn) (see FIG. 3).

Further, at this time, the 4-bit parallel pixel data signal PDp output from the D-FF circuit 41 at the last stage of the shift register unit 122A in the drive circuit unit 102a is the drive circuit unit 102b at the subsequent stage of the drive circuit unit 102a. Is output to (see Fig. 3). Similarly, the 4-bit parallel pixel data signal PDp output from the D-FF circuit 41 at the last stage of the shift register unit 122A in the drive circuit unit 102b is driven by the subsequent stage (last stage) of the drive circuit unit 102b. It is output to the circuit unit 102c (see FIG. 3). At this time, the parallel pixel data signals PDp for each drive circuit unit 102a, 102b, 102c are sequentially transferred from the drive circuit unit 102a to the drive circuit units 102b, 102c while sequentially shifting (FIG. 4). (B), FIG. 4 (F), FIG. 4 (G)).

In this way, in the inkjet head 101 of the comparative example, the input signal and the output signal in each drive circuit unit 102a, 102b, 102c are configured by using the parallel data signal including the parallel pixel data signal PDp. Therefore, in this comparative example, the number of signals (the number of signal lines) between the head control unit 2 and the drive circuit unit 102a and between the drive circuit units 102a, 102b, 102c increases. (The number of signal lines will increase). As a result of the increase in the number of signal lines in this way, in this comparative example, the size of the inkjet head 101 is increased, the skew between signals is increased, and the degree of freedom in design of the inkjet head 101 is reduced. There is a risk.

(B-2. Embodiment of this present)
On the other hand, as shown in FIG. 2, each drive circuit unit 12a, 12b, 12c of the present embodiment is provided with a serial / parallel conversion unit 121 and a parallel / serial conversion unit 123, respectively. .. Then, in each drive circuit unit 12a, 12b, 12c and the entire inkjet head 1, the data transfer operation is performed as follows.

FIG. 5 schematically shows an operation example (data transfer operation example) in each of the drive circuit units 12a, 12b, and 12c shown in FIG. 2, in a timing diagram, and FIG. 6 is shown in FIG. A part of the operation example is enlarged and schematically shown in a timing diagram. Further, FIG. 7 schematically shows the data transfer operation of the entire inkjet head 1 shown in FIG. 1 in a timing diagram. In addition, in these FIGS. 5 to 7, one cycle of the clock signal CLK is shown as the cycle T, and the same applies to the subsequent timing diagrams.

Here, in FIGS. 5 and 6, (A), (B), and (C) are clock signals CLK input to the respective drive circuit units 12a, 12b, and 12c (serial / parallel conversion unit 121 in), respectively. , And the 7-bit parallel data (including the 4-bit parallel pixel data signal PDp [3: 0]) after the serial data signal Ds is serially / parallel-converted.

On the other hand, in FIG. 5, (D), (E), and (F) are clock signal CLK and serial data signal output from each drive circuit unit 12a, 12b, 12c (parallel / serial conversion unit 123 in), respectively. Ds and 7-bit parallel data (including 4-bit parallel pixel data signal PDp [3: 0]) before parallel / serial conversion are shown.

Further, in FIG. 7, (A) indicates a clock signal CLK, and (B) to (E), (F) to (I), and (J) to (M) are drive circuit units 12a and 12b, respectively. , 7-bit parallel data (including 4-bit parallel pixel data signal PDp [3: 0]) in 12c are shown respectively. Specifically, (B), (F), and (J) are 4-bit parallel pixel data signals PDp [3: 0], respectively, and (C), (G), and (K) are latch signals, respectively. LATCH is shown. Further, (D), (H), and (L) each indicate a firing signal FIRE, and (E), (I), and (M) each indicate a strobe signal STB.

In FIG. 7, for convenience, the contents of each bit in the 4-bit parallel pixel data signal PDp [3: 0] are summarized and the symbols are simplified to "Dab" instead of "Dn_a_b" in the above definition. It is shown as.

The data transfer operation of the present embodiment is as follows in each drive circuit unit 12a, 12b, 12c, for example, as shown in FIGS. 5 and 6. That is, first, the serial data signal Ds includes 7 bits of serial data within the period (1 clock period) of the period T in synchronization with the clock signal CLK (FIGS. 5 (A) and 5 (FIG. 5)). B), FIG. 6 (A), FIG. 6 (B)). The serial data signal Ds is serially / parallel-converted by the serial / parallel conversion unit 121, so that the 4-bit parallel pixel data signal PDp [3: 0], the latch signal LATCH, the firing signal FIRE, and the strobe A signal STB and a signal STB are generated, respectively (see the dashed arrow in FIG. 6). In this example, as shown in FIG. 6, the four bits from the beginning of the serial data signal Ds are the serial pixel data signals PDs, followed by the latch signal LATCH, the firing signal FIRE, and the strobe signal. They are arranged in the order of STB.

Here, only during the period of the strobe signal STB = "1" (period from timing t11 to t16) generated in this way, the shift clock (logical product signal Scom) is applied to each D-FF circuit 41 in the shift register unit 122A. ) Is entered. Therefore, this period is the valid period of the data input (input of the parallel pixel data signal PDp) to the shift register unit 122A (see FIGS. 5 (C) and 6 (C)).

During this period, first, the parallel pixel data signals PDp corresponding to the nozzle holes Hn1 to Hn5 are sequentially input to the shift register unit 122A. Next, in the shift register unit 122A, the parallel pixel data signal PDp that is sequentially transferred and held is the latch circuit unit 122B at the timing (timing t17) when the latch signal LATCH changes from “0” to “1”. It is held by each of the latch circuits 42 (see FIG. 5C). Subsequently, at the timing (timing t19) when the firing signal FIRE changes from "0" to "1", each waveform generation circuit 43 in the waveform generation circuit unit 122C is a parallel pixel held in each latch circuit 42. Based on the data signal PDp, the generation of the waveform signal that is the basis of the drive signal Sd is started (see FIG. 5C). Then, the level conversion circuit 122D generates a drive signal Sd corresponding to each nozzle hole Hn based on each such waveform signal, and the above-mentioned drive wall is driven based on the drive signal Sd (result). For example, the ink 9 is ejected from each nozzle hole Hn) (see timings t19 to t20 in FIGS. 1, 2, and 5).

At this time, the 4-bit parallel pixel data signal PDp [3: 0] output from the D-FF circuit 41 at the last stage of the shift register unit 122A is subjected to parallel / serial conversion in the parallel / serial conversion unit 123. Will be done. Specifically, the parallel / serial conversion is performed based on the 4-bit parallel pixel data signal PDp [3: 0], the latch signal LATCH, the firing signal FIRE, and the strobe signal STB. The serial data signals Ds are regenerated (see FIGS. 5 (D) to 5 (F)). Then, the serial data signal Ds regenerated in this way is output from the parallel / serial conversion unit 123 to the outside of each drive circuit unit 12a, 12b, 12c together with the clock signal CLK (FIG. 5D). , See FIG. 5 (E)). At the timings t16 to 23 at "PDp [3: 0]" (IN) in FIG. 5C, since the strobe signal STB = "0", the above-mentioned sequential transfer is not performed. Therefore, as shown in the timings t18 to t23 at “PDp [3: 0]” (OUT) in FIG. 5 (F), the parallel pixel data signal PDp [3: 0] remains “Dn_1” and does not change. It has become like.

At this time, for example, as shown by the broken line arrows P10 and P11 in FIG. 5, a period of seven cycles T from data input to data output in each drive circuit unit 12a, 12b, 12c. Each data shifts sequentially for minutes (7 cycles). Specifically, the parallel pixel data signal PDp included in the serial data signal Ds input in the period up to the timing t11 is included in the serial data signal Ds and output in the period from the timing t13 to t18. (See the dashed arrow P10). Similarly, the parallel pixel data signal PDp included in the serial data signal Ds input in the period from timing t11 to t16 will be included in the serial data signal Ds and output in the period from timing t18 to t23. (See the dashed arrow P11).

Further, for example, as shown in FIG. 7, the data transfer operation in the entire inkjet head 1 is as follows. That is, first, the 4-bit parallel pixel data signal PDp in the drive circuit unit 12a becomes the serial data signal Ds as described above, and is output to the drive circuit unit 12b in the subsequent stage of the drive circuit unit 12a. (See arrows P21 to P23 in FIG. 7). Similarly, the 4-bit parallel pixel data signal PDp in the drive circuit unit 12b becomes the serial data signal Ds as described above, and goes to the drive circuit unit 12c in the subsequent stage (last stage) of the drive circuit unit 12b. Is output (see arrows P31 to P33 in FIG. 7). Also in FIG. 7, during the period when the strobe signal STB = "0", the above-mentioned sequential transfer is not performed, and the parallel pixel data signal PDp [3: 0] remains "D_5-1" or "D_5-2". , It is designed not to change.

At this time, the parallel pixel data signals PDp for each drive circuit unit 12a, 12b, 12c are sequentially transferred from the drive circuit unit 12a to the drive circuit units 12b, 12c while sequentially shifting. (See arrows P21 to P23 and P31 to P33 in FIG. 7).

(B-3. Action / effect)
In this way, in the inkjet head 1 of the present embodiment, the serial data signal Ds (including the serial pixel data signal PDs for each of the plurality of nozzle holes Hn) and the clock signal CLK supplied from the outside (head control unit 2). Based on the above, parallel pixel data signals PDp for each of a plurality of nozzle holes Hn are generated in each drive circuit unit 12a, 12b, 12c. Further, in each drive circuit unit 12a, 12b, 12c, a drive signal Sd for each of a plurality of nozzle holes Hn is generated based on the parallel pixel data signal PDp or the like. Then, in each drive circuit unit 12a, 12b, 12c, the serial data signal Ds is regenerated based on such a parallel pixel data signal PDp or the like, and together with the clock signal CLK, each drive circuit unit 12a, 12b, 12c It is output to the outside of.

In this way, in the inkjet head 1, the input signal and the output signal in each of the drive circuit units 12a, 12b, and 12c are configured to include the serial data signal Ds and the clock signal CLK, respectively. Therefore, in this inkjet head 1, for example, an inkjet of the above comparative example in which an input signal and an output signal in each drive circuit unit 102a, 102b, 102b are configured by using a parallel data signal including a parallel pixel data signal PDp. Compared with the head 101, it is as follows. That is, since serial data transfer is performed in the present embodiment, the number of signals (number of signal lines) between the head control unit 2 and the drive circuit unit 12a and between the drive circuit units 12a, 12b, and 12c. However, compared to the above comparative example (parallel data transfer), the number can be reduced (the number of signal lines can be reduced).

As described above, in the inkjet head 1 of the present embodiment, the number of signal lines can be reduced, and as a result, the size of the inkjet head 1 is reduced and the skew between signals is reduced as compared with the above comparative example. It is possible to improve the degree of freedom in designing the inkjet head 1 and the like. Specifically, since the degree of freedom in design is increased, for example, it is possible to expand the number of nozzles (the number of nozzle holes Hn) without changing the hardware in the printer 3. Further, for example, it is possible to perform high-speed data transfer while using a low-speed clock signal CLK.

Further, in the present embodiment, the serial data signal Ds and the clock signal CLK output from the parallel / serial conversion unit 123 in the drive circuit unit located relatively on the front stage side are respectively located on the rear stage side relatively. By inputting data to the serial / parallel conversion unit 121 in the drive circuit unit, the plurality of drive circuit units 12a, 12b, and 12c are connected in series to each other in multiple stages (cascade connection). In this way, the signal connection as described above is performed between the drive circuit units on the front stage side and the rear stage side, so that the following is achieved. That is, it is possible to easily realize a cascade connection between a plurality of drive circuit units 12a, 12b, 12c, and it is also possible to easily increase the number of stages of the cascade connection.

Further, in the present embodiment, the latch signal LATCH, the firing signal FIRE, and the strobe signal STB are each further included (multiplexed) in the serial data signal Ds, so that the result is as follows. .. That is, the input signal and the output signal in each drive circuit unit 12a, 12b, 12c are composed of only the serial data signal Ds and the clock signal CLK, respectively. Therefore, the number of signals (number of signal lines) between the head control unit 2 and the drive circuit unit 12a and between the drive circuit units 12a, 12b, and 12c can be further reduced (the number of signal lines). The number can be further reduced). Therefore, it is possible to further reduce the size of the inkjet head 1, further reduce the skew between signals, and further improve the degree of freedom in designing the inkjet head 1.

In addition, in the present embodiment, since a single serial data signal Ds is used, the number of serial data signals Ds (the number of signal lines) can be one. Therefore, it is possible to further reduce the size of the inkjet head 1, further reduce the skew between signals, and further improve the degree of freedom in designing the inkjet head 1.

Further, in the present embodiment, the parallel pixel data signal PDp is sequentially transferred in the shift register unit 122A in synchronization with the logical product signal Scom of the strobe signal STB and the clock signal CLK. become. That is, it is no longer necessary to specify the clock signal CLK as an intermittent signal, and a continuous signal can be obtained. Therefore, based on such a continuous clock signal CLK, it is possible to perform serial / parallel conversion in the serial / parallel conversion unit 121 to generate a parallel pixel data signal PDp. Further, for example, in the serial / parallel conversion unit 121, by multiplying this continuous clock signal CLK, the speed is increased so that a plurality of bits (for example, 7 bits) are included in one clock period (period T). It becomes possible to process the generated serial data signal Ds.

Further, in the present embodiment, it is possible to reduce the circuit scale around the serial / parallel conversion unit 121 and the parallel / serial conversion unit 123 as compared with the case of the data transfer method by the so-called "8B / 10B method". Become.

<2. Modification example>
Subsequently, modification examples (modification examples 1 to 4) of the above-described embodiment will be described. The liquid injection heads according to the modified examples 1 to 4 may also be provided in the liquid injection recording device (printer) in the same manner as in the above embodiment. Further, in the following, the same components as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

[Modification 1]
FIG. 8 is a block diagram showing a configuration example of each drive circuit unit 13a, 13b, 13c in the liquid injection head (inkjet head 1A) according to the modification 1. Also in the inkjet head 1A of this modification 1, the plurality of drive circuit units 13a, 13b, 13c are connected in series to each other in multiple stages, as in the inkjet head 1 of the embodiment shown in FIG. It is assumed that they are connected (cascade connection). That is, it is assumed that the number of stages of cascade connection between the drive circuit units 13a, 13b, and 13c in the inkjet head 1A is three.

The drive circuit units 13a, 13b, 13c in the inkjet head 1A correspond to the above-mentioned drive circuit units 12a, 12b, 12c (see FIG. 2) in the inkjet head 1 as follows. That is, as shown in FIG. 8, each drive circuit unit 13a, 13b, 13c is serialized in each drive circuit unit 12a, 12b, 12c instead of the serial / parallel conversion unit 121 and the parallel / serial conversion unit 123. The / parallel conversion unit 121A and the parallel / serial conversion unit 123A are provided, and the demultiplexer 124A is further provided. The other configurations are basically the same.

The inkjet head 1A corresponds to a specific example of the "liquid injection head" in the present disclosure.

(Serial / Parallel Converter 121A)
Similar to the serial / parallel conversion unit 121, the serial / parallel conversion unit 121A has a serial data signal Ds including m-bit (4 bits in this example) serial pixel data signal PDs and a clock signal CLK. Based on this, it is a circuit that performs a predetermined serial / parallel conversion. By such serial / parallel conversion, as shown in FIG. 8, an m-bit (4 bits in this example) parallel pixel data signal PDp (PDp [3: 0]) is generated.

However, unlike the serial / parallel conversion unit 121, the serial / parallel conversion unit 121A generates the following signals by performing such serial / parallel conversion. That is, as shown in FIG. 8, the serial / parallel conversion unit 121A generates a strobe signal STB and a latch / firing signal LATCH / FIRE, respectively, together with the 4-bit parallel pixel data signal PDp described above. There is. The latch / firing signal LATCH / FIRE, which will be described in detail later (see FIG. 9), is a single composite signal in which the latch signal LATCH and the firing signal FIRE are individually defined. The clock signal CLK is also output from the serial / parallel conversion unit 121A (see FIG. 8).

Here, such a latch / firing signal LATCH / FIRE corresponds to a specific example of the "single composite signal" in the present disclosure.

(Parallel / serial conversion unit 123A)
Similar to the parallel / serial conversion unit 123, the parallel / serial conversion unit 123A performs a predetermined parallel / serial conversion based on the parallel pixel data signal PDp of m bits (4 bits in this example) and the clock signal CLK. It is a circuit to perform. By such parallel / serial conversion, as shown in FIG. 8, the above-mentioned serial data signal Ds is generated (regenerated), and the serial data signal Ds and the clock signal CLK are generated by the respective drive circuit units 13a, respectively. It is designed to be output to the outside of 13b and 13c.

However, unlike the parallel / serial conversion unit 123, the parallel / serial conversion unit 123A performs parallel / serial conversion specifically as follows. That is, the parallel / serial conversion unit 123A uses the 4-bit parallel pixel data signal PDp output from the shift register unit 122A, the clock signal CLK, the strobe signal STB, and the latch / firing signal LATCH / FIRE described above. Based on this, parallel / serial conversion is performed (see FIG. 8).

Further, the serial data signal Ds and the clock signal CLK output from the parallel / serial conversion unit 123A in the drive circuit unit located relatively on the front stage side are serial in the drive circuit unit relatively located on the rear stage side, respectively. / It is designed to be input to the parallel conversion unit 121A (see FIG. 8).

(Demultiplexer 124A)
The demultiplexer 124A is a circuit that demultiplexes (separates) the latch / firing signal LATCH / FIRE, which is the single combined signal described above, into the latch signal LATCH and the firing signal FIRE. The latch signal LATCH and the firing signal FIRE generated in this way are connected to the latch circuit unit 122B and the waveform generation circuit unit 122C, respectively, in the same manner as the drive circuit units 12a, 12b, 12c (see FIG. 2). It is designed to be output (see FIG. 8).

Here, FIG. 9 schematically shows an operation example of the demultiplexer 124A (an example of the above-mentioned demultiplexing operation) in a timing diagram.

First, in the example shown in FIG. 9A, in the latch / firing signal LATCH / FIRE, the latch signal LATCH and the firing signal FIRE are individually defined as follows. That is, the latch signal LATCH and the firing signal FIRE are individually defined by using the rising timing in the latch / firing signal LATCH / FIRE and the timing after a predetermined time Δt has elapsed from this rising timing. .. Therefore, the duplexer 124A is adapted to demultiplex the latch / firing signal LATCH / FIRE into the latch signal LATCH and the firing signal FIRE by utilizing such a timing difference.

On the other hand, in the example shown in FIG. 9B, in the latch / firing signal LATCH / FIRE, the latch signal LATCH and the firing signal FIRE are individually defined as follows. That is, the latch signal LATCH and the firing signal FIRE are individually defined by using the rising timing and the falling timing in the latch / firing signal LATCH / FIRE. Therefore, the duplexer 124A is adapted to demultiplex the latch / firing signal LATCH / FIRE into the latch signal LATCH and the firing signal FIRE by utilizing such a timing difference.

(Action / effect)
Even in the modified example 1 having such a configuration, it is possible to obtain the same effect by basically the same operation as that of the embodiment.

Further, in particular, in this modification 1, two types of control signals (latch signal LATCH and firing signal FIRE) can be integrated into a single composite signal (latch / firing signal LATCH / FIRE) and specified. Therefore, for example, the following effects can be obtained. That is, the number of control signals can be reduced, and the overhead of control signals can be reduced.

[Modification 2]
FIG. 10 is a block diagram showing a configuration example of each drive circuit unit 14a, 14b, 14c in the liquid injection head (inkjet head 1B) according to the modification 2. Even in the inkjet head 1B of the modification 1, the plurality of drive circuit units 14a, 14b, 14c are connected in series to each other in multiple stages, as in the inkjet head 1 of the embodiment shown in FIG. It is assumed that they are connected (cascade connection). That is, it is assumed that the number of stages of cascade connection between the drive circuit units 14a, 14b, 14c in the inkjet head 1B is three.

The drive circuit units 14a, 14b, 14c in the inkjet head 1B correspond to the above-mentioned drive circuit units 12a, 12b, 12c (see FIG. 2) in the inkjet head 1 as follows. That is, as shown in FIG. 10, each drive circuit unit 14a, 14b, 14c is serialized in each drive circuit unit 12a, 12b, 12c instead of the serial / parallel conversion unit 121 and the parallel / serial conversion unit 123. It corresponds to the one provided with the / parallel conversion unit 121B and the parallel / serial conversion unit 123B, and the other configurations are basically the same.

The inkjet head 1B corresponds to a specific example of the "liquid injection head" in the present disclosure.

(Serial / Parallel Converter 121B)
Similar to the serial / parallel conversion unit 121 (see FIG. 2) of the embodiment, the serial / parallel conversion unit 121B performs a predetermined serial / parallel conversion based on various signals supplied from the external head control unit 2. It is a circuit to perform. By such serial / parallel conversion, as shown in FIG. 10, an m-bit (4 bits in this example) parallel pixel data signal PDp (PDp [3: 0]) is generated.

However, unlike the serial / parallel conversion unit 121, the serial / parallel conversion unit 121B performs serial / parallel conversion as follows. That is, as shown in FIG. 10, the serial / parallel conversion unit 121B includes a serial data signal Ds including serial pixel data signal PDs, a clock signal CLK, a strobe signal STB, a latch signal LATCH, and the like. Serial / parallel conversion is performed based on the firing signal FIRE. The clock signal CLK, strobe signal STB, latch signal LATCH, and firing signal FIRE are also output from the serial / parallel conversion unit 121B (see FIG. 10).

(Parallel / serial conversion unit 123B)
Similar to the parallel / serial conversion unit 123, the parallel / serial conversion unit 123B performs a predetermined parallel / serial conversion based on the parallel pixel data signal PDp of m bits (4 bits in this example) and the clock signal CLK. It is a circuit to perform. Specifically, the parallel / serial conversion unit 123B includes a 4-bit parallel pixel data signal PDp output from the shift register unit 122A, a clock signal CLK, a strobe signal STB, a latch signal LATCH, and a firing signal. Parallel / serial conversion is performed based on the FIRE (see FIG. 10).

By such parallel / serial conversion, as shown in FIG. 10, the above-mentioned serial data signal Ds is generated (regenerated). Then, the serial data signal Ds, the clock signal CLK, the strobe signal STB, the latch signal LATCH, and the firing signal FIRE are output to the outside of each drive circuit unit 14a, 14b, 14c, respectively. It has become.

Further, the serial data signal Ds, the clock signal CLK, the strobe signal STB, the latch signal LATCH, and the firing signal FIRE output from the parallel / serial conversion unit 123B in the drive circuit unit located relatively on the front stage side are relative to each other. It is designed to be input to the serial / parallel conversion unit 121B in the drive circuit unit located on the rear stage side (see FIG. 10).

As described above, unlike the embodiments and the first modification described so far, the serial pixel data signals PDs and other signals (control signals such as strobe signal STB, latch signal LATCH and firing signal FIRE) are used. It may not be multiplexed. In other words, these other signals may not be included in the serial data signal Ds.

Even in the modified example 2 having such a configuration, it is possible to obtain the same effect by basically the same operation as that of the embodiment.

Also in this modification 2, as in the modification 1 described above, two types of control signals (latch signal LATCH and firing signal FIRE) are combined with each other as a single composite signal (latch / firing signal LATCH / FIRE). ) May be integrated and specified (see FIG. 9).

[Modification 3]
(A. Configuration)
FIG. 11 is a block diagram showing a configuration example of each drive circuit unit 15a, 15b, 15c in the liquid injection head (inkjet head 1C) according to the modification 3. Further, FIG. 12 schematically shows a configuration example of grouping of a plurality of nozzles (10 nozzle holes Hn1 to Hn10 described later) according to the modified example 3.

Even in the inkjet head 1C of the modification 3, the plurality of drive circuit units 15a, 15b, and 15c are connected in series to each other in multiple stages, as in the inkjet head 1 of the embodiment shown in FIG. It is assumed that they are connected (cascade connection). That is, it is assumed that the number of stages of cascade connection between the drive circuit units 15a, 15b, and 15c in the inkjet head 1C is three.

Here, the inkjet head 1C corresponds to a specific example of the "liquid injection head" in the present disclosure.

As shown in FIG. 11, the inkjet head 1C includes injection units 11a, 11b, 11c and drive circuit units 15a, 15b, 15c.

It is assumed that the injection portions 11a, 11b, 11c of the modified example 3 are provided with 10 nozzle holes Hn1 to Hn10 as an example (see FIG. 11). Each of these nozzle holes Hn1 to Hn10 (plurality of nozzle holes Hn) corresponds to a specific example of the "nozzle" in the present disclosure.

As shown in FIG. 11, each of the drive circuit units 15a, 15b, and 15c has a serial / parallel conversion unit 121C, a drive signal generation unit 125, a parallel / serial conversion unit 123C, and a duplexer 124C, respectively.

(Serial / Parallel Converter 121C)
Unlike the serial / parallel conversion units 121, 121A, 121B described so far, the serial / parallel conversion unit 121C is based on a plurality of (two in this example) serial data signals Ds1 and Ds2 and a clock signal CLK. , Predetermined serial / parallel conversion is performed. That is, in this modification 3, the head control unit 2 (see FIG. 1) has two serial data signals Ds1 and Ds2 and 1 with respect to the drive circuit unit 15a (the drive circuit unit in the front stage) in the inkjet head 1C. One clock signal CLK is supplied respectively.

By such serial / parallel conversion, although details will be described later, two parallel pixel data signals PDp1 and PDp2 (PDp1 [5: 0], PDp2 [5: 0]) of m bits (6 bits in this example) , The strobe signal STB and the above-mentioned latch / firing signal LATCH / FIRE are generated respectively (see FIG. 11). The clock signal CLK is also output from the serial / parallel conversion unit 121C (see FIG. 11).

Here, these serial data signals Ds1 and Ds2 and the clock signal CLK are also transmitted by LVDS (low voltage differential signal), for example, as described above. Further, the serial data signals Ds1 and Ds2 and the clock signal CLK are each transmitted by one signal line as shown in FIG. Further, the serial data signals Ds1 and Ds2 are each synchronized with the clock signal CLK, and include 7 bits of data within one clock period (period of period T). However, the data is not limited to 7 bits, and may be a plurality of bits of data other than 7 bits. As will be described in detail later, the serial pixel data signals PDs1 and PDs2 corresponding to the two nozzle holes Hn in the inkjet head 1C are transmitted every one clock period.

Further, in the modification 3, the details of the serial data signals Ds1 and Ds2 will be described later (see FIG. 13), but the m-bit (6 bits in this example) serial pixel data signals PDs and other signals are used. Is multiplexed. Specifically, the latch signal LATCH, the firing signal FIRE, and the strobe signal STB are included in any one of these two serial data signals Ds1 and Ds2, respectively.

It should be noted that such two serial data signals Ds1 and Ds2 correspond to a specific example of "n serial data signals (n: integers of 2 or more)" in the present disclosure.

Here, for example, as shown in FIG. 12, in the modified example 3, a plurality of nozzle holes Hn (10 nozzle holes Hn1 to Hn10) in the inkjet head 1C are grouped as follows. That is, in this example, the 10 nozzle holes Hn1 to Hn10 are grouped so as to belong to any one of the two nozzle groups Gp1 and Gp2. Specifically, in the example shown in FIG. 12, the even-numbered nozzle holes Hn2, Hn4, Hn6, Hn8, and Hn10 belong to the nozzle group Gp1. On the other hand, nozzle holes Hn1, Hn3, Hn5, Hn7, and Hn9 located at odd-numbered positions belong to the nozzle group Gp2.

The two serial data signals Ds1 and Ds2 described above include serial pixel data signals corresponding to the nozzle holes Hn belonging to one of the two nozzle groups Gp1 and Gp2, respectively. It is configured. Specifically, as shown in FIG. 12, the serial data signal Ds1 includes the serial pixel data signal PDs1 corresponding to the nozzle holes Hn2, Hn4, Hn6, Hn8, Hn10 belonging to the nozzle group Gp1. (See the dashed arrow P41). On the other hand, as shown in FIG. 12, the serial data signal Ds2 includes the serial pixel data signal PDs2 corresponding to the nozzle holes Hn1, Hn3, Hn5, Hn7, Hn9 belonging to the nozzle group Gp2 ( See the broken arrow P42). The method of distributing the nozzle group and the nozzle hole Hn for each serial data signal Ds1 and Ds2 is not limited to the example shown in FIG. 12, and the nozzle group and the nozzle hole Hn are distributed by using another method. May be done.

(Demultiplexer 124C)
The demultiplexer 124C is a circuit that demultiplexes the latch / firing signal LATCH / FIRE, which is a single composite signal, into the latch signal LATCH and the firing signal FIRE, similarly to the demultiplexer 124A described above. In particular, the demultiplexer 124C is configured by using a logic negative circuit (NOT circuit) 45 as shown in FIG. Specifically, the logical negative signal (inverted signal) of the latch / firing signal LATCH / FIRE is generated as the firing signal FIRE, and the latch / firing signal LATCH / FIRE is output as it is as the latch signal LATCH. It has become so.

The latch signal LATCH and the firing signal FIRE generated in this way are output to the latch circuit unit 125B and the waveform generation circuit unit 125C, respectively (see FIG. 11).

(Drive signal generator 125)
The drive signal generation unit 125 includes a shift register unit 125A, a latch circuit unit 125B, a waveform generation circuit unit 125C, a level conversion circuit 125D, and a logical product circuit 40.

The shift register unit 125A is a circuit that sequentially transfers and holds the two parallel pixel data signals PDp1 and PDp2 described above from the front stage side to the rear stage side corresponding to the drive signals Sd for each of the plurality of nozzle holes Hn. (See FIG. 11). The shift register unit 125A has a D-FF circuit 41 having the same number (10 in this example) as the number of the plurality of nozzle holes Hn. Each D-FF circuit 41 can hold a 6-bit parallel pixel data signal PDp1 or a 6-bit parallel pixel data signal PDp2.

As shown in FIG. 11, each D-FF circuit 41 has a logical product generated by the logical product circuit 40 as a shift clock for sequential transfer, as in the embodiment (see FIG. 2). The signal Scom is input. In other words, the shift register unit 125A sequentially transfers the parallel pixel data signals PDp1 and PDp2 described above in synchronization with the AND signal Scom.

The latch circuit unit 125B synchronizes the 6-bit parallel pixel data signals PDp1 and PDp2 for each of the plurality of nozzle holes Hn output from each D-FF circuit 41 in the shift register unit 125A with the latch signal LATCH, respectively. It is a holding circuit (see FIG. 11). The latch circuit unit 125B has a latch circuit 42 having the same number (10 in this example) as the number of the plurality of nozzle holes Hn. Each latch circuit 42 can hold a 6-bit parallel pixel data signal PDp1 or a 6-bit parallel pixel data signal PDp2.

The waveform generation circuit unit 125C serves as a base for the drive signal Sd based on the 6-bit parallel pixel data signals PDp1 and PDp2 for each of the plurality of nozzle holes Hn output from each latch circuit 42 in the latch circuit unit 125B. It is a circuit that generates a waveform signal (see FIG. 11). The waveform generation circuit unit 125C has the same number of waveform generation circuits 43 as the number of the plurality of nozzle holes Hn (10 in this example), and each waveform generation circuit 43 synchronizes with the firing signal FIRE. Therefore, such a waveform signal is generated.

The level conversion circuit 125D is a circuit that generates a drive signal Sd for each of the plurality of nozzle holes Hn based on the waveform signals for each of the plurality of nozzle holes Hn output from each waveform generation circuit 43 in the waveform generation circuit unit 125C. (See FIG. 11). Specifically, the level conversion circuit 125D converts the level (voltage value) of each waveform signal to generate a drive signal Sd having a drive voltage Vd corresponding to each nozzle hole Hn (nozzle holes Hn1 to Hn10). , Each is designed to be generated.

(Parallel / serial conversion unit 123C)
Unlike the parallel / serial conversion units 123, 123A, 123B described above, the parallel / serial conversion unit 123C has a predetermined parallel / serial conversion based on the two serial data signals Ds1 and Ds2 and the clock signal CLK. It is a circuit that performs. Specifically, the parallel / serial conversion unit 123C has 6-bit parallel pixel data signals PDp1 and PDp2 output from the shift register unit 125A, a clock signal CLK, a strobe signal STB, and a latch / firing signal LATCH. Parallel / serial conversion is performed based on / FIRE (see FIG. 11).

By such parallel / serial conversion, as shown in FIG. 11, the two serial data signals Ds1 and Ds2 described above are generated (regenerated), respectively, and together with the clock signal CLK, the drive circuit units 15a, 15b, and 15c are generated. It is designed to be output to the outside of.

Further, the serial data signals Ds1 and Ds2 and the clock signal CLK output from the parallel / serial conversion unit 123C in the drive circuit unit relatively located on the front stage side are respectively in the drive circuit unit relatively located on the rear stage side. , Is input to the serial / parallel conversion unit 121C (see FIG. 11).

(B. Data transfer operation)
Here, FIG. 13 schematically shows an operation example (data transfer operation example) in each of the drive circuit units 15a, 15b, and 15c shown in FIG. 11 in a timing diagram.

In FIG. 13, (A), (B), and (C) are clock signal CLK and serial data signal Ds1 input to each drive circuit unit 15a, 15b, 15c (serial / parallel conversion unit 121C in), respectively. And the serial data signal Ds2 are shown. Further, in (D) and (E), 7-bit parallel data (6-bit parallel pixel data signal PDp1 [5: 0], PDp2) after these serial data signals Ds1 and Ds2 are serially / parallel-converted, respectively. (Including [5: 0] respectively) is shown.

On the other hand, in FIG. 13, (F), (G), and (H) are clock signals CLK and serial data signals output from the drive circuit units 15a, 15b, and 15c (parallel / serial conversion units 123C in each), respectively. The Ds1 and the serial data signal Ds2 are shown. Further, (I) and (J) each include 7-bit parallel data (including 6-bit parallel pixel data signals PDp1 [5: 0] and PDp2 [5: 0]) before parallel / serial conversion. Shows.

As shown in FIG. 13, for example, the data transfer operation of the modification 3 is as follows in each drive circuit unit 15a, 15b, 15c. That is, first, the serial data signals Ds1 and Ds2 each include 7 bits of serial data within the period (1 clock period) of the period T in synchronization with the clock signal CLK (FIGS. 13A to 13A). See FIG. 13 (C). Of these, the serial data signal Ds1 is serially / parallel-converted by the serial / parallel conversion unit 121C to generate a 6-bit parallel pixel data signal PDp1 [5: 0] and a strobe signal STB, respectively. (See FIGS. 13 (B) and 13 (D)). On the other hand, the serial data signal Ds2 is serially / parallel-converted by the serial / parallel conversion unit 121C, so that the 6-bit parallel pixel data signal PDp2 [5: 0] and the latch / firing signal LATCH / FIRE are combined. They are generated respectively (see FIGS. 13 (C) and 13 (E)).

In this example, the 6 bits from the beginning of the serial data signal Ds1 are the serial pixel data signals PDs1, and are subsequently arranged in the order of the strobe signal STB. Similarly, in this example, the 6 bits from the beginning of the serial data signal Ds2 are the serial pixel data signals PDs2, followed by the latch / firing signal LATCH / FIRE.

Here, only in the period of the strobe signal STB = "1" (period of timing t31 to t36) generated in this way, the shift clock (logical product signal Scom) is applied to each D-FF circuit 41 in the shift register unit 125A. ) Is entered. Therefore, this period is the valid period of the data input (input of the parallel pixel data signals PDp1 and PDp2) to the shift register unit 125A (see FIGS. 13 (D) and 13 (E)).

During this period, first, the parallel pixel data signals PDp1 and PDp2 corresponding to the nozzle holes Hn1 to Hn10 are sequentially input to the shift register unit 125A. Next, in the shift register unit 125A, the timing (timing) at which the latch / firing signal LATCH / FIRE changes from “0” to “1” in the parallel pixel data signals PDp1 and PDp2 that are sequentially transferred and held, respectively. At t37), it is held by each latch circuit 42 in the latch circuit unit 125B (see FIG. 13E). Subsequently, at the timing (timing t39) at which the latch / firing signal LATCH / FIRE changes from "1" to "0", each waveform generation circuit 43 in the waveform generation circuit unit 125C is a latch circuit. Based on the parallel pixel data signals PDp1 and PDp2 held in 42, the generation of the waveform signal that is the basis of the drive signal Sd is started (see FIG. 13E). Then, the level conversion circuit 125D generates a drive signal Sd corresponding to each nozzle hole Hn based on each such waveform signal, and the above-mentioned drive wall is driven based on the drive signal Sd (result). For example, the ink 9 is ejected from each nozzle hole Hn) (see timings t39 to t40 in FIGS. 11 and 13).

At this time, the 6-bit parallel pixel data signals PDp1 [5: 0] and PDp2 [5: 0] output from the D-FF circuit 41 at the last stage of the shift register unit 125A are parallel / serial conversion, respectively. Parallel / serial conversion is performed in unit 123C. Specifically, parallel / serial conversion is performed based on these 6-bit parallel pixel data signals PDp1 [5: 0], PDp2 [5: 0], strobe signal STB, and latch / firing signal LATCH / FIRE. By doing so, the above-mentioned serial data signals Ds1 and Ds2 are regenerated, respectively (see FIGS. 13 (F) to 13 (J)). Then, the serial data signals Ds1 and Ds2 regenerated in this way are output together with the clock signal CLK from the parallel / serial conversion unit 123C to the outside of each drive circuit unit 15a, 15b, 15c (FIG. 13). (I), see FIG. 13 (J)).

At this time, for example, as shown by the broken line arrows P51 and P52 in FIG. 13, a period of seven cycles T from data input to data output in each drive circuit unit 15a, 15b, 15c. Each data shifts sequentially for minutes (7 cycles). Specifically, the parallel pixel data signals PDp1 and PDp2 included in the serial data signals Ds1 and Ds2 input in the period up to the timing t31 are included in the serial data signals Ds1 and Ds2 in the period from the timing t33 to t38, respectively. Will be output (see the broken line arrow P52). Similarly, the parallel pixel data signals PDp1 and PDp2 included in the serial data signals Ds1 and Ds2 input in the period from timing t31 to t36 are included in the serial data signals Ds1 and Ds2 in the period from timing t38 to t43, respectively. Will be output (see the broken line arrow P51). Also in FIG. 13, the above-mentioned sequential transfer is not performed during the period when the strobe signal STB = “0” (timings t36 to t43 in FIGS. 13 (D) and 13 (E)). Therefore, as shown in the timings t38 to t43 at “PDp1 [5: 0]” and “PDp2 [5: 0]” (OUT) in FIGS. 13 (I) and 13 (J), the parallel pixel data signal PDp1 [ In 5: 0] and PDp2 [5: 0], "Dn_10_1" and "Dn_9_1" remain unchanged, respectively.

Further, the data transfer operation in the entire inkjet head 1C is as follows, as in the case of the above-described embodiment (data transfer operation in the entire inkjet head 1: see FIG. 7). That is, first, the 6-bit parallel pixel data signals PDp1 and PDp2 in the drive circuit unit 15a become serial data signals Ds1 and Ds2 as described above, respectively, and the drive circuit unit 15b in the subsequent stage of the drive circuit unit 15a. Is output to. Similarly, the 6-bit parallel pixel data signals PDp1 and PDp2 in the drive circuit unit 15b become serial data signals Ds1 and Ds2, respectively, as described above, and are in the subsequent stage (last stage) of the drive circuit unit 15b. It is output to the drive circuit unit 15c.

At this time, the parallel pixel data signals PDp1 and PDp2 for each of the drive circuit units 15a, 15b, and 15c are sequentially shifted in the same manner as in the case of the embodiment (see FIG. 7), while the drive circuit unit. It will be sequentially transferred from 15a to the drive circuit units 15b and 15c.

(C. Action / Effect)
Even in the modified example 3 having such a configuration, it is possible to obtain the same effect by basically the same operation as that of the embodiment.

Further, in particular, in this modification 3, since a plurality of (two in this example) serial data signals Ds1 and Ds2 are used, for example, the following effects can be obtained. That is, in these plurality (two) serial data signals Ds1 and Ds2, the number of bits of each serial pixel data signal PDs1 and PDs2 and the control signal (latch signal LATCH, firing signal FIRE, strobe signal STB, etc.) are configured. The degree of freedom can be increased. That is, for example, the number of bits of each serial pixel data signal PDs1 and PDs2 can be increased to transmit more data, and the overhead of the above-mentioned control signal can be reduced.

In Modification 3, the case where two serial data signals Ds1 and Ds2 are used has been described as an example, but the present invention is not limited to this example, and for example, even if three or more serial data signals are used. good. That is, in generalization, the serial data signal may be composed of n serial data signals (n: an integer of 2 or more). Further, even in such a case, as in the modification 3, if the plurality of nozzle holes Hn in the inkjet head are grouped so as to belong to any one of the plurality of nozzle groups. good. Further, in this case, each of the n serial data signals may include a serial pixel data signal corresponding to the nozzle hole Hn belonging to one or a plurality of nozzle groups among the plurality of nozzle groups. That is, as for the mode (regularity) in which the serial pixel data signal corresponding to each nozzle hole Hn and each serial data signal are associated with each other, not only the mode corresponding to each nozzle group but also various modes can be used. be.

[Modification 4]
FIG. 14 is a block diagram showing a configuration example of each drive circuit unit 16a, 16b, 16c in the liquid injection head (inkjet head 1D) according to the modified example 4. Even in the inkjet head 1D of the modification 4, the plurality of drive circuit units 16a, 16b, 16c are connected in series to each other in multiple stages, as in the inkjet head 1 of the embodiment shown in FIG. It is assumed that they are connected (cascade connection). That is, it is assumed that the number of stages of cascade connection between the drive circuit units 16a, 16b, 16c in the inkjet head 1D is three.

The drive circuit units 16a, 16b, 16c in the inkjet head 1D correspond to the drive circuit units 15a, 15b, 15c (see FIG. 11) described above in the inkjet head 1C of the modification 3 as follows. are doing. That is, as shown in FIG. 14, each drive circuit unit 16a, 16b, 16c is serialized in each drive circuit unit 15a, 15b, 15c instead of the serial / parallel conversion unit 121C and the parallel / serial conversion unit 123C. It corresponds to the one provided with the / parallel conversion unit 121D and the parallel / serial conversion unit 123D, and the other configurations are basically the same.

The inkjet head 1D corresponds to a specific example of the "liquid injection head" in the present disclosure.

(Serial / Parallel Converter 121D)
Similar to the serial / parallel conversion unit 121C (see FIG. 11) of the modification 3, the serial / parallel conversion unit 121D performs a predetermined serial / parallel conversion based on various signals supplied from the external head control unit 2. It is a circuit to perform. By such serial / parallel conversion, as shown in FIG. 14, m-bit (6 bits in this example) parallel pixel data signals PDp1 and PDp2 are generated, respectively.

However, unlike the serial / parallel conversion unit 121C, the serial / parallel conversion unit 121D performs serial / parallel conversion as follows. That is, as shown in FIG. 14, the serial / parallel conversion unit 121D serializes based on the serial data signals Ds1 and Ds2, the clock signal CLK, the strobe signal STB, and the latch / firing signal LATCH / FIRE. / Perform parallel conversion. The clock signal CLK, strobe signal STB, and latch / firing signal LATCH / FIRE are also output from the serial / parallel conversion unit 121D (see FIG. 14).

(Parallel / serial conversion unit 123D)
Similar to the parallel / serial conversion unit 123C of the modification 3, the parallel / serial conversion unit 123D is predetermined based on the parallel pixel data signals PDp1 and PDp2 of m bits (6 bits in this example) and the clock signal CLK. It is a circuit that performs parallel / serial conversion. Specifically, the parallel / serial conversion unit 123D has 6-bit parallel pixel data signals PDp1 and PDp2 output from the shift register unit 125A, a clock signal CLK, a strobe signal STB, and a latch / firing signal LATCH. Parallel / serial conversion is performed based on / FIRE (see FIG. 14).

By such parallel / serial conversion, as shown in FIG. 14, the above-mentioned two serial data signals Ds1 and Ds2 are generated (regenerated), respectively. Then, these serial data signals Ds1 and Ds2, a clock signal CLK, a strobe signal STB, and a latch / firing signal LATCH / FIRE are output to the outside of each drive circuit unit 16a, 16b, 16c, respectively. It has become like.

Further, the serial data signals Ds1 and Ds2, the clock signal CLK, the strobe signal STB and the latch / firing signal LATCH / FIRE output from the parallel / serial conversion unit 123D in the drive circuit unit located relatively on the front stage side are respectively. , It is designed to be input to the serial / parallel conversion unit 121D in the drive circuit unit located relatively on the rear stage side (see FIG. 14).

As described above, unlike the above-mentioned modification 3, the serial pixel data signals PDs1 and PDs2 and other signals (strobe signal STB, latch / firing signal LATCH / FIRE and other control signals) are not multiplexed. You may do so. In other words, as in the modification 2 described above, these other signals may not be included in the serial data signals (serial data signals Ds1 and Ds2).

Even in the modified example 4 having such a configuration, it is possible to obtain the same effect by basically the same operation as the modified example 3.

<3. Other variants>
Although the present disclosure has been described above with reference to some embodiments and modifications, the present disclosure is not limited to these embodiments and the like, and various modifications are possible.

For example, in the above-described embodiment and the like, the configuration examples (shape, arrangement, number, etc.) of each member in the printer 3 and the inkjet heads 1, 1A to 1D have been specifically described, but the above-described embodiment will be described. It is not limited to the one that has been printed, and may have other shapes, arrangements, numbers, and the like.

Further, as the structure of the inkjet head, each type can be applied. That is, for example, it may be a so-called side shoot type inkjet head that ejects ink 9 from the central portion of each ejection channel in the piezoelectric actuator 111 in the extending direction. Alternatively, for example, it may be a so-called edge shoot type inkjet head that ejects ink 9 along the extending direction of each ejection channel. Furthermore, the printer method is not limited to the method described in the above embodiment, for example, a thermal type (bubble jet type), a MEMS (Micro Electro Mechanical Systems) method, a thermal paper method, a dot impact method, and the like. , Various methods can be applied.

Further, for example, it is either a circulation type inkjet head that circulates and uses the ink 9 between the ink container and the inkjet head, or a non-circulation type inkjet head that uses the ink 9 without circulating it. However, it is possible to apply this disclosure.

In addition, in the above-described embodiment and the like, an example of the data transfer method has been specifically described, but the data transfer is not limited to the example given in the above-mentioned embodiment and the like, and data transfer may be performed by using another method. You may do it. Specifically, for example, even in the so-called "8B / 10B method" data transfer method, the method of the present disclosure can be applied by providing an 8B / 10B decoder, an encoder, and a protocol control circuit.

Further, the series of processes described in the above-described embodiment or the like may be performed by hardware (circuit) or software (program). When it is done by software, the software is composed of a group of programs for executing each function by a computer. Each program may be used by being preliminarily incorporated in the computer, for example, or may be installed and used in the computer from a network or a recording medium.

Further, in the above-described embodiment and the like, a printer 3 (inkjet printer) has been described as a specific example of the "liquid injection recording device" in the present disclosure, but the present invention is not limited to this example, and other than the inkjet printer. The present disclosure can also be applied to the device. In other words, the "liquid injection head" (inkjet head) of the present disclosure may be applied to devices other than the inkjet printer. Specifically, for example, the "liquid injection head" of the present disclosure may be applied to a device such as a so-called 3D printer, a facsimile, or an on-demand printing machine.

In addition, the various examples described so far may be applied in any combination.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

In addition, the present disclosure may have the following structure.
(1)
An injection unit having multiple nozzles for injecting liquid,
Based on the serial data signal, clock signal, latch signal, firing signal and strobe signal supplied from the external head control unit, a drive signal for injecting the liquid from the nozzle is generated, and the drive signal is generated. It is provided with one or more drive circuit units that output to the injection unit.
The drive circuit unit
Serial / parallel conversion is performed based on the serial data signal composed of the serial pixel data signal of m bits (m: an integer of 2 or more) individually defined for each of the plurality of nozzles and the clock signal. By doing so, the serial / parallel conversion unit that generates the m-bit parallel pixel data signal and
Drive signal generation for generating the drive signal for each of the plurality of nozzles based on the parallel pixel data signal of the mbit, the latch signal, the firing signal, the strobe signal, and the clock signal. Department and
By performing parallel / serial conversion based on the parallel pixel data signal of the m-bit and the clock signal, the serial data signal is generated, and the serial data signal and the clock signal are driven, respectively. A liquid injection head having a parallel / serial conversion unit that outputs to the outside of the circuit unit.
(2)
In the plurality of drive circuit units,
The serial data signal and the clock signal output from the parallel / serial conversion unit in the drive circuit unit located relatively on the front stage side are respectively.
By inputting to the serial / parallel conversion unit in the drive circuit unit located relatively on the rear stage side,
The liquid injection head according to (1) above, wherein the plurality of drive circuit units are connected in series to each other in multiple stages.
(3)
The serial data signal is configured to further include the latch signal, the firing signal, and the strobe signal together with the serial pixel data signal of the mbit.
The serial / parallel conversion unit performs the serial / parallel conversion based on the serial data signal and the clock signal, whereby the m-bit parallel pixel data signal, the latch signal, and the firing signal. And the strobe signal, respectively,
The parallel / serial conversion unit performs the parallel / serial conversion based on the parallel pixel data signal of the mbit, the latch signal, the firing signal, and the strobe signal, thereby performing the serial data. The liquid injection head according to (1) or (2) above, which generates a signal.
(4)
The serial data signal is composed of a single serial data signal.
The single serial data signal is configured to include the serial pixel data signals corresponding to all the nozzles, the latch signal, the firing signal, and the strobe signal (the above). The liquid injection head according to 3).
(5)
The serial data signal is composed of n serial data signals (n: integers of 2 or more) and is also composed of n serial data signals.
The plurality of nozzles are grouped so as to belong to any one of the n nozzle groups.
Each of the n serial data signals is configured to include the serial pixel data signal corresponding to a nozzle belonging to the corresponding one or a plurality of nozzle groups in the n nozzle groups.
The liquid injection head according to (3) above, wherein the latch signal, the firing signal, and the strobe signal are each included in any one of the n serial data signals.
(6)
The latch signal and the firing signal are
A single composite signal, individually defined with signal rise and fall timings, or
The description according to any one of (1) to (5) above, which is composed of a single synthetic signal individually defined by using the rising timing and the timing after a predetermined time has elapsed from the rising timing. Liquid injection head.
(7)
The drive signal generation unit has a shift register unit that sequentially transfers and holds the parallel pixel data signal of the mbit from the front stage side to the rear stage side corresponding to the drive signal for each of the plurality of nozzles. And
The shift register unit according to any one of (1) to (6) above, wherein the shift register unit sequentially transfers from the front stage side to the rear stage side in synchronization with the logical product signal of the strobe signal and the clock signal. Liquid injection head.
(8)
The liquid injection head according to any one of (1) to (7) above,
A liquid injection recording device including a head control unit that supplies the serial data signal, the clock signal, the latch signal, the firing signal, and the strobe signal to the liquid injection head, respectively.

1,1A, 1B, 1C, 1D ... Inkjet head, 11, 11a, 11b, 11c ... Injection unit, 111 ... Piezoelectric actuator (actuator plate), 112 ... Nozzle plate, 12a, 12b, 12c, 13a, 13b, 13c, 14a, 14b, 14c, 15a, 15b, 15c, 16a, 16b, 16c ... Drive circuit unit, 121, 121A, 121B, 121C, 121D ... Serial / parallel conversion unit, 122, 125 ... Drive signal generation unit, 122A, 125A ... shift register unit, 122B, 125B ... latch circuit unit, 122C, 125C ... waveform generation circuit unit, 122D, 125D ... level conversion circuit, 123, 123A, 123B, 123C, 123D ... parallel / serial conversion unit, 124A, 124C ... Demultiplexer, 2 ... head control unit, 3 ... printer, 40 ... logic product circuit (AND circuit), 41 ... D-FF circuit, 42 ... latch circuit, 43 ... waveform generation circuit, 45 ... logic negative circuit (NOT circuit) ), 9 ... Ink, Hn, Hn1 to Hn10 ... Nozzle hole, Gp1, Gp2 ... Nozzle group, Ds, Ds1, Ds2 ... Serial data signal, PDs, PDs1, PDs2 ... Serial pixel data signal, PDp, PDp1, PDp2 ... Parallel Pixel data signal, CLK ... clock signal, STB ... strobe signal, LATCH ... latch signal, FIRE ... firing signal, LATCH / FIRE ... latch / firing signal, Scom ... logical product signal, Sd ... drive signal, Vd ... drive voltage , T ... time, Δt ... predetermined time, t11 to t23, t31 to t43 ... timing, T ... cycle.

Claims (8)

An injection unit having multiple nozzles for injecting liquid,
Based on the serial data signal, clock signal, latch signal, firing signal and strobe signal supplied from the external head control unit, a drive signal for injecting the liquid from the nozzle is generated, and the drive signal is generated. It is provided with one or more drive circuit units that output to the injection unit.
The drive circuit unit
Serial / parallel conversion is performed based on the serial data signal composed of the serial pixel data signal of m bits (m: an integer of 2 or more) individually defined for each of the plurality of nozzles and the clock signal. By doing so, the serial / parallel conversion unit that generates the m-bit parallel pixel data signal and
Drive signal generation for generating the drive signal for each of the plurality of nozzles based on the parallel pixel data signal of the mbit, the latch signal, the firing signal, the strobe signal, and the clock signal. Department and
By performing parallel / serial conversion based on the parallel pixel data signal of the m-bit and the clock signal, the serial data signal is generated, and the serial data signal and the clock signal are driven, respectively. A liquid injection head having a parallel / serial conversion unit that outputs to the outside of the circuit unit. In the plurality of drive circuit units,
The serial data signal and the clock signal output from the parallel / serial conversion unit in the drive circuit unit located relatively on the front stage side are respectively.
By inputting to the serial / parallel conversion unit in the drive circuit unit located relatively on the rear stage side,
The liquid injection head according to claim 1, wherein the plurality of drive circuit units are connected in series with each other in multiple stages. The serial data signal is configured to further include the latch signal, the firing signal, and the strobe signal together with the serial pixel data signal of the mbit.
The serial / parallel conversion unit performs the serial / parallel conversion based on the serial data signal and the clock signal, whereby the m-bit parallel pixel data signal, the latch signal, and the firing signal. And the strobe signal, respectively,
The parallel / serial conversion unit performs the parallel / serial conversion based on the parallel pixel data signal of the mbit, the latch signal, the firing signal, and the strobe signal, thereby performing the serial data. The liquid injection head according to claim 1 or 2, wherein the signal is generated. The serial data signal is composed of a single serial data signal.
A claim comprising the single serial data signal including a number of serial pixel data signals corresponding to all the nozzles, a latch signal, a firing signal, and a strobe signal. 3. The liquid injection head according to 3. The serial data signal is composed of n serial data signals (n: integers of 2 or more) and is also composed of n serial data signals.
The plurality of nozzles are grouped so as to belong to any one of the n nozzle groups.
Each of the n serial data signals is configured to include the serial pixel data signal corresponding to a nozzle belonging to the corresponding one or a plurality of nozzle groups in the n nozzle groups.
The liquid injection head according to claim 3, wherein the latch signal, the firing signal, and the strobe signal are each included in any one of the n serial data signals. The latch signal and the firing signal are
A single composite signal, individually defined with signal rise and fall timings, or
The present invention according to any one of claims 1 to 5, which is composed of a single synthetic signal individually defined by using the rising timing and the timing after a predetermined time has elapsed from the rising timing. Liquid injection head. The drive signal generation unit has a shift register unit that sequentially transfers and holds the parallel pixel data signal of the mbit from the front stage side to the rear stage side corresponding to the drive signal for each of the plurality of nozzles. And
The one according to any one of claims 1 to 6, wherein the shift register unit sequentially transfers from the front stage side to the rear stage side in synchronization with the logical product signal of the strobe signal and the clock signal. Liquid injection head. The liquid injection head according to any one of claims 1 to 7.
A liquid injection recording device including a head control unit that supplies the serial data signal, the clock signal, the latch signal, the firing signal, and the strobe signal to the liquid injection head, respectively.

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