CN110648967A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110648967A
CN110648967A CN201810670328.2A CN201810670328A CN110648967A CN 110648967 A CN110648967 A CN 110648967A CN 201810670328 A CN201810670328 A CN 201810670328A CN 110648967 A CN110648967 A CN 110648967A
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ions
source
forming
fin
drain
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part; forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed. The device formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
When the channel length is less than 100nm, in the conventional MOSFET, the source and drain regions interact with each other due to the semiconductor material of the semiconductor substrate surrounding the active region, the distance between the drain and the source is also shortened, and a short channel effect is generated, so that the control capability of the gate on the channel is deteriorated, the difficulty of pinch-off of the gate voltage on the channel is increased, and the Sub-threshold leakage (Sub-threshold leakage) phenomenon is more likely to occur.
A Fin Field effect transistor (FinFET) is a new type of metal oxide semiconductor Field effect transistor, and its structure is usually formed on a silicon-on-insulator (SOI) substrate, and includes narrow and isolated silicon strips (i.e., vertical channel structures, also called fins) with gate structures on both sides of the Fin. The FinFET structure makes the device smaller and has higher performance.
However, as the integration of semiconductor devices is further improved, the performance of finfet devices is expected to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a fin field effect transistor.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part; forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed.
Optionally, the material of the protective layer includes: SiO 22SiOCN, SiBCN or SiOBCN.
Optionally, the thickness of the protective layer is: 50 to 200 angstroms.
Optionally, the substrate has a well region therein, and the well region has trap ions therein, wherein the trap ions have a conductivity type opposite to that of the doped ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
Optionally, a gate structure crossing the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; the forming method of the protective layer comprises the following steps: forming protective films on the top surface of the isolation structure, the side wall and the top surface of the fin part and the side wall and the top surface of the grid structure; forming a first dielectric layer on the surface of the protective film, wherein the top surface of the first dielectric layer is lower than the top surface of the fin portion; and removing the protective film on the top of the fin part and the grid structure by taking the first dielectric layer as a mask to form the protective layer.
Optionally, the material of the first dielectric layer includes: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
Optionally, the thickness of the first dielectric layer is 200 angstroms to 500 angstroms.
Optionally, the forming method further includes: and forming source and drain doped regions in the fin parts on two sides of the grid structure respectively, wherein source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions.
Optionally, after the protective layer is formed and before the source-drain doped region is formed, doping ions are doped at the bottom of the fin portion; or doping ions into the fin part at the bottom of the source-drain doped region after the protective layer and the source-drain doped region are formed.
Optionally, the size from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
Optionally, the doping concentration of the source and drain ions is: 1.0E 21-5.0E 21 atomic number/cubic centimeter.
Optionally, after the source-drain doped region is formed and the dopant ions are doped at the bottom of the fin portion, the forming method further includes: forming a second dielectric layer on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; forming a contact hole exposing the top surface of the source drain doped region in the second dielectric layer; and forming a plug in the contact hole.
The present invention also provides a semiconductor structure comprising: the surface of the substrate is provided with a fin part and an isolation structure, and the top of the isolation structure is lower than the top of the fin part and covers part of the side wall of the fin part; a protective layer on a top surface of the isolation structure; dopant ions located within the bottom fin portion.
Optionally, the material of the protective layer includes:SiO2SiOCN, SiBCN or SiOBCN.
Optionally, the thickness of the protective layer is: 50 to 200 angstroms.
Optionally, the substrate has a well region therein, and the well region has trap ions therein, wherein the trap ions have a conductivity type opposite to that of the doped ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
Optionally, a gate structure crossing the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; source and drain doped regions are respectively arranged in the fin parts at two sides of the grid structure and the protective layer, source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions; the semiconductor structure further includes: the first dielectric layer is positioned on the surface of the protective layer, and the top surface of the first dielectric layer is lower than the top surface of the fin portion; the second dielectric layer is positioned on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; the contact hole is positioned in the second medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region; a plug located within the contact hole.
Optionally, the material of the first dielectric layer includes: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
Optionally, the thickness of the first dielectric layer is 200 angstroms to 500 angstroms.
Optionally, the size from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the substrate is internally provided with a well region, and the well region is used for realizing electrical isolation among different devices. Form the protective layer at isolation structure top for the basement top not only covers isolation structure, still covers the protective layer, then follow-up when doping ion in fin portion bottom, protective layer and isolation structure are great to the protection dynamics of basement, make in the well region be difficult for being doped with doping ion, then the isolation performance of well region is not influenced, promptly: the well region has better performance for isolating different devices, and the performance of the semiconductor device is better.
Further, the method for forming the protective layer includes: and forming protective films on the surfaces of the isolation structures, the side walls and the top surfaces of the fin parts. And forming a first dielectric layer on the surface of the protective film after the protective film is formed. And forming the protective layer by taking the first dielectric layer as a mask. And when doping ions are doped at the bottoms of the fin portions subsequently, the first dielectric layer can further protect the well region in the substrate, doping ions in the well region are prevented, and the performance of different devices of the semiconductor isolated by the well region is further ensured.
Furthermore, the grid electrode structures are arranged across the fin parts, after the first dielectric layers are formed, the depth-to-width ratio of the grooves between the adjacent grid electrode structures is favorably reduced, the difficulty of forming the second dielectric layers in the grooves between the adjacent grid electrode structures is low subsequently, the compactness of the formed second dielectric layers is good, the isolation performance of the second dielectric layers is good, and the performance of the semiconductor device is favorably improved.
Drawings
Fig. 1-3 are schematic structural diagrams of steps in a method of forming an N-type finfet transistor;
fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, finfet performance is poor.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming an N-type finfet.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view taken along line a-a1 in fig. 1, fig. 1 is a cross-sectional view taken along line B-B1 in fig. 2, providing a substrate 100, the substrate 100 having a well region 150 therein, the substrate 100 having a fin 101 and an isolation structure 104 on a surface thereof, the isolation structure 104 having a top portion lower than a top surface of the fin 101 and covering a portion of a sidewall of the fin 101 and crossing over a gate structure 102 of the fin 101; and source-drain doped regions 103 are respectively formed in the fin portions 101 on the two sides of the gate structure 102.
Referring to fig. 3, doped ions are doped into the fin 101 at the bottom of the source/drain doped region 103.
In the above method, the method for forming the source/drain doped region 103 includes: forming source and drain openings in the fin portions 101 on two sides of the gate structure 102 respectively; forming an epitaxial layer in the source drain opening; and doping source and drain ions into the epitaxial layer to form the source and drain doped region 103.
In order to reduce the contact resistance between the source and drain doped regions 103 and the plugs subsequently located on the top of the source and drain doped regions 103, one solution includes: and increasing the doping concentration of source and drain ions. However, the doping concentration of the source and drain ions is too high, so that more source and drain ions are easy to diffuse into the channel region to generate a short channel effect. A method for suppressing short channel effects comprises: and reducing the depth of the source and drain openings. However, the depth of the source-drain opening is small, so that the resistance of the fin 101 at the bottom of the source-drain opening is large. The method for reducing the resistance of the fin part 101 at the bottom of the source drain doped region 103 comprises the following steps: doping ions are doped into the fin portion 101 at the bottom of the source drain doping region 103. Due to the fact that the size from the top of the source-drain doped region 103 to the bottom of the source-drain doped region 103 is large, the energy required for doping the doped ions in the fin portion 101 at the bottom of the source-drain doped region 103 is high.
However, the energy of the doped ions at the bottom of the source/drain doped region 103 is high, and the thickness of the isolation structure 104 is thin, so that the isolation structure 104 may be broken down, and the doped ions easily enter the well region 150 at the bottom of the isolation structure 104. The well region 150 is used for realizing electrical isolation between semiconductor devices, and the doped ions enter the well region 150, so that the isolation performance of the well region 150 is deteriorated, the well region 150 is not favorable for realizing electrical isolation between semiconductor devices, and electric leakage is easy to occur.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a protective layer on the top surface of the isolation structure; and doping ions at the bottom of the fin part after the protective layer is formed. The device formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a cross-sectional view taken along line C-C1 in fig. 4, and fig. 4 is a cross-sectional view taken along line D-D1 in fig. 5, providing a substrate 200, wherein the substrate 200 has a fin 201 and an isolation structure 202 on a surface thereof, and a top of the isolation structure 202 is lower than a top of the fin 201 and covers a portion of a sidewall of the fin 201.
The method for forming the substrate 200 and the fin 201 comprises the following steps: providing an initial substrate, wherein the surface of the initial substrate is provided with a first mask layer, and the first mask layer exposes part of the top surface of the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form a substrate 200 and a fin part 201 positioned on the surface of the substrate 200.
In this embodiment, the initial substrate is made of silicon, and correspondingly, the substrate 200 and the fin 201 are made of silicon. In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator, and accordingly, the materials of the substrate and the fin portion comprise: germanium, silicon on insulator, or germanium on insulator.
The material of the first mask layer comprises: silicon nitride or titanium nitride. The first mask layer is used as a mask for forming the substrate 200 and the fin 201.
The process for etching the initial substrate by taking the first mask layer as a mask comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
Also within the substrate 200 is a well region 250 having well ions therein, the conductivity type of which is related to the type of transistor. Specifically, when the transistor is an NMOS transistor, the trap ions are P-type ions, such as: boron ions; when the transistor is a PMOS transistor, the trap ions are N-type ions, such as: phosphorus ions or arsenic ions. The well region 250 is used to electrically isolate different devices of the semiconductor.
The method for forming the isolation structure 202 comprises the following steps: forming an isolation structure film on the surface of the substrate 200 and the sidewall and the top surface of the fin 201; and removing part of the isolation structure film to expose part of the side wall and the top surface of the fin 201, and forming an isolation structure 202, wherein the top surface of the isolation structure 202 is lower than the top surface of the fin 201 and covers part of the side wall of the fin 201.
The material of the isolation structure film comprises: silicon oxide, silicon oxynitride, or low K material (K less than 3.9), and accordingly, the material of the isolation structure 202 includes: silicon oxide, silicon oxynitride, or low K material (K less than 3.9). The isolation structure 202 is made of a material having good insulation property, which is beneficial to reducing the leakage current of the fin portion 201.
The forming process of the isolation structure film comprises the following steps: a fluid chemical vapor deposition process.
The isolation structure 202 is used to electrically isolate different devices in the semiconductor.
A protective layer is subsequently formed on the surface of the isolation structure 202. In this embodiment, after forming the isolation structure 202 and before forming the protection layer, the forming method further includes: forming a grid structure crossing the fin part; forming a first side wall on the side wall of the grid structure; and forming a lightly doped region in the gate structure and the fin portion 201 at two sides of the first side wall. Please refer to fig. 6 to 7.
Referring to fig. 6, a gate structure 203 is formed across the fin 201.
The cross-sectional direction of fig. 6 coincides with the cross-sectional direction of fig. 5.
The gate structure 203 includes: the fin 201 includes a gate dielectric layer on partial side walls and top surfaces of the fin, and a gate layer on a surface of the gate dielectric layer.
The forming method of the gate structure 203 comprises the following steps: forming a gate dielectric film on the side wall and the top surface of the fin portion 201; forming a gate film on the surface of the gate dielectric film, wherein the surface of the gate film is provided with a second mask layer (not shown in the figure), and the second mask layer exposes the top surface of part of the gate film; and etching the gate film and the gate dielectric film by using the second mask layer as a mask until the top surface of the isolation structure 202 is exposed, so as to form a gate dielectric layer (not shown in the figure) and a gate layer (not shown in the figure) on the surface of the gate dielectric layer.
The gate dielectric film is made of the following materials: and silicon oxide, and correspondingly, the material of the gate dielectric layer comprises silicon oxide. The forming process of the gate dielectric film comprises the following steps: an in-situ steam generation process or a chemical oxidation process.
The material of the gate film comprises silicon, and correspondingly, the material of the gate layer comprises silicon. The forming process of the gate electrode film comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
The gate structure 203 includes a gate dielectric layer and a gate layer on the surface of the gate dielectric layer.
Referring to fig. 7, a first sidewall 204 is formed on a sidewall of the gate structure 203; lightly doped regions 205 are formed in the fin portions 201 on two sides of the gate structure 203 and the first sidewall 204, respectively.
The method for forming the first side wall 204 includes: forming a first sidewall film on the sidewall and the top surface of the gate structure 203; and removing the first sidewall film on the top of the gate structure 203 to form the first sidewall 204.
The first side wall film is made of materials including: silicon nitride or silicon oxynitride, respectively, the material of the first side comprising: silicon nitride or silicon oxynitride.
The forming process of the first side wall film comprises the following steps: an atomic layer deposition process or a chemical vapor deposition process.
The process for removing the first sidewall film on the top of the gate structure 203 comprises: one or two of the dry etching process and the wet etching process are combined.
The first side walls 204 are used for defining the position of the lightly doped region 205.
The formation process of the lightly doped region 205 includes a second ion implantation process including lightly doped ions having a conductivity type related to the type of the transistor. In the present embodiment, the transistor is an NMOS transistor, and therefore, the lightly doped ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the transistor is a PMOS transistor, and thus, the lightly doped ions are P-type ions, such as: boron ion or BF2 +Ions.
Referring to fig. 8 and 9, after the doped region 205 is formed, a protection film 206 is formed on the surface of the isolation structure 202, the sidewalls and the top surface of the fin 201, the sidewalls of the first sidewall 204, and the top surface of the gate structure 203.
Fig. 8 and 7 are in the same cross-sectional direction, and fig. 9 and 4 are in the same cross-sectional direction.
In this embodiment, the material of the protection film 206 is silicon nitride. In other embodiments, the material of the protective film includes: SiOCN, SiBCN or SiOBCN.
In the present embodiment, the protection film 206 on the surface of the isolation structure 202 and on the sidewalls of the fin 201 and the gate structure 203 is used to form a subsequent protection layer. The protective layer on the sidewall of the gate structure 203 is used to define the position of the subsequent source/drain doped region.
In this embodiment, the forming process of the protection film 206 is as follows: and (5) an atomic layer deposition process. In other embodiments, the process of forming the protective film includes: a physical vapor deposition process or a chemical vapor deposition process.
In this embodiment, the protection film 206 formed by the atomic layer deposition process is dense, and because the protection film 206 is used for forming a subsequent protection layer, the protection layer is also dense, so that when doping ions are doped at the bottom of the fin portion 201 subsequently, the protection layer and the isolation structure 202 have a large protection force on the substrate 200, so that the doping ions are not easily doped in the well region 250, which is beneficial to ensuring the electrical isolation performance of the well region 250 and improving the performance of the semiconductor device.
The thickness of the protective film 206 is: 50 to 200 angstroms. The thickness of the protective film 206 determines the thickness of the subsequent protective layer.
Referring to fig. 10, a first dielectric layer 207 is formed on the surface of the protection film 206, and the top surface of the first dielectric layer 207 is lower than the top surface of the fin 201.
The forming method of the first dielectric layer 207 comprises the following steps: forming a first dielectric film on the surface of the protective film 206; and etching back part of the first dielectric film to form the first dielectric layer 207.
The first dielectric film comprises the following materials: silicon oxide, silicon oxynitride or low K material (K less than 3.9), and correspondingly, the material of the first dielectric layer 207 includes: silicon oxide, silicon oxynitride, or low K material (K less than 3.9).
The forming process of the first dielectric film comprises a chemical vapor deposition process or a physical vapor deposition process.
The process for removing part of the first dielectric film comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The functions of the first dielectric layer 207 include: on one hand, the first dielectric layer 207 is used for protecting the protective film 206 on the surface of the isolation structure 202 from being removed, which is beneficial to forming a protective layer on the surface of the isolation structure 202 subsequently; moreover, when doping ions are doped at the bottom of the fin portion 201 subsequently, the first dielectric layer 207 is also used for protecting the substrate 200 at the bottom of the isolation structure 202, so that the doping ions are not easy to enter the well region 250, the electrical isolation performance of the well region 250 is guaranteed, and the performance of the well region 250 in isolating different devices of the semiconductor is better; on the other hand, after the first dielectric layer 207 is formed, the depth-to-width ratio of the trench between the adjacent gate structures 203 is small, which is beneficial to reducing the difficulty of forming a second dielectric layer in the trench between the adjacent gate structures 203, and the formed second dielectric layer is compact, the isolation performance of the second dielectric layer is good, and the performance of the semiconductor device is beneficial to being improved.
The thickness of the first dielectric layer 207 is: 200 to 500 angstroms.
Referring to fig. 11, the first dielectric layer 207 is used as a mask to remove the gate structure 203 and the protective film 206 on the top of the fin 201, and a protective layer 246 is formed on the surface of the isolation structure 202 and on the sidewalls of the fin 201 and the gate structure 203; after the protective layer 246 is formed, source and drain openings 208 are formed in the fin portions 201 on two sides of the gate structure 203 (see fig. 8), respectively.
In the present embodiment, silicon nitride is used as the material of the protection film 206, and the protection film 206 is used for forming the protection layer 246 later, so the material of the protection layer 246 is also silicon nitride. Due to the compactness of the silicon nitride, when doping ions are doped at the bottom of the fin portion 201, the protective layer 246 and the isolation structure 202 have stronger protective capability for the substrate 200, so that the doping ions are not easily doped in the well region 250, thereby being beneficial to ensuring the electrical isolation performance of the well region 250 and improving the performance of the semiconductor device.
The first sidewall 204 of the sidewall of the gate structure 203 and the protection layer 246 are used to define the position of the source drain opening 208.
The forming process of the source-drain opening 208 includes: one or two of the dry etching process and the wet etching process are combined.
The depth of the source drain opening 208 is: 300 to 800 angstroms. And a source-drain doped region is formed in the source-drain opening 208 in the follow-up process, and although the doping concentration of source-drain ions in the source-drain doped region is higher, the depth of the source-drain opening 208 is shallower, and the source-drain ions are not easy to diffuse into a channel region, so that the short channel effect can be inhibited.
Referring to fig. 12, an epitaxial layer (not shown) is formed in the source-drain opening 208 (see fig. 11); and doping source and drain ions into the epitaxial layer 209 to form a source and drain doped region 209.
The forming process of the epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
The material of the epitaxial layer and the conductivity type of the source and drain ions are related to the type of the transistor.
In this embodiment, the transistor is an NMOS transistor, and therefore, the material of the epitaxial layer includes silicon and phosphorus, and the source and drain ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the transistor is a PMOS transistor, and thus, the epitaxial layer comprises silicon germanium, and the source and drain ions are P-type ionsAnd (c) as follows: boron ion or BF2 +Ions.
The doping concentration of the source and drain ions is as follows: 1.0E 21-5.0E 21 atomic number/cubic centimeter. The source and drain ions have a higher doping concentration, which is beneficial to reducing the contact resistance between the source and drain doped region 209 and the plug which is subsequently positioned on the surface of the source and drain doped region 209.
The dimension from the top of the source-drain doped region 209 to the bottom of the source-drain doped region 209 is determined by the depth of the source-drain opening 208, and therefore the dimension from the top of the source-drain doped region 209 to the bottom of the source-drain doped region 209 is: 300 to 800 angstroms. Although the dimension from the top of the source-drain doped region 209 to the bottom of the source-drain doped region 209 is larger, because the top of the substrate 200 not only has the isolation structure 202, but also has the protection layer 246 and the first dielectric layer 207, and the protection strength of the first dielectric layer 207, the protection layer 246 and the isolation structure 202 to the substrate 200 is larger, ions are not easily doped into the well region 250 when ions are doped into the fin portion 201 at the bottom of the source-drain doped region 209 in the following process, so that the isolation performance of the well region 250 is still better, and the performance of the semiconductor device is favorably improved.
Referring to fig. 13, doped ions are doped into the fin 201 at the bottom of the source/drain doped region 209, and the conductivity type of the doped ions is the same as that of the source/drain ions.
In this embodiment, after the protection layer 246 and the source/drain doped region 209 are formed, doped ions are doped into the fin 201 at the bottom of the source/drain doped region 209.
In other embodiments, after the protective layer is formed and before the source/drain doped region is formed, doped ions are doped at the bottom of the fin portion.
The doped ions are used for reducing the resistance of the fin 201 at the bottom of the source drain doped region 209. The dopant ions are related to the type of transistor. In this embodiment, the transistor is an NMOS transistor, and the dopant ions are N-type ions, such as: phosphorus ions or arsenic ions. In other embodiments, the transistor is a PMOS transistor, and the dopant ions are P-type, such as: boron ion or BF2 +Ions.
Since the dimension from the top of the source drain doped region 209 to the bottom of the source drain doped region 209 is large, the energy of the implantation process required for doping ions at the bottom of the fin 201 is high. Although the implantation process has high energy, the top of the substrate 200 not only has the isolation structure 202, but also has the protection layer 246 and the first dielectric layer 207, so that the isolation structure 202, the protection layer 246 and the first dielectric layer 207 have high protection to the substrate 200, and the doped ions are not easy to enter the well region 250, that is: the isolation performance of the well region 250 is less affected by the doped ions, so that the well region 250 has stronger performance of isolating different devices of the semiconductor, and the performance of the semiconductor device is better.
After doping ions into the fin portion 201 at the bottom of the source drain doping region 209, the forming method further includes: forming a second dielectric layer on the surface of the first dielectric layer 207, the side wall and the top surface of the source-drain doped region 209, and the side wall and the top surface of the gate structure 203; removing part of the second dielectric layer until the top surface of the source drain doped region 209 is exposed, and forming a contact hole in the second dielectric layer; and forming a plug in the contact hole.
Before the second dielectric layer is formed, the first dielectric layer 207 is formed, which is beneficial to reducing the depth-to-width ratio of the grooves between the adjacent gate structures 203, so that the difficulty of forming the second dielectric layer is reduced, and the formed second dielectric layer is compact, so that the isolation performance of the second dielectric layer is good, and the performance of a semiconductor device is improved.
Accordingly, the present invention further provides a semiconductor structure, please refer to fig. 13, which includes: the semiconductor device comprises a substrate 200, wherein the surface of the substrate 200 is provided with a fin portion 201 and an isolation structure 202, and the top of the isolation structure 202 is lower than the top of the fin portion 201 and covers part of the side wall of the fin portion 201; a protective layer 246 on a top surface of the isolation structure 202; dopant ions located within the bottom fin 201.
The material of the protective layer 246 includes: silicon nitride, SiOCN, SiBCN, or SiOBCN. The thickness of the protective layer 246 is: 50 to 200 angstroms.
The substrate 200 has a well region 250 therein, the well region 250 has trap ions therein, and the trap ions have a conductivity type opposite to that of the doped ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
The semiconductor device comprises a fin part 201, a grid electrode structure 203, source and drain doped regions 209, source and drain ions and a semiconductor substrate, wherein the grid electrode structure 203 crosses the fin part 201, the fin part 201 on two sides of the grid electrode structure 203 is internally provided with the source and drain doped regions 209 respectively, and the source and drain doped regions 209 are internally provided with the source and drain ions, and the conductivity type of the source and drain ions is the same as that of the doped; the semiconductor structure further includes: a sacrificial layer 207 on the surface of the protection layer 246, wherein the top surface of the sacrificial layer 207 is lower than the top surface of the fin 201; the dielectric layers are positioned on the surface of the sacrificial layer 207, the side wall and the top surface of the source drain doped region 209 and the side wall and the top surface of the gate structure 203; a contact hole in the dielectric layer, wherein the bottom of the contact hole exposes the top surface of the source drain doped region 209; a plug located within the contact hole.
The material of the sacrificial layer 207 includes: silicon oxide, silicon oxynitride, or low-K dielectric material; the low K dielectric material has a K value of less than 3.9.
The thickness of the sacrificial layer 207 is: 200 to 500 angstroms.
The dimension from the top of the source drain doped region 209 to the bottom of the source drain doped region 209 is: 300 to 800 angstroms.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the surface of the substrate is provided with a fin part and an isolation structure, the top of the isolation structure is lower than the top of the fin part, and the isolation structure covers part of the side wall of the fin part;
forming a protective layer on the top surface of the isolation structure;
and doping ions at the bottom of the fin part after the protective layer is formed.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises: SiO 22SiOCN, SiBCN or SiOBCN.
3. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of: 50 to 200 angstroms.
4. The method of claim 1, wherein the substrate has a well region therein, the well region having trap ions therein, the trap ions being of opposite conductivity type to the dopant ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
5. The method of claim 1, wherein the gate structure crosses the fin portion; the protective layer also covers the fin part and the side wall of the grid structure; the forming method of the protective layer comprises the following steps: forming protective films on the top surface of the isolation structure, the side wall and the top surface of the fin part and the side wall and the top surface of the grid structure; forming a first dielectric layer on the surface of the protective film, wherein the top surface of the first dielectric layer is lower than the top surface of the fin portion; and removing the protective film on the top of the fin part and the grid structure by taking the first dielectric layer as a mask to form the protective layer.
6. The method of forming a semiconductor structure of claim 5, wherein a material of the first dielectric layer comprises: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
7. The method of claim 5, wherein the first dielectric layer has a thickness of 200 to 500 angstroms.
8. The method of forming a semiconductor structure of claim 5, further comprising: and forming source and drain doped regions in the fin parts on two sides of the grid structure respectively, wherein source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions.
9. The method for forming a semiconductor structure according to claim 8, wherein after the protective layer is formed and before the source-drain doped region is formed, doping ions are doped at the bottom of the fin portion; or doping ions into the fin part at the bottom of the source-drain doped region after the protective layer and the source-drain doped region are formed.
10. The method for forming the semiconductor structure according to claim 8, wherein the dimension from the top of the source-drain doped region to the bottom of the source-drain doped region is as follows: 300 to 800 angstroms.
11. The method for forming a semiconductor structure according to claim 8, wherein the doping concentration of the source and drain ions is: 1.0E 21-5.0E 21 atomic number/cubic centimeter.
12. The method for forming a semiconductor structure of claim 8, wherein after forming the source-drain doped regions and doping dopant ions at the bottom of the fin, the method further comprises: forming a second dielectric layer on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; forming a contact hole exposing the top surface of the source drain doped region in the second dielectric layer; and forming a plug in the contact hole.
13. A semiconductor structure, comprising:
the surface of the substrate is provided with a fin part and an isolation structure, and the top of the isolation structure is lower than the top of the fin part and covers part of the side wall of the fin part;
a protective layer on a top surface of the isolation structure;
dopant ions located within the bottom fin portion.
14. The semiconductor structure of claim 13, wherein a material of the protective layer comprises: SiO 22SiOCN, SiBCN or SiOBCN.
15. The semiconductor structure of claim 13, wherein the protective layer has a thickness of: 50 to 200 angstroms.
16. The semiconductor structure of claim 13, wherein said substrate has a well region therein, said well region having therein trap ions, said trap ions being of opposite conductivity type to the dopant ions; when the transistor is an NMOS transistor, the doped ions are N-type ions; when the transistor is a PMOS transistor, the doped ions are P-type ions.
17. The semiconductor structure of claim 13, wherein the gate structure crosses the fin; the protective layer also covers the fin part and the side wall of the grid structure; source and drain doped regions are respectively arranged in the fin parts at two sides of the grid structure and the protective layer, source and drain ions are arranged in the source and drain doped regions, and the conductivity type of the source and drain ions is the same as that of the doped ions; the semiconductor structure further includes: the first dielectric layer is positioned on the surface of the protective layer, and the top surface of the first dielectric layer is lower than the top surface of the fin portion; the second dielectric layer is positioned on the surface of the first dielectric layer, the side wall and the top surface of the source-drain doped region and the side wall and the top surface of the grid structure; the contact hole is positioned in the second medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region; a plug located within the contact hole.
18. The semiconductor structure of claim 17, wherein a material of the first dielectric layer comprises: silicon oxide, silicon oxynitride, or a low dielectric constant dielectric material.
19. The semiconductor structure of claim 17, wherein the first dielectric layer has a thickness of 200 to 500 angstroms.
20. The semiconductor structure of claim 17, wherein the dimension from the top of the source drain doped region to the bottom of the source drain doped region is: 300 to 800 angstroms.
CN201810670328.2A 2018-06-26 2018-06-26 Semiconductor structure and forming method thereof Pending CN110648967A (en)

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