CN110648920A - Trench MOS device and manufacturing method thereof - Google Patents

Trench MOS device and manufacturing method thereof Download PDF

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CN110648920A
CN110648920A CN201910938219.9A CN201910938219A CN110648920A CN 110648920 A CN110648920 A CN 110648920A CN 201910938219 A CN201910938219 A CN 201910938219A CN 110648920 A CN110648920 A CN 110648920A
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impurity
substrate
layer
mos device
trench mos
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CN110648920B (en
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周东飞
孙永生
钟圣荣
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Element Separation (AREA)
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Abstract

The invention discloses a Trench MOS device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: s1, providing a substrate; s2, etching one surface of the substrate to form a groove; s3, forming a first oxide layer on the surface of the substrate and in the groove; s4, depositing on the surface of the first oxide layer to form a deposition layer; s5, performing high-temperature annealing treatment on the deposition layer, and diffusing first impurities in the deposition layer into the substrate to form a diffusion layer; s6, impurity injection is carried out on the diffusion layer and the substrate to form an impurity injection region. The invention realizes that the channel length is reduced under the condition of not influencing the body junction depth, the on-resistance of the Trench MOS device is effectively reduced, the reverse characteristic of the device is not influenced, and the reliability of the device is further ensured; the body regions are prevented from being connected into a whole, so that the Trench MOS device is started; in addition, there is an advantage that the cost is not increased.

Description

Trench MOS device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a Trench MOS (deep Trench metal oxide semiconductor field effect transistor) device and a manufacturing method thereof.
Background
The Trench MOS is developed on the basis of a VDMOS (vertical double-diffused metal oxide semiconductor field effect transistor), and has lower on-resistance and gate-drain charge density than the VDMOS, and thus has lower conduction and switching loss and faster switching speed.
For the Trench MOS, it is required that the on-resistance is as small as possible, and the on-resistance of the Trench MOS is currently mainly reduced by reducing the channel resistance, specifically, the channel length is reduced by reducing the body junction depth, and the body junction depth is made to be shallow by reducing the channel length, so that the reverse leakage performance of the device is affected, and the turn-off loss of the device is increased when the reverse leakage becomes large, so that the reliability of the device is affected.
Disclosure of Invention
The invention aims to overcome the defects that in the prior art, the channel length is reduced, the body junction depth is shallow and the reverse leakage performance of a device is affected by reducing the on-resistance of a Trench MOS, and provides a Trench MOS device and a manufacturing method thereof.
The invention solves the technical problems through the following technical scheme:
the invention provides a manufacturing method of a Trench MOS device, which comprises the following steps:
s1, providing a substrate;
s2, etching one surface of the substrate to form a groove;
s3, forming a first oxide layer on the surface of the substrate and in the groove;
s4, depositing on the surface of the first oxide layer to form a deposition layer;
wherein the deposited layer includes a first impurity;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate;
s5, performing high-temperature annealing treatment on the deposition layer, and diffusing first impurities in the deposition layer into the substrate to form a diffusion layer;
s6, injecting impurities into the diffusion layer and the substrate to form an impurity injection region;
the impurity injection regions are respectively positioned at two sides of the groove.
Preferably, step S5 includes:
carrying out high-temperature treatment on the deposition layer for a first set time by adopting a first set temperature, carrying out annealing treatment on the deposition layer for a second set time by adopting a second set temperature, and diffusing first impurities in the deposition layer into the substrate to form the diffusion layer;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
Preferably, step S6 includes:
adopting second impurity injection to the diffusion layer and the substrate to form a first impurity injection region;
adopting the first impurity implantation in the first impurity implantation region to form a second impurity implantation region;
wherein the second impurity implantation region is positioned at one side of the first impurity implantation region far away from the substrate;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
Preferably, step S6 is followed by:
s7, etching off the part of the deposition layer except the part positioned in the groove;
s8, forming a second oxide layer on the surface of the groove and the surface of the first oxide layer;
s9, etching the second oxide layer and the second impurity injection region to form a contact hole;
wherein the contact hole is positioned at the outer side of the second impurity injection region;
and S10, forming a first metal layer in the contact hole and on the upper surface of the second oxidation layer, and forming a second metal layer on the lower surface of the substrate.
The invention also provides a Trench MOS device, which is obtained by using the method for manufacturing the Trench MOS device, and the Trench MOS device includes:
a substrate;
the groove is formed on one surface of the substrate;
the first oxidation layer is formed on the surface of the substrate and in the groove;
depositing a layer, forming and filling the groove;
wherein the deposited layer includes a first impurity;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate;
a diffusion layer formed between the first oxide layer and the substrate, the diffusion layer being formed by performing high-temperature annealing treatment on the deposition layer to diffuse the first impurity in the deposition layer;
an impurity implantation region formed by implanting impurities to the diffusion layer and the substrate;
the impurity injection regions are respectively positioned at two sides of the groove.
Preferably, the diffusion layer is formed by performing high-temperature treatment on the deposition layer at a first set temperature for a first set time, and then performing annealing treatment on the deposition layer at a second set temperature for a second set time;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
Preferably, the impurity implantation region includes a first impurity implantation region and a second impurity implantation region;
the first impurity implantation region is formed by implanting a second impurity into the diffusion layer and the substrate;
the second impurity implantation region is formed by implanting the first impurity into the first impurity implantation region;
wherein the second impurity implantation region is positioned at one side of the first impurity implantation region far away from the substrate;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
Preferably, the Trench MOS device further includes:
the second oxidation layer is formed on the surface of the groove and the surface of the first oxidation layer;
the first metal layer covers the upper surface of the second oxide layer;
and the second metal layer is formed on the lower surface of the substrate.
The positive progress effects of the invention are as follows:
according to the invention, the first impurity (such as phosphorus element) is adopted for deposition, the deposition layer is treated by high-temperature annealing, and the first impurity in the deposition layer is diffused into the substrate to form the diffusion layer, so that the channel length is reduced under the condition of not influencing the body junction depth, the on-resistance of a Trench MOS device is effectively reduced, the reverse characteristic of the device is not influenced, and the reliability of the device is further ensured; the body regions are prevented from being connected into a whole, so that the Trench MOS device is started; in addition, there is an advantage that the cost is not increased.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a Trench MOS device.
Fig. 2 shows a first structure formed during the fabrication process of the Trench MOS device.
Fig. 3 shows a second structure formed during the fabrication process of the Trench MOS device.
Fig. 4 shows a third structure formed during the manufacturing process of the Trench MOS device.
Fig. 5 shows a fourth structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 6 shows a fifth structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 7 shows a sixth structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 8 shows a seventh structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 9 shows an eighth structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 10 shows a ninth structure formed during the manufacturing process of the Trench MOS device manufacturing method.
Fig. 11 shows a tenth structure formed in the manufacturing process of the Trench MOS device manufacturing method.
Fig. 12 shows an eleventh structure formed during the fabrication process of the Trench MOS device.
Fig. 13 is a schematic structural diagram of a Trench MOS device.
Fig. 14 is a schematic diagram of a corresponding relationship between an output voltage and a drain current of a Trench MOS device.
Fig. 15 is a schematic diagram of a corresponding relationship between drain current and on-resistance of a Trench MOS device.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the method for manufacturing a Trench MOS device of the present embodiment includes:
s101, providing a substrate (shown in figure 2);
s102, etching one surface of the substrate to form a groove (as shown in figure 3);
s103, forming a first oxide layer (shown in figure 4) on the surface of the substrate and in the groove, wherein the first oxide layer is a gate oxide layer and plays an isolation role;
s104, depositing on the surface of the first oxide layer to form a deposition layer (as shown in FIG. 5);
wherein the deposition layer includes a first impurity;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate;
when the first impurity is an N-type impurity, the impurity type corresponding to the substrate is also an N-type impurity, namely the Trench MOS device corresponds to an NMOS (N-type metal-oxide-semiconductor field effect transistor);
when the first impurity is a P-type impurity, the impurity type corresponding to the substrate is also a P-type impurity, that is, the Trench MOS device corresponds to a PMOS (P-type metal-oxide-semiconductor field effect transistor).
S105, adopting high-temperature annealing treatment on the deposition layer to diffuse the first impurities in the deposition layer into the substrate to form a diffusion layer (as shown in FIG. 6);
specifically, the first impurity includes a phosphorus element.
Carrying out high-temperature treatment on the deposition layer for a first set time by adopting a first set temperature, carrying out annealing treatment on the deposition layer for a second set time by adopting a second set temperature, and diffusing phosphorus in the deposition layer into the substrate to form a diffusion layer;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
For example, high temperature treatment at 1150 ℃ for 100min may be employed; and adopting 950 ℃ for 100min to carry out annealing treatment, and diffusing the phosphorus element in the deposited layer into the substrate to form a diffusion layer.
S106, etching away the part of the deposition layer except the part positioned in the groove (as shown in FIG. 7);
s107, adopting impurity injection to the diffusion layer and the substrate to form an impurity injection region;
wherein, the impurity injection regions are respectively positioned at two sides of the groove.
Specifically, as shown in fig. 8, a first impurity implantation region is formed by performing second impurity implantation on the diffusion layer and the substrate;
as shown in fig. 9, a second impurity implantation region is formed in the first impurity implantation region by the first impurity implantation;
wherein the second impurity implantation region is positioned at one side of the first impurity implantation region far away from the substrate;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
For example, the diffusion layer and the substrate may be implanted with P-type impurities under the condition of B/300KeV/1.2E13 to form a first impurity implantation region, and the annealing treatment may be performed at 1000 ℃ for 20min, and the second impurity implantation region may be formed with the first impurity implantation in the first impurity implantation region under the condition of P/60KeV/5E 15.
The execution sequence of step S106 and step S107 can be replaced, and the specific execution sequence is determined according to actual situations.
S108, forming a second oxide layer on the surface of the groove and the first oxide layer (as shown in figure 10);
s109, etching the second oxide layer and the second impurity injection region to form a contact hole (as shown in FIG. 11);
wherein, each contact hole is respectively positioned at the outer side of the second impurity injection region;
s1010, forming a first metal layer in the contact hole and on the upper surface of the second oxide layer, and forming a second metal layer on the lower surface of the substrate (as shown in fig. 12), thereby forming a Trench MOS device.
In the embodiment, the first impurity is adopted for deposition, the deposition layer is subjected to high-temperature annealing treatment, and the first impurity in the deposition layer is diffused into the substrate to form the diffusion layer, so that the channel length is reduced under the condition of not influencing the body junction depth, the on-resistance of a Trench MOS device is effectively reduced, the reverse characteristic of the device is not influenced, and the reliability of the device is further ensured; the body regions are prevented from being connected into a whole, so that the Trench MOS device is started; in addition, there is an advantage that the cost is not increased.
Example 2
The Trench MOS device of the present embodiment is obtained by using the method for manufacturing the Trench MOS device of embodiment 1.
As shown in fig. 13, the Trench MOS device of the present embodiment includes:
a substrate 1;
a trench 2 formed on one surface of the substrate 1;
a first oxide layer 3 formed on the surface of the substrate 1 and in the trench 2;
depositing a layer 4 formed and filled in the trench 2;
wherein, the deposition layer 4 comprises first impurities;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate 1;
and a diffusion layer 5 formed between the first oxide layer and the substrate and formed by diffusing the first impurity in the deposition layer by applying a high-temperature annealing process to the deposition layer.
Specifically, the diffusion layer is formed by performing high-temperature treatment on the deposition layer at a first set temperature for a first set time, and then performing annealing treatment on the deposition layer at a second set temperature for a second set time;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
For example, high temperature treatment at 1150 ℃ for 100min may be employed; and adopting 950 ℃ for 100min to carry out annealing treatment, and diffusing the phosphorus element in the deposited layer into the substrate to form a diffusion layer.
An impurity implantation region formed by implanting impurities into the diffusion layer and the substrate 1;
wherein, the impurity injection regions are respectively positioned at two sides of the trench 2.
Specifically, the impurity implantation region includes a first impurity implantation region 6 and a second impurity implantation region 7;
a first impurity implantation region 6 formed by implanting a second impurity into the diffusion layer 5 and the substrate 1;
a second impurity implantation region 7 formed by implanting the first impurity into the first impurity implantation region 6;
wherein, the second impurity implantation region 7 is positioned at one side of the first impurity implantation region 6 far away from the substrate 1;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
A second oxide layer 8 formed on the surfaces of the trench 2 and the first oxide layer 3;
a first metal layer 9 covering the upper surface of the second oxide layer 8;
and a second metal layer 10 formed on the lower surface of the substrate 1.
Taking a 20V NMOS as an example, as shown in fig. 14, the horizontal axis represents the output voltage (unit V) of the Trench MOS device, and the vertical axis represents the leakage current (unit nA). The curve a represents a change curve corresponding to the existing Trench MOS device which can be used in normal operation, and the curve b represents a change curve corresponding to the Trench MOS device of this embodiment, so that it can be known that the curve change trends of the two curves are consistent, that is, the curve change trends of the Trench MOS device of this embodiment represent that the Trench MOS device of this embodiment can work normally.
As shown in fig. 15, the abscissa represents the drain current (unit a) and the ordinate represents the on-resistance (unit m Ω). The straight line c represents the on-resistance corresponding to the conventional Trench MOS device capable of being used in normal operation, and the straight line d represents the on-resistance corresponding to the Trench MOS device of this embodiment, so that it can be known that the on-resistance of the Trench MOS device is effectively reduced in this embodiment.
In the embodiment, the first impurity is adopted for deposition, the deposition layer is subjected to high-temperature annealing treatment, and the first impurity in the deposition layer is diffused into the substrate to form the diffusion layer, so that the channel length is reduced under the condition of not influencing the body junction depth, the on-resistance of a Trench MOS device is effectively reduced, the reverse characteristic of the device is not influenced, and the reliability of the device is further ensured; the body regions are prevented from being connected into a whole, so that the Trench MOS device is started; in addition, there is an advantage that the cost is not increased.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (8)

1. A method for manufacturing a Trench MOS device, the method comprising:
s1, providing a substrate;
s2, etching one surface of the substrate to form a groove;
s3, forming a first oxide layer on the surface of the substrate and in the groove;
s4, depositing on the surface of the first oxide layer to form a deposition layer;
wherein the deposited layer includes a first impurity;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate;
s5, performing high-temperature annealing treatment on the deposition layer, and diffusing first impurities in the deposition layer into the substrate to form a diffusion layer;
s6, injecting impurities into the diffusion layer and the substrate to form an impurity injection region;
the impurity injection regions are respectively positioned at two sides of the groove.
2. The method of manufacturing a Trench MOS device as claimed in claim 1, wherein the step S5 includes:
carrying out high-temperature treatment on the deposition layer for a first set time by adopting a first set temperature, carrying out annealing treatment on the deposition layer for a second set time by adopting a second set temperature, and diffusing first impurities in the deposition layer into the substrate to form the diffusion layer;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
3. The method of manufacturing a Trench MOS device as claimed in claim 1, wherein the step S6 includes:
adopting second impurity injection to the diffusion layer and the substrate to form a first impurity injection region;
adopting the first impurity implantation in the first impurity implantation region to form a second impurity implantation region;
wherein the second impurity implantation region is positioned at one side of the first impurity implantation region far away from the substrate;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
4. The method of manufacturing a Trench MOS device as claimed in claim 3, wherein the step S6 is followed by further comprising:
s7, etching off the part of the deposition layer except the part positioned in the groove;
s8, forming a second oxide layer on the surface of the groove and the surface of the first oxide layer;
s9, etching the second oxide layer and the second impurity injection region to form a contact hole;
wherein the contact hole is positioned at the outer side of the second impurity injection region;
and S10, forming a first metal layer in the contact hole and on the upper surface of the second oxidation layer, and forming a second metal layer on the lower surface of the substrate.
5. A Trench MOS device obtained by the method for manufacturing a Trench MOS device according to claim 1, the Trench MOS device comprising:
a substrate;
the groove is formed on one surface of the substrate;
the first oxidation layer is formed on the surface of the substrate and in the groove;
depositing a layer, forming and filling the groove;
wherein the deposited layer includes a first impurity;
the impurity type of the first impurity is consistent with the impurity type corresponding to the substrate;
a diffusion layer formed between the first oxide layer and the substrate, the diffusion layer being formed by performing high-temperature annealing treatment on the deposition layer to diffuse the first impurity in the deposition layer;
an impurity implantation region formed by implanting impurities to the diffusion layer and the substrate;
the impurity injection regions are respectively positioned at two sides of the groove.
6. The Trench MOS device of claim 5, wherein the diffusion layer is formed by high temperature processing the deposited layer at a first set temperature for a first set time period and annealing the deposited layer at a second set temperature for a second set time period;
wherein the value range of the first set temperature is 1100-1200 ℃, and the value range of the first set time is 30-120 min;
the value range of the second set temperature is 900-.
7. The Trench MOS device of claim 1, wherein the impurity implanted region comprises a first impurity implanted region and a second impurity implanted region;
the first impurity implantation region is formed by implanting a second impurity into the diffusion layer and the substrate;
the second impurity implantation region is formed by implanting the first impurity into the first impurity implantation region;
wherein the second impurity implantation region is positioned at one side of the first impurity implantation region far away from the substrate;
when the first impurity is an N-type impurity, the second impurity is a P-type impurity;
when the first impurity is a P-type impurity, the second impurity is an N-type impurity.
8. The Trench MOS device of claim 7, further comprising:
the second oxidation layer is formed on the surface of the groove and the surface of the first oxidation layer;
the first metal layer covers the upper surface of the second oxide layer;
and the second metal layer is formed on the lower surface of the substrate.
CN201910938219.9A 2019-09-30 2019-09-30 Trench MOS device and manufacturing method thereof Active CN110648920B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101877A (en) * 2007-07-20 2008-01-09 哈尔滨工程大学 Method for making groove power semiconductor device
US20100264488A1 (en) * 2009-04-15 2010-10-21 Force Mos Technology Co. Ltd. Low Qgd trench MOSFET integrated with schottky rectifier
CN103855018A (en) * 2012-12-04 2014-06-11 上海华虹宏力半导体制造有限公司 Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches
CN106298891A (en) * 2015-05-14 2017-01-04 北大方正集团有限公司 The preparation method of trench VDMOS device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101877A (en) * 2007-07-20 2008-01-09 哈尔滨工程大学 Method for making groove power semiconductor device
US20100264488A1 (en) * 2009-04-15 2010-10-21 Force Mos Technology Co. Ltd. Low Qgd trench MOSFET integrated with schottky rectifier
CN103855018A (en) * 2012-12-04 2014-06-11 上海华虹宏力半导体制造有限公司 Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches
CN106298891A (en) * 2015-05-14 2017-01-04 北大方正集团有限公司 The preparation method of trench VDMOS device

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