CN110635032A

CN110635032A - Process method of RRAM resistive switching structure lower electrode

Info

Publication number: CN110635032A
Application number: CN201910914898.6A
Authority: CN
Inventors: 唐优青; 张志刚
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2019-12-31
Anticipated expiration: 2039-09-26
Also published as: CN110635032B

Abstract

The invention provides a process method of RRAM resistive structure bottom electrode, the invention adopts the method of changing the lattice structure, on the basis of changing the program of depositing TiN into multiple deposition, insert a thin layer of Ti between each layer of TiN, block the growth of TiN lattice, and in the TiN, Ti layers formed alternately in turn, the method of changing the flow proportion of N2, Ar and power supply power in the deposition process condition is used to change the different lattice structures of adjacent TiN layers in the alternately formed TiN, Ti layers, the TiN layer with the existing lattice structure is used on the top TiN layer, which not only avoids the influence of changing TiN lattice to the whole device, but also obtains better filled TiN and bottom electrode TiN without disc phenomenon after CMP.

Description

Process method of RRAM resistive switching structure lower electrode

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a process method of a lower electrode of a RRAM resistive switching structure.

Background

A Resistive Random-Access Memory (RRAM) is a Memory resistor that can still memorize charges after power is turned off, but at the same time, transfer data quickly, and is considered as a fourth element of a circuit, because the resistance of a material changes between a high resistance state and a low resistance state according to different voltages applied to a metal oxide, so as to open or block a current channel.

The RRAM is a key structure, namely a resistance change material structure, and a TiN/TaO/Ta/TiN structure is used, and the device realizes reversible conversion between a high resistance state and a low resistance state by forming and breaking a conductive channel under positive voltage and negative voltage, so that data can be stored. In this way, in the key structure of the front-stage process, the lower electrode is formed by filling a through hole (Via) with TiN and then performing Chemical Mechanical Polishing (CMP), but the pressure (stress) of the TiN film increased by a bias voltage (Bia power) and an electromagnetic field formed on the sidewall of the cavity (chamber) is very high, which causes a crack (crack) to the through hole (Via) at the bottom, while the TiN using a normal Physical Vapor Deposition (PVD) plate process has insufficient filling capability, as shown in fig. 1, fig. 1 shows an electron microscope picture that the TiN in the lower electrode of the existing RRAM resistance change structure does not completely fill the bottom of the through hole; as can be seen from fig. 1, although the via hole at the bottom has no cracks, TiN is not completely filled in, there are very obvious voids, and TiN grows in a cluster-like lattice. Referring to FIG. 2, FIG. 2 is a schematic electron microscope image of the polished bottom electrode of FIG. 1 showing dishing.

The prior art attempts to break the cluster-like growth state of TiN and fill the via hole by modifying the deposition process into multiple depositions and adding N2 in the middle, as shown in fig. 3, the TiN is denser and better filled morphology can be obtained, but since the slurry in CMP easily infiltrates along the direction of the crystal lattice, no void is formed after CMP (as shown in fig. 4), but dishing phenomenon occurs.

Therefore, a new method for manufacturing a lower electrode of a RRAM resistive switching structure is needed to solve the above problems.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a lower electrode of a RRAM resistive random access structure, which is used to solve the problems that in the prior art, a hole exists due to incomplete TiN filling of the lower electrode of the RRAM resistive random access structure, and the performance of a device is affected due to a dishing phenomenon after grinding because TiN grows in a cluster lattice.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing a lower electrode of a RRAM resistive random structure, the method at least comprising the following steps: providing a through hole structure for forming a lower electrode of an RRAM resistive switching structure; step two, alternately forming a plurality of TiN layers and Ti layers in sequence to fill and cover the through hole structure; the Ti layer of each layer has a thickness smaller than that of the TiN layer adjacent thereto, and the adjacent TiN layers formed have lattice structures different from each other; step three, forming a top TiN layer on the Ti layer of the topmost layer formed alternately; and step four, grinding the top TiN layer to be flat.

Preferably, the through hole structure in the first step includes a through hole and silicon carbonitride containing structures on two sides of the through hole, the bottom of the through hole is made of metal copper, and two sides of the metal copper are made of ultra-low dielectric constant materials.

Preferably, in the second step, the plurality of TiN layers and Ti layers are formed alternately in sequence by a deposition method.

Preferably, the deposition method is a physical vapor deposition method.

Preferably, the physical vapor deposition method is a PVD sputtering plate process.

Preferably, 3 to 7 TiN layers and Ti layers are formed alternately in sequence in the second step.

Preferably, 3 TiN layers and Ti layers are formed alternately in sequence in the second step.

Preferably, in the plurality of TiN layers and Ti layers alternately formed in sequence in the second step, the thickness of each TiN layer is 100 angstroms; each Ti layer was 50 angstroms thick.

Preferably, in the second step, the adjacent TiN layers with different lattice structures are formed by controlling the flow ratio of Ar to N2 in the physical vapor deposition process.

Preferably, in the process of alternately forming the TiN layers in the second step, the proportion of N2 to the sum of N2 and Ar is 30% to 80%.

Preferably, in the second step, the adjacent TiN layers with different lattice structures are formed by controlling the power supply power in the physical vapor deposition process.

Preferably, the power supply power in the physical vapor deposition process of step two is 1000W to 12000W.

Preferably, the thickness of the top TiN layer formed in step three is 100 angstroms.

Preferably, in step four, the top TiN layer is planarized by chemical mechanical polishing.

As described above, the process method of the lower electrode of the RRAM resistive random access structure of the present invention has the following beneficial effects: the invention adopts a method of changing lattice structure, changes the program of depositing TiN into the foundation of depositing for a plurality of times, inserts a thin Ti layer between each TiN layer to block the growth of TiN lattice, and in the TiN and Ti layers formed in turn, changes the different lattice structures of the adjacent TiN layers in the TiN and Ti layers formed alternately by changing the flow ratio of N2 and Ar and the power supply power in the deposition process conditions, and uses the TiN layer with the existing lattice structure on the top TiN layer, thereby not only avoiding the influence of changing TiN lattice on the whole device, but also obtaining the lower electrode TiN which is better filled with TiN and has no disc-shaped phenomenon after CMP.

Drawings

Fig. 1 is an electron microscope image of a conventional RRAM resistive switching structure lower electrode in which TiN does not completely fill the bottom of a through hole;

FIG. 2 is an electron microscope photograph showing dishing of the lower electrode of FIG. 1 after polishing;

FIG. 3 is an electron microscope image showing the filling effect of the bottom electrode after the cluster lattice growth state is broken by TiN deposition for many times in the prior art;

FIG. 4 is an electron microscope photograph showing dishing of the lower electrode of FIG. 3 after polishing;

FIG. 5 is a schematic structural view of 3 alternately formed TiN layers and Ti layers in the lower electrode of the present invention;

FIG. 6 is a schematic structural view showing the formation of a top TiN layer on 3 alternately formed TiN layers and Ti layers in the present invention;

FIG. 7 is a schematic view showing a lattice structure between 3 TiN layers in the present invention;

fig. 8 is a schematic view showing a lattice structure between two adjacent TiN layers in the present invention;

fig. 9 is a flow chart of a process method of the lower electrode of the RRAM resistive switching structure according to the present invention;

fig. 10 and 11 show PVD process conditions for forming TiN in a lower electrode of a RRAM resistive switching structure in the prior art.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 5 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The invention provides a process method of an RRAM resistive switching structure lower electrode, a process flow chart of the process method is shown in figure 9, and the process method comprises the following steps:

providing a through hole structure for forming a lower electrode of an RRAM resistive switching structure; further, as shown in fig. 5, in the first step, the via structure includes a via and silicon carbonitride containing structures (NDC) on both sides of the via, the bottom of the via is copper metal (Gu), and both sides of the copper metal are ultra low dielectric constant materials (ULK). That is, as shown in fig. 5, the metal copper and the ultra-low dielectric constant material (ULK) on both sides thereof are located at the lowest layer in the structure of fig. 5, an NDC layer is formed on the copper layer and the ultra-low dielectric constant material (ULK), and then the NDC layer is etched to form the via hole, and the RRAM lower electrode of the present invention is formed by alternately filling the via hole structure with TiN and Ti in the subsequent steps and then performing Chemical Mechanical Polishing (CMP).

Step two, alternately forming a plurality of TiN layers and Ti layers in sequence to fill and cover the through hole structure; the Ti layer of each layer has a thickness smaller than that of the TiN layer adjacent thereto, and the adjacent TiN layers formed have lattice structures different from each other; as shown in fig. 5, in step two, the through hole is filled with a TiN layer 010, then a Ti layer 02 is formed on the TiN layer 010, then a TiN layer 011 is formed on the Ti layer 02, then a Ti layer 02 is formed on the TiN layer 011, then a TiN layer 012 is formed on the Ti layer 02, then a Ti layer 02 is formed on the TiN layer 012, and so on, a laminated structure of TiN layers and Ti layers is formed, which is partially filled in the through hole and partially covered on the through hole structure, and is partially covered on the through hole and NDC on both sides of the through hole as shown in fig. 5.

In the second step of the present invention, the plurality of TiN layers and Ti layers are formed alternately in sequence by a deposition method. In a further aspect of the present invention, the deposition method in step two is a physical vapor deposition method. In this embodiment, the physical vapor deposition method is a PVD sputtering flat process. The deposition process of alternately forming the TiN layers of the plurality of TiN layers and Ti layers in the invention is as follows: and bombarding the target material by using Ar Plasma (Plasma) to drop on the wafer, and introducing nitrogen N2 to form Plasma which reacts with N2 Plasma to generate TiN.

Preferably, in the second step of the present invention, 3 to 7 TiN layers and Ti layers are formed alternately in sequence. That is, one layer of TiN and one layer of Ti constitute one laminated structure, and the present invention constitutes a total of 3 to 7 of the laminated structures. As shown in fig. 5, in the second step of this embodiment, 3 TiN layers and Ti layers are formed alternately in sequence. I.e. 3 of said stacked structures are comprised in this embodiment.

Preferably, in the plurality of TiN layers and Ti layers alternately formed in sequence in the second step, the thickness of each TiN layer is 100 angstroms; each Ti layer was 50 angstroms thick. That is, the thickness of each of the

TiN layers

010, 011 and 012 in the embodiments is 100 angstroms, and the thickness of each Ti layer among the

TiN layers

010, 011 and 012 is 50 angstroms.

The invention further forms the adjacent TiN layers with different crystal lattice structures by controlling the flow ratio of Ar and N2 in the physical vapor deposition process in the second step. In a further aspect of the present invention, in the process of alternately forming the TiN layer in the second step, the flow ratio of N2 to the sum of N2 and Ar is 30% to 80%, that is, N2: (N2+ Ar) ═ 30% to 80%, that is, in the process of forming the TiN layer 010, TiN layer 011, and TiN layer 012, the flow rate ratio of N2 to the sum of N2 and Ar is controlled in the range of 30% to 80%, and in this embodiment, since the lattice structures of the adjacent two TiN layers are required to be different in this step, by adjusting the flow rate ratio of N2 to the sum of N2 and Ar to be different in the range of 30% to 80%, the TiN layer 010 and TiN layer 011 of different lattice structures, and the TiN layer 011 and TiN layer 012 of different lattice structures are formed.

According to the invention, the flow ratio of N2 and the sum of N2 and Ar can be adjusted by controlling the power supply power in the physical vapor deposition process to form the adjacent TiN layers with different lattice structures. Furthermore, the power supply power in the physical vapor deposition process of the second step is 1000W to 12000W. In the invention, different lattice structures of adjacent TiN layers can be realized by combining one or two means. Namely, adjacent TiN layers with different crystal lattice structures are formed only by adjusting the flow ratio of N2 to the sum of N2 and Ar within the range of 30-80%, or adjacent TiN layers with different crystal lattice structures are formed only by controlling the power supply in the physical vapor deposition process, or the two means are combined with each other.

Step three, forming a top TiN layer on the Ti layer of the topmost layer formed alternately; as shown in fig. 6, fig. 6 is a schematic structural view showing that top TiN layers are formed on 3 alternating TiN layers and Ti layers in the present invention, and the top TiN layer 03 is formed on the Ti layer on the TiN layer 012, and further, the thickness of the top TiN layer 03 formed in the third step is 100 angstroms. And the top TiN layer is formed by adopting the conditions of the physical vapor deposition process in the process method for forming the lower electrode of the RRAM resistive switching structure in the prior art, so as to avoid the influence of changing the crystal lattice of the top TiN layer 03 on the whole device, and therefore, the existing crystal lattice structure is used for the top TiN layer 03. As shown in fig. 10 and 11, fig. 10 and 11 show PVD process conditions for forming TiN in a lower electrode of a RRAM resistive switching structure in the related art. The RRAM resistive switching structure lower electrode in the prior art can be formed only by filling a TiN layer in the through hole, the top TiN layer 03 does not exist as the invention because only TiN exists, and the process conditions of the top TiN layer 03 in the invention are equivalent to the process conditions of the prior art for filling the whole TiN layer in the through hole.

And step four, grinding the top TiN layer to be flat. And step four, flattening the top TiN layer by adopting chemical mechanical polishing.

Referring to fig. 7, fig. 7 is a schematic diagram showing the lattice structure between 3 TiN layers in the present invention; the lattice structures of the TiN layers 010, 011 and 012 shown in fig. 7 are different from each other, and the circular marked area in fig. 7 corresponds to the circular marked area in fig. 5, and the channels which are easy to crack (waak) between the cluster-shaped TiN are separated due to the intersecting bottom deposition of TiN and Ti, and the directions of arrows in fig. 7 indicate the waak channels. In the prior art, due to the fact that the lattice structures of the upper TiN layer and the lower TiN layer are the same, when CMP polishing is conducted, polishing liquid may penetrate into the lower film layer along the waak channel.

As shown in fig. 8, fig. 8 is a schematic diagram showing the lattice structure between two adjacent TiN layers in the present invention. The circular circled area of fig. 8 corresponds to the circular circled area of fig. 6. Because the upper and lower two-layer TiN layer of different lattice structure, the waak channel can not align to can not link up from top to bottom, avoid the grinding fluid to permeate lower floor's rete.

In summary, the present invention adopts a method of changing lattice structure, the program of depositing TiN is changed into multiple depositions, a thin layer of Ti is inserted between each TiN layer to block the growth of TiN lattice, in the TiN and Ti layers formed alternately in sequence, the different lattice structures of adjacent TiN layers in the TiN and Ti layers formed alternately are changed by changing the flow ratio of N2 and Ar and the power supply, the top TiN layer uses the existing lattice structure TiN layer, which not only avoids the influence of changing TiN lattice on the whole device, but also obtains the lower electrode TiN with better filled TiN and without dishing phenomenon after CMP. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

The process method of the RRAM resistive structure lower electrode is characterized by at least comprising the following steps:

providing a through hole structure for forming a lower electrode of an RRAM resistive switching structure;

step two, alternately forming a plurality of TiN layers and Ti layers in sequence to fill and cover the through hole structure; the Ti layer of each layer has a thickness smaller than that of the TiN layer adjacent thereto, and the adjacent TiN layers formed have lattice structures different from each other;

step three, forming a top TiN layer on the Ti layer of the topmost layer formed alternately;

and step four, grinding the top TiN layer to be flat.
2. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: in the first step, the through hole structure comprises a through hole and silicon carbonitride containing structures at two sides of the through hole, the bottom of the through hole is made of metal copper, and two sides of the metal copper are made of ultralow dielectric constant materials.
3. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: and in the second step, the TiN layers and the Ti layers are formed in sequence and alternately by a deposition method.
4. The process method of the RRAM resistive switching structure lower electrode according to claim 3, wherein the process method comprises the following steps: and the deposition method in the second step is a physical vapor deposition method.
5. The process method of the RRAM resistive switching structure lower electrode according to claim 4, wherein the step of forming the RRAM resistive switching structure lower electrode comprises the following steps: the physical vapor deposition method is a PVD sputtering flat plate process.
6. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: and in the second step, 3 to 7 TiN layers and Ti layers are formed in sequence and alternately.
7. The process method of the RRAM resistive switching structure lower electrode according to claim 6, wherein the step of forming the RRAM resistive switching structure lower electrode comprises the following steps: and in the second step, 3 TiN layers and Ti layers are formed in sequence and alternately.
8. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: in the plurality of TiN layers and Ti layers formed alternately in sequence in the second step, the thickness of each TiN layer is 100 angstroms; each Ti layer was 50 angstroms thick.
9. The process method of the RRAM resistive switching structure lower electrode according to claim 4, wherein the step of forming the RRAM resistive switching structure lower electrode comprises the following steps: and in the second step, adjacent TiN layers with different lattice structures are formed by controlling the flow ratio of Ar to N2 in the physical vapor deposition process.
10. The process method of the RRAM resistive switching structure lower electrode according to claim 9, wherein: in the process of alternately forming the TiN layer in the second step, the flow ratio of the N2 to the sum of the N2 and Ar is 30-80%.
11. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: and in the second step, the adjacent TiN layers with different lattice structures are formed by controlling the power supply power in the physical vapor deposition process.
12. The process method for the RRAM resistive switching structure lower electrode according to claim 11, wherein the step of forming the RRAM resistive switching structure lower electrode comprises the following steps: and the power supply power in the physical vapor deposition process in the second step is 1000W to 12000W.
13. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: the thickness of the top TiN layer formed in step three was 100 angstroms.
14. The process method of the RRAM resistive switching structure lower electrode according to claim 1, wherein the process method comprises the following steps: and step four, flattening the top TiN layer by adopting chemical mechanical polishing.