CN110635032B

CN110635032B - Technological method for RRAM resistive structure lower electrode

Info

Publication number: CN110635032B
Application number: CN201910914898.6A
Authority: CN
Inventors: 唐优青; 张志刚
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2023-06-13
Anticipated expiration: 2039-09-26
Also published as: CN110635032A

Abstract

The invention provides a process method for a lower electrode of an RRAM resistance change structure, which adopts a method for changing a lattice structure, changes a program for depositing TiN into a multi-deposition basis, inserts a thin layer of Ti between each layer of TiN to block the growth of TiN lattices, and in the alternately formed TiN and Ti layers in turn, changes different lattice structures of adjacent TiN layers in the alternately formed TiN and Ti layers by changing the flow proportion of N2 and Ar in the deposition process condition and the power supply, uses the existing TiN layer with the lattice structure on the top TiN layer, thereby avoiding the influence of changing the TiN lattices on the whole device, and simultaneously obtaining the lower electrode TiN with better filling and no dishing phenomenon after CMP.

Description

Technological method for RRAM resistive structure lower electrode

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a process method of a lower electrode of an RRAM resistance change structure.

Background

A Resistive Random-Access Memory (RRAM) is a Memory resistor that can store charges after power is turned off, but at the same time transfer data is fast, and is considered as a fourth element of a circuit, in which a resistance of a material is changed between a high resistance state and a low resistance state according to a voltage applied to a metal oxide, thereby opening or blocking a channel of a current, and using this property for storage.

The key structure of RRAM is a resistance change material structure, and a TiN/TaO/Ta/TiN structure is used, and the structure is used for storing data by forming and breaking a conductive channel to realize reversible transition between a high-resistance state and a low-resistance state under positive voltage and negative voltage. In this way, in the key structure of the front-end process, the lower electrode is formed by filling the through hole (Via) with TiN and then performing Chemical Mechanical Polishing (CMP), but the pressure (stress) of the TiN film increased by the bias voltage (biapower) and the electromagnetic field formed on the cavity (chamber) side wall is very high, which can cause cracks (crack) on the bottom through hole (Via), while TiN using the normal Physical Vapor Deposition (PVD) flat plate process is not sufficient in filling capacity, as shown in fig. 1, fig. 1 shows an electron microscope diagram in which TiN does not completely fill the bottom of the through hole in the lower electrode of the conventional RRAM resistive structure; as can be seen from fig. 1, the bottom via hole has no crack, but the TiN is not completely filled with holes, and the TiN grows as a clustered lattice. As shown in fig. 2, fig. 2 is an electron microscope image of the bottom electrode of fig. 1 after being polished.

In the prior art, the program of the deposition process is modified into a plurality of depositions, N2 is added in the middle of the deposition process to try to break the cluster growth state of TiN, so that the through holes are filled, as shown in fig. 3, the TiN is denser, and the better filled morphology can be obtained, but the polishing liquid in CMP is easy to permeate along the direction of crystal lattice, so that no cavity exists after CMP (as shown in fig. 4), but dishing phenomenon exists.

Therefore, a new process method for preparing the bottom electrode of the RRAM resistive structure is needed to solve the above problems.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a process method for forming a bottom electrode of a resistive switching structure of an RRAM, which is used for solving the problems that in the prior art, tiN of the bottom electrode of the resistive switching structure of the RRAM is incompletely filled and has holes, and TiN grows in a cluster lattice, so that dishing phenomenon occurs after grinding and device performance is affected.

To achieve the above and other related objects, the present invention provides a process method of a bottom electrode of a resistive switching structure of an RRAM, the method at least comprising the following steps: step one, providing a through hole structure for forming a lower electrode of the RRAM resistance change structure; sequentially and alternately forming a plurality of TiN layers and Ti layers to fill and cover the through hole structure; the thickness of the Ti layer of each layer is smaller than that of the TiN layer adjacent thereto, and lattice structures of the adjacent TiN layers formed are different from each other; forming a top TiN layer on the Ti layer of the top layer formed alternately; and fourthly, grinding the top TiN layer to be flat.

Preferably, in the first step, the via structure includes a via and carbon-containing silicon nitride structures on both sides thereof, the bottom of the via is metal copper, and both sides of the metal copper are ultra-low dielectric constant materials.

Preferably, in the second step, the TiN layers and the Ti layers are alternately formed in turn by a deposition method.

Preferably, the deposition method is a physical vapor deposition method.

Preferably, the physical vapor deposition method is a PVD sputtering flat plate process.

Preferably, 3 to 7 TiN layers and Ti layers are alternately formed in sequence in the second step.

Preferably, in the second step, 3 TiN layers and Ti layers are alternately formed in sequence.

Preferably, in the second step, the thickness of each TiN layer is 100 angstroms among the TiN layers and the Ti layers alternately formed in turn; each Ti layer was 50 a thick.

Preferably, in the second step, adjacent TiN layers with different lattice structures are formed by controlling the flow ratio of Ar to N2 in the physical vapor deposition process.

Preferably, in the process of alternately forming the TiN layer in the second step, the ratio of N2 to the sum of N2 and Ar is 30% to 80%.

Preferably, in the second step, the adjacent TiN layers with different lattice structures are formed by controlling the power of a power supply in the physical vapor deposition process.

Preferably, the power of the power supply in the physical vapor deposition process of the second step is 1000W to 12000W.

Preferably, the top TiN layer formed in step three has a thickness of 100 angstroms.

Preferably, in the fourth step, chemical mechanical polishing is used to planarize the top TiN layer.

As described above, the process method of the RRAM resistive structure lower electrode has the following beneficial effects: the invention adopts a method for changing the lattice structure, changes the program of depositing TiN into a multi-deposition basis, inserts a thin layer of Ti between each layer of TiN to block the growth of the TiN lattice, and in the TiN and Ti layers which are formed alternately in turn, changes the different lattice structures of adjacent TiN layers in the alternately formed TiN and Ti layers by changing the flow ratio of N2 and Ar in the deposition process condition and the power supply power, and uses the existing lattice structure of the TiN layer on the top TiN layer, thereby avoiding the influence of changing the TiN lattice on the whole device, and simultaneously obtaining better filled TiN and lower electrode TiN without dishing phenomenon after CMP.

Drawings

FIG. 1 is an electron microscope image of a conventional RRAM resistive structure in which TiN does not completely fill the bottom of the via hole;

FIG. 2 is an electron microscope image of the bottom electrode of FIG. 1 after being polished;

FIG. 3 is an electron microscope image showing the filling effect of the lower electrode after the growth state of the clustered lattice is broken by multiple times of TiN deposition in the prior art;

FIG. 4 is an electron microscope image of the bottom electrode of FIG. 3 after being polished to show dishing;

FIG. 5 is a schematic view showing the structure of 3 alternately formed TiN layers and Ti layers in the lower electrode of the present invention;

FIG. 6 is a schematic diagram showing the structure of the formation of a top TiN layer on 3 alternately formed TiN layers, ti layers according to the present invention;

FIG. 7 is a schematic diagram showing the lattice structure between 3 TiN layers according to the present invention;

fig. 8 is a schematic diagram showing a lattice structure between two adjacent TiN layers in the present invention;

FIG. 9 is a flow chart of a process of the bottom electrode of the RRAM resistive structure of the invention;

fig. 10 and 11 show PVD process conditions for forming TiN in the bottom electrode of the RRAM resistive switching structure in the prior art.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 5 to 11. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The invention provides a process method of a lower electrode of an RRAM resistance change structure, wherein a process flow chart of the process is shown in FIG. 9, and the process comprises the following steps:

step one, providing a through hole structure for forming a lower electrode of the RRAM resistance change structure; in the present invention, as shown in fig. 5, the via structure in the first step includes a via and carbon-containing silicon Nitride Structures (NDCs) on both sides thereof, wherein the bottom of the via is copper (Gu), and both sides of the copper are ultra-low dielectric constant materials (ULKs). That is, as shown in fig. 5, the copper metal and the ultra low dielectric constant materials (ULK) on both sides thereof are located at the lowest layer in the structure of fig. 5, an NDC layer is formed on the copper layer and the ultra low dielectric constant materials (ULK), then the NDC layer is etched to form the via hole, and the RRAM lower electrode of the present invention is formed by Chemical Mechanical Polishing (CMP) after the via hole structure is alternately filled with TiN and Ti in the subsequent steps.

Sequentially and alternately forming a plurality of TiN layers and Ti layers to fill and cover the through hole structure; the thickness of the Ti layer of each layer is smaller than that of the TiN layer adjacent thereto, and lattice structures of the adjacent TiN layers formed are different from each other; as shown in fig. 5, i.e., step two, a TiN layer 010 is filled in the via hole, then a Ti layer 02 is formed on the TiN layer 010, then a TiN layer 011 is formed on the Ti layer 02, then a Ti layer 02 is formed on the TiN layer 011, then a TiN layer 012 is formed on the Ti layer 02, then a Ti layer 02 is formed on the TiN layer 012, and so on, a laminated structure of a plurality of TiN layers and Ti layers is formed, the laminated structure is partially filled in the via hole, partially covered on the via hole structure, and partially covered on NDCs on both sides of the via hole as shown in fig. 5.

In the second step, the TiN layers and the Ti layers are alternately formed in turn by a deposition method. In a further aspect of the present invention, the deposition method in the second step is a physical vapor deposition method. The physical vapor deposition method in this embodiment is a PVD sputtering flat plate process. The deposition process of alternately forming the TiN layers in the TiN layers and the Ti layers in the invention is as follows: ti bombards a target material by Ar Plasma (Plasma) to fall on a wafer, and nitrogen N2 is introduced to form Plasma to react with N2 Plasma to generate TiN.

In the present invention, preferably, 3 to 7 TiN layers and Ti layers are alternately formed in sequence in the second step. I.e. one layer of TiN and one layer of Ti constitute one laminated structure, the present invention constitutes a total of 3 to 7 of said laminated structures. As shown in fig. 5, in the second step of this embodiment, 3 TiN layers and Ti layers are alternately formed in sequence. I.e. the present embodiment comprises 3 of said stacked structures.

In the second step, preferably, the thickness of each TiN layer is 100 angstroms among the TiN layers and the Ti layers alternately formed in sequence; each Ti layer was 50 a thick. That is, the thickness of each of the

TiN layers

010, 011, 012 in the embodiment is 100 angstroms, and the thickness of each of the Ti layers between the

TiN layers

010, 011, 012 is 50 angstroms.

In the second step, adjacent TiN layers with different lattice structures are formed by controlling the flow ratio of Ar to N2 in the physical vapor deposition process. In the process of alternately forming the TiN layer in the second step, the flow ratio of the sum of N2 and Ar is 30% to 80%, that is, N2: (n2+ar) =30% to 80%, that is, in the process of forming the

TiN layers

010, 011, 012, the flow ratio of the sum of N2 and Ar is controlled to be in the range of 30% to 80%, and since the lattice structures of the adjacent two TiN layers are required to be different in this step in this embodiment, the

TiN layers

010 and 011 of different lattice structures, and the

TiN layers

011, 012 of different lattice structures are formed by adjusting the flow ratio of the sum of N2 and Ar to be different in the range of 30% to 80%.

In the invention, preferably, the flow ratio of the N2 to the sum of the N2 and Ar can be adjusted by controlling the power of a power supply in a physical vapor deposition process to form adjacent TiN layers with different lattice structures. In the present invention, the power of the power supply in the physical vapor deposition process in the second step is 1000W to 12000W. In the invention, different lattice structures of adjacent TiN layers can be realized by combining one or two of the above means. That is, adjacent TiN layers with different lattice structures are formed only by adjusting the flow ratio of N2 to the sum of N2 and Ar to be different in the range of 30-80%, or the adjacent TiN layers with different lattice structures are formed only by controlling the power of a power supply in a physical vapor deposition process, or the two means are combined with each other.

Forming a top TiN layer on the Ti layer of the top layer formed alternately; as shown in fig. 6, fig. 6 is a schematic diagram showing a structure of forming a top TiN layer on 3 TiN layers and Ti layers alternately formed in the present invention, and forming the top TiN layer 03 on the Ti layer on the TiN layer 012, and further, the thickness of the top TiN layer 03 formed in the third step is 100 a. And the top TiN layer is formed by adopting the condition of physical vapor deposition process in the process method for forming the RRAM resistive-switching structure lower electrode in the prior art, so as to avoid changing the influence of the crystal lattice of the top TiN layer 03 on the whole device, and thus the existing crystal lattice structure is used for the top TiN layer 03. As shown in fig. 10 and 11, fig. 10 and 11 show PVD process conditions for forming TiN in the bottom electrode of the RRAM resistive switching structure in the prior art. The bottom electrode of the RRAM resistive structure in the prior art can be formed only by filling a TiN layer in the through hole, and as the bottom electrode is only TiN, the top TiN layer 03 does not exist, and the process condition of the top TiN layer 03 is equivalent to the process condition of filling the whole TiN layer in the through hole in the prior art.

And fourthly, grinding the top TiN layer to be flat. And fourthly, flattening the top TiN layer by adopting chemical mechanical polishing.

Fig. 7 is a schematic diagram of a lattice structure between 3 TiN layers according to the present invention; the lattice structures in the TiN layers 010, 011, 012 in fig. 7 are different from each other, and the circular ring mark region in fig. 7 corresponds to the circular ring mark region in fig. 5, and the cluster-shaped TiN is broken by the deposition of TiN and Ti at the intersection, and the arrow direction in fig. 7 indicates the well channel. In the prior art, since the lattice structures of the upper and lower TiN are the same, the polishing liquid may infiltrate into the lower film layer along the wet channel during CMP polishing.

As shown in fig. 8, fig. 8 is a schematic diagram showing a lattice structure between two adjacent TiN layers in the present invention. The circle mark region of fig. 8 corresponds to the circle mark region of fig. 6. Because the upper layer and the lower layer of TiN layers with different lattice structures, the well channels cannot be aligned, so that the upper layer and the lower layer cannot be penetrated, and the grinding fluid is prevented from penetrating into the lower layer of film.

In summary, the method of changing the lattice structure is adopted in the invention, the program of depositing TiN is changed into a method of depositing a plurality of times, a thin layer of Ti is inserted between each layer of TiN to block the growth of the TiN lattice, in the TiN and Ti layers which are formed alternately in turn, the different lattice structures of adjacent TiN layers in the alternately formed TiN and Ti layers are changed by changing the flow ratio of N2 and Ar in the deposition process condition and the power supply power, the existing lattice structure of the TiN layer is used at the top TiN layer, thereby avoiding the influence of changing the TiN lattice on the whole device, and simultaneously obtaining better filled TiN and lower electrode TiN without dishing phenomenon after CMP. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

The process method of the RRAM resistive-switching structure lower electrode is characterized by at least comprising the following steps:

step one, providing a through hole structure for forming a lower electrode of the RRAM resistance change structure;

sequentially and alternately forming a plurality of TiN layers and Ti layers to fill and cover the through hole structure; the thickness of the Ti layer of each layer is smaller than that of the TiN layer adjacent thereto, and lattice structures of the adjacent TiN layers formed are different from each other;

forming a top TiN layer on the Ti layer of the top layer formed alternately;

and fourthly, grinding the top TiN layer to be flat.
2. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: in the first step, the through hole structure comprises a through hole and carbon-containing silicon nitride structures on two sides of the through hole, wherein the bottom of the through hole is made of metal copper, and the two sides of the metal copper are made of ultra-low dielectric constant materials.
3. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: and step two, sequentially and alternately forming the TiN layers and the Ti layers by a deposition method.
4. The process method of the RRAM resistive structure lower electrode of claim 3, wherein: the deposition method in the second step is a physical vapor deposition method.
5. The process method of the RRAM resistive structure lower electrode of claim 4, wherein: the physical vapor deposition method is a PVD sputtering flat plate process.
6. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: and step two, forming 3 to 7 TiN layers and Ti layers alternately in sequence.
7. The process method of the RRAM resistive structure lower electrode of claim 6, wherein: and step two, sequentially and alternately forming 3 TiN layers and Ti layers.
8. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: in the second step, the thickness of each TiN layer is 100 angstroms among the plurality of TiN layers and Ti layers which are alternately formed in sequence; each Ti layer was 50 a thick.
9. The process method of the RRAM resistive structure lower electrode of claim 4, wherein: and secondly, forming adjacent TiN layers with different lattice structures by controlling the flow ratio of Ar to N2 in the physical vapor deposition process.
10. The process method of the lower electrode of the RRAM resistive structure of claim 9, wherein the process method comprises the steps of: in the process of alternately forming the TiN layer in the second step, the flow ratio of the sum of N2 and Ar is 30% to 80%.
11. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: and in the second step, adjacent TiN layers with different lattice structures are formed by controlling the power of a power supply in the physical vapor deposition process.
12. The process method of the lower electrode of the RRAM resistive structure of claim 11, wherein the steps of: the power of the power supply in the physical vapor deposition process in the second step is 1000W to 12000W.
13. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: the top TiN layer formed in step three has a thickness of 100 angstroms.
14. The process method of the lower electrode of the RRAM resistive structure of claim 1, wherein the process method comprises the steps of: and fourthly, flattening the top TiN layer by adopting chemical mechanical polishing.