CN113097382B - Method for manufacturing RRAM cell and RRAM cell - Google Patents
Method for manufacturing RRAM cell and RRAM cell Download PDFInfo
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- CN113097382B CN113097382B CN202010018189.2A CN202010018189A CN113097382B CN 113097382 B CN113097382 B CN 113097382B CN 202010018189 A CN202010018189 A CN 202010018189A CN 113097382 B CN113097382 B CN 113097382B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 153
- 239000002184 metal Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 41
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 239000002131 composite material Substances 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 8
- 229910017107 AlOx Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a manufacturing method of an RRAM unit and the RRAM unit, comprising the following steps: forming a BE dielectric layer on a semiconductor substrate; forming a BE hole on the BE dielectric layer, wherein the BE hole is in contact with the semiconductor substrate; forming BE in the BE hole; forming a switching layer over the layer to which the BE belongs; forming a TE layer over the switching layer; making the TE layer into a target size to obtain a TE island; making the switch layer into a target size; forming a low-K dielectric layer on the TE island and the BE dielectric layer; forming a trench on the low-K dielectric layer, wherein the trench extends into the TE island and the size of the trench is smaller than that of the TE; forming a copper wire in the groove; an RRAM cell is obtained. The RRAM cell is made by the method, or the RRAM cell comprises: BE, switch layer, TE and copper wire; the BE is sequentially provided with a switch layer, a TE and a lead; the TE is larger in size than the BE, the TE having a recess, the wire being located on the recess of the TE.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and in particular, to a method for manufacturing an RRAM cell and an RRAM cell.
Background
RRAM (Resistive random access Memory) is one of the emerging memories, and has many advantages compared with a conventional NVM (Non-volatile Memory). The structure of an RRAM cell can BE understood in a simple abstract way as a metal-insulator-metal (MIM) structure with a bottom electrode BE, a switching layer and a top electrode TE. However, the Back End of Line (BEOL) integration process of RRAM cells is always challenged by copper diffusion. Copper diffusion may lead to high leakage currents and dielectric breakdown, thereby further complicating the overall fabrication scheme.
In addition, the prior process has the following problems:
1. special handling is required to control the sidewall leakage of BE and TE;
2. a separate via process is required to enable a damascene connection between two metal layers;
3. the fault tolerance of controlling the depth of the groove on the top electrode TE is small;
4. the TE material (iridium) has a large process difficulty coefficient in a logic device.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide at least a method of manufacturing a RRAM cell and a RRAM cell, which aim to solve the problem of leakage current instability.
To achieve the above and other related objects, one embodiment of the present invention provides a method of manufacturing a RRAM cell, including the steps of:
forming a bottom electrode dielectric layer on a semiconductor substrate;
forming a bottom electrode hole on the bottom electrode dielectric layer, the bottom electrode hole being in contact with the semiconductor substrate;
forming a bottom electrode in the bottom electrode hole;
forming a switching layer over the bottom electrode;
forming a top electrode layer over the switching layer;
manufacturing the top electrode layer into a target size to obtain a top electrode island;
making the switching layer to a target size;
forming a low-K dielectric layer on the top electrode island and the bottom electrode dielectric layer;
forming a trench in said low-K dielectric layer, said trench extending into said top electrode island and said trench having a dimension less than a dimension of said top electrode;
forming a copper wire in the groove;
and obtaining the RRAM unit.
Optionally, the step of forming a bottom electrode hole on the bottom electrode dielectric layer comprises:
and photoetching and etching the bottom electrode dielectric layer to form a bottom electrode hole.
Optionally, the step of forming a bottom electrode in the bottom electrode hole comprises:
depositing a first metal layer on the bottom electrode dielectric layer;
polishing the first metal layer so that the upper surface of the first metal layer is flush with the upper surface of the dielectric layer.
Optionally, the step of making the top electrode layer to a target size to obtain a top electrode island includes:
and forming a protective layer at the position of the top electrode layer where the top electrode needs to be manufactured, and then etching to obtain the top electrode island.
Optionally, the step of forming a trench on the low-K dielectric layer includes:
and photoetching and etching are carried out on the low-K dielectric layer to obtain the groove.
Optionally, the top electrode island is a step-like structure.
Optionally, the minimum size of the top electrode island is: the minimum of the sum of the copper line size and the registration size.
Optionally, the material of the bottom electrode dielectric layer includes: siN or NDC.
Optionally, the material of the first metal layer includes: tiN or Ti.
Optionally, the material of the switch layer includes: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
Optionally, the material of the top electrode layer includes: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
Optionally, the method further comprises the steps of: forming a conductive via in the semiconductor substrate.
To achieve the above and other related objects, one embodiment of the present invention provides a RRAM cell fabricated by the method.
To achieve the above and other related objects, one embodiment of the present invention provides a RRAM cell including:
a bottom electrode, a switching layer, a top electrode and a copper wire;
the bottom electrode is sequentially provided with a switch layer, a top electrode and a lead; the size of the top electrode is larger than that of the bottom electrode, the top electrode is provided with a concave part, and the conducting wire is positioned on the concave part of the top electrode.
Optionally, the wire is a copper wire.
Optionally, the bottom electrode is made of: tiN or Ti.
Optionally, the material of the switch layer includes: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
Optionally, the top electrode is made of: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
According to the technical scheme provided by the embodiment of the invention, the stability of leakage current is ensured due to the asymmetric sizes of the bottom electrode and the top electrode of the prepared RRAM unit, meanwhile, the connection between a copper wire and the top electrode is irrelevant to the depth of a groove, so that the RRAM unit has a larger process boundary, and meanwhile, the adopted materials and processes completely conform to a logic platform, and the compatibility and the stability of the storage unit are improved. In addition, the method provided by the embodiment of the invention can form the RRAM unit by only one extra mask plate, thereby effectively reducing the complexity of the manufacturing scheme.
Drawings
Fig. 1 is a flowchart illustrating a method of manufacturing an RRAM cell according to an embodiment of the invention.
FIG. 2 is a schematic diagram illustrating the formation of a bottom electrode dielectric layer according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating the formation of a bottom electrode hole according to one embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the formation of a first metal layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating bottom electrode polishing according to one embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the formation of a switching layer according to one embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the formation of a second metal layer according to an embodiment of the present invention;
FIG. 8 is a schematic illustration of a photolithography process for forming top electrode islands according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of an etch process for forming top electrode islands according to an embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating the formation of a low-K dielectric layer according to one embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating the formation of a trench in a low-K dielectric layer according to one embodiment of the present invention;
fig. 12 is a schematic diagram illustrating the formation of copper lines according to an embodiment of the invention.
Description of the element reference numerals
| Reference numerals | Name (R) |
| 1 | |
| 2 | Bottom |
| 3 | |
| 4 | Bottom electrode |
| 41 | A |
| 5 | |
| 6 | |
| 7 | |
| 71 | |
| 8 | Low-K dielectric layer |
| 9 | |
| 10 | Conductive vias |
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings are only used for matching the disclosure of the present disclosure, and are not used for limiting the conditions that the present disclosure can be implemented, so that the present disclosure is not technically significant, and any structural modifications, ratio changes or size adjustments should still fall within the scope of the present disclosure without affecting the efficacy and the achievable purpose of the present disclosure. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
As shown in fig. 1 to 12, a method of manufacturing an RRAM cell includes the steps of:
forming a bottom electrode dielectric layer 2 on a semiconductor substrate 1;
forming a bottom electrode hole 3 on the bottom electrode dielectric layer, the bottom electrode hole being in contact with the semiconductor substrate;
forming a bottom electrode 4 in the bottom electrode hole;
forming a switching layer 5 over the layer to which the bottom electrode belongs;
forming a top electrode layer 6 over the switching layer;
making the top electrode layer into a target size to obtain a top electrode island 7;
making the switching layer to a target size;
forming a low-K dielectric layer 8 on the top electrode island and the bottom electrode dielectric layer;
forming a trench in said low-K (K is dielectric constant) dielectric layer, said trench extending into said top electrode island and said trench having a dimension less than a dimension of said top electrode;
forming a copper wire 9 in the groove;
and obtaining the RRAM unit. The RRAM unit includes: bottom electrode 4, switching layer 5, top electrode 71 and copper line 9.
According to the technical scheme provided by the embodiment of the invention, the stability of leakage current is ensured due to the asymmetric size of the bottom electrode and the top electrode of the manufactured RRAM unit, meanwhile, the connection between a copper wire and the top electrode is irrelevant to the depth of a groove, so that the RRAM unit has a larger process boundary, and meanwhile, the adopted materials and processes completely conform to each other, and a logic platform increases the compatibility and the stability of the storage unit. In addition, the method provided by the embodiment of the invention can form the RRAM unit by only one extra mask plate, does not prevent BE/TE side wall leakage through extra processes, and does not have a separate hole opening process flow, thereby effectively reducing the complexity of the manufacturing scheme.
In one embodiment, the step of forming the bottom electrode dielectric layer 2 on the semiconductor substrate 1 includes:
on the semiconductor substrate 1, a bottom electrode dielectric layer 2 is formed by CVD (Chemical Vapor Deposition); the bottom electrode dielectric layer 2 is made of the following materials: siN or NDC (nitrogen doped silicon carbide), the thickness of the bottom electrode dielectric layer is twice the standard thickness of the bottom dielectric layer of the final finished (fabricated RRAM cell).
In one embodiment, the step of forming the bottom electrode hole 3 in the bottom electrode dielectric layer 2 includes:
and photoetching and etching the bottom electrode dielectric layer 2 to form a bottom electrode hole 3, wherein during etching, the etching depth needs to be deep into the semiconductor substrate, namely: the bottom electrode hole 3 is brought into contact with the semiconductor substrate. The mask used in this step is the same as a CT (Contact, connecting portion of device and metal line) mask.
In one embodiment, the step of forming a bottom electrode in the bottom electrode hole comprises:
depositing a first metal layer 41 on the bottom electrode dielectric layer 2; a first metal layer 41 is grown on the bottom electrode dielectric layer 2 by PVD, in which step the BE holes are filled with the first metal without leaving a blank, while the first metal layer also extends over the upper surface of the bottom electrode dielectric layer 2.
And (3) performing CMP (Chemical Mechanical Polishing) on the first metal layer to remove the first metal on the surface, so that the first metal after the upper surface of the first metal layer and the upper surface of the dielectric layer are polished flush and level is completely positioned in the bottom electrode hole 3 to form a bottom electrode 4, wherein the bottom of the bottom electrode 4 is contacted with the semiconductor substrate 1, the periphery of the bottom electrode 4 is a bottom electrode dielectric layer 2, and the bottom electrode 4 is positioned in the bottom electrode dielectric layer 2 to form a layer belonging to the bottom electrode. The bottom electrode layer includes a bottom electrode dielectric layer and a bottom electrode, and the bottom electrode is located in the bottom electrode dielectric layer. After polishing, the thickness of the bottom electrode dielectric layer was 1.5 times the standard thickness of the bottom dielectric layer of the final product (fabricated RRAM cell).
In one embodiment, the material of the first metal layer includes: tiN or Ti.
In one embodiment, the step of forming the switching layer 5 above the layer to which the bottom electrode belongs includes:
a switching layer 5 is formed by PVD (Physical Vapor Deposition) on the bottom electrode layer, and the switching layer is made of materials including: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
In one embodiment, forming the top electrode layer 6 over the switching layer 5 comprises:
forming a second metal layer on the switching layer; and growing a second metal layer through PVD, wherein the thickness of the second metal layer is consistent with that of the hard mask in the patterning process of the copper wire M1.
In one embodiment, the step of forming the top electrode layer 6 to a target size to obtain the top electrode island 7 includes:
and forming a protective layer at the position of the top electrode layer 6 (i.e. the second metal layer) where the top electrode needs to be manufactured, and then etching and stripping the protective layer to obtain a top electrode island 7. The top electrode 71 is larger in size than the bottom electrode 4. The bottom electrode 4 and the top electrode 71 have different sizes, ensuring stability of leakage current. The protective layer can be formed by coating photoresist at the position where the top electrode needs to be manufactured, and then forming the protective layer after exposure; or coating photoresist on the whole second layer of metal, carrying out patterning exposure, and forming a protective layer at the position where the top electrode needs to be manufactured.
In one embodiment, the top electrode island (TE island) has a step structure, and a dimension above the step is smaller than a dimension below the step. In one embodiment, the minimum size of the TE island is: the minimum of the sum of the copper line size and the registration size. The minimum dimension in the top electrode island is the dimension of the top electrode island and is also the dimension of the protective layer.
In one embodiment, the step of forming the switching layer to a target size includes: and etching the switch layer until the size of the switch layer is the target size.
In the above steps, the bottom electrode dielectric layer 2 is also etched while the switch layer 5 is etched, so that the thickness of the bottom electrode dielectric layer 2 is the standard thickness of the bottom dielectric layer of the final product (the manufactured RRAM cell).
In one embodiment, a target size of a bottom of the TE island coincides with a target size of the switching layer.
In one embodiment, the step of forming a low-K dielectric layer on the top electrode island and the bottom electrode dielectric layer comprises growing a layer of low-K dielectric material uppermost by conventional means (PVD or CVD or other means).
In one embodiment, the step of forming a trench in the low-K dielectric layer 8 includes:
and photoetching and etching are carried out on the low-K dielectric layer to obtain the groove. The size of the groove is smaller than that of the top electrode, so that the copper wire completely falls on the top electrode, and the groove extends into the top electrode, and the copper diffusion is effectively prevented. The top electrode 71 having the concave portion can be obtained by this step. The trench extends 3-20nm deep into the top electrode, which can simultaneously compromise contact resistance and barrier to Cu diffusion.
The step of forming a copper line 9 in the trench includes: at the top of the previous step, a layer of copper is grown by conventional means (PVD or other means) so that the trenches are filled with copper, forming copper lines M1. Then, CMP is performed to obtain an RRAM cell.
In one embodiment, the material of the second metal layer includes: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
In one embodiment, the method further comprises the steps of: conductive vias 10 are formed in the semiconductor substrate 1. The conductive via 10 is established below the bottom electrode.
Since the above method is based on an ILD (interlayer dielectric) structure, the low-K dielectric layer is not damaged, so that the process tolerance capability is higher.
By using the method, the logic unit can be manufactured at the periphery of the RRAM unit, and the specific manufacturing process comprises the following steps: in the step of etching the switch layer, the bottom dielectric and the bottom electrode around the RRAM cell are etched away until the semiconductor substrate 1 is exposed, then a low-K dielectric layer is formed above along with the step of forming the low-K dielectric layer (the low-K dielectric layer is contacted with the semiconductor substrate in the logic cell), in the step of manufacturing a trench, a trench is formed above the semiconductor substrate in the logic cell, the trench is fully covered with copper wires along with the formation of the copper wires, and a conductive through hole is obtained below the trench along with the formation of the conductive through hole, so that a peripheral logic cell is obtained.
To achieve the above and other related objects, one embodiment of the present invention provides a RRAM cell fabricated by the method.
According to the RRAM unit manufactured by the method, the bottom electrode and the top electrode which are not symmetrical in size are obtained, so that the stability of leakage current is guaranteed, meanwhile, the connection between a copper wire and the top electrode is irrelevant to the depth of a groove, so that the RRAM unit has a larger process boundary, and meanwhile, the adopted materials and the process completely conform to each other, and a logic platform increases the compatibility and the stability of a storage unit. In addition, the method provided by the embodiment of the invention can form the RRAM unit by only needing one additional mask plate, thereby effectively reducing the complexity of the manufacturing scheme.
To achieve the above and other related objects, one embodiment of the present invention provides a RRAM cell including:
a bottom electrode, a switching layer, a top electrode and a copper wire;
the bottom electrode is sequentially provided with a switch layer, a top electrode and a lead; the size of the top electrode is larger than that of the bottom electrode, the top electrode is provided with a concave part, and the conducting wire is positioned on the concave part of the top electrode.
In one embodiment, the wire is a copper wire.
In one embodiment, the bottom electrode is made of: tiN or Ti.
In one embodiment, the material of the switching layer includes: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
In one embodiment, the top electrode is made of: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
The asymmetric bottom electrode and the top electrode in size ensure the stability of leakage current, and meanwhile, the connection between the copper wire and the top electrode is independent of the depth of the groove, so that the copper wire and the top electrode have larger process boundary, and meanwhile, the adopted materials and the process completely conform to the logic platform, and the compatibility and the stability of the memory cell are improved. In addition, the method provided by the embodiment of the invention can form the RRAM unit by only one extra mask plate, thereby effectively reducing the complexity of the manufacturing scheme.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (18)
1. A method of manufacturing an RRAM cell, comprising the steps of:
forming a bottom electrode dielectric layer on a semiconductor substrate;
forming a bottom electrode hole on the bottom electrode dielectric layer, the bottom electrode hole being in contact with the semiconductor substrate;
forming a bottom electrode in the bottom electrode hole;
forming a switching layer over the bottom electrode;
forming a top electrode layer over the switching layer;
making the top electrode layer into a target size to obtain a top electrode island, wherein the size of the top electrode island is larger than that of the bottom electrode;
making the switching layer to a target size;
forming a low-K dielectric layer on the top electrode island and the bottom electrode dielectric layer;
forming a trench in said low-K dielectric layer, said trench extending into said top electrode island and said trench having a dimension less than a dimension of said top electrode;
forming a copper wire in the groove;
and obtaining the RRAM unit.
2. The method of claim 1, wherein the step of forming a bottom electrode hole in the bottom electrode dielectric layer comprises:
and photoetching and etching the bottom electrode dielectric layer to form a bottom electrode hole.
3. The method of claim 1, wherein the step of forming a bottom electrode in the bottom electrode hole comprises:
depositing a first metal layer on the bottom electrode dielectric layer;
performing CMP on the first metal layer so that an upper surface of the first metal layer is flush with an upper surface of the dielectric layer.
4. The method of claim 1, wherein the step of forming the top electrode layer to a target size to obtain a top electrode island comprises:
and forming a protective layer at the position of the top electrode layer where the top electrode needs to be manufactured, and then etching to obtain the top electrode island.
5. The method of claim 1, wherein the step of forming a trench in the low-K dielectric layer comprises:
and photoetching and etching are carried out on the low-K dielectric layer to obtain the groove.
6. The method of manufacturing an RRAM cell as claimed in claim 1, wherein the top electrode island is a step-like structure.
7. The method of claim 1 or 6, wherein the top electrode island has a minimum dimension of: the minimum of the sum of the copper line size and the registration size.
8. The method of claim 1, wherein the bottom electrode dielectric layer comprises: siN or NDC.
9. The method of claim 3, wherein the first metal layer comprises: tiN or Ti.
10. The method of claim 3, wherein the switching layer comprises: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
11. The method of claim 1, wherein the top electrode layer comprises: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
12. The method of manufacturing an RRAM cell as claimed in claim 1, further comprising the steps of: forming a conductive via in the semiconductor substrate.
13. An RRAM cell produced by the method of any one of claims 1 to 12.
14. A RRAM cell, comprising:
the device comprises a substrate, a bottom electrode, a switch layer, a top electrode and a lead;
a bottom electrode dielectric layer is arranged on the substrate, a bottom electrode hole is formed in the bottom electrode dielectric layer, the bottom electrode is positioned in the bottom electrode hole, and a switch layer, a top electrode and a lead are sequentially arranged on the bottom electrode hole; the top electrode and the side face of the conducting wire are surrounded by the dielectric layer; the top electrode has a size greater than a size of the bottom electrode.
15. The RRAM cell of claim 14, wherein the wire is a copper wire.
16. The RRAM cell of claim 14 or 15, wherein the bottom electrode comprises: tiN or Ti.
17. The RRAM cell of claim 14 or 15, wherein the material of the switching layer comprises: taOx or AlOx or HfOx; the thickness of the switch layer is 10-50 angstroms.
18. The RRAM cell of claim 14 or 15, wherein the top electrode comprises: ti or TiN or a composite metal; the composite metal includes: al and TiN or W and TiN.
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