CN217903116U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The utility model discloses a semiconductor memory device, it includes substrate, bit line and resistance structure. The substrate includes an active region and a plurality of insulating regions. The resistor structure is arranged on the insulating region and sequentially comprises a first semiconductor layer and a first cover layer from bottom to top. The bit line is arranged on the substrate and crosses the active region and the insulating region, and the bit line further comprises a second semiconductor layer, a first barrier layer, a first conductive layer and a second cover layer from bottom to top in sequence. The first semiconductor layer and the second semiconductor layer have top surfaces which are flush with each other and are made of the same semiconductor material. Therefore, the resistor with both structure reliability and stable surface resistance value can be formed on the premise of simplifying the manufacturing process.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device.

Background

With the current semiconductor technology level, the control circuit, the access device, the low voltage operating circuit, and the high voltage operating circuit can be integrated and fabricated on a single chip, thereby reducing the cost and improving the operating performance. In addition, as the size of semiconductor devices is reduced, the fabrication steps of transistors, accessors, resistors and other devices are improved to produce high quality semiconductor devices with small size. However, as the size of devices is continuously reduced, it is more difficult to simultaneously dispose multiple semiconductor devices on the same device, and the fabrication process thereof also faces many limitations and challenges. Therefore, further improvement is needed in the prior art to effectively improve the efficiency of the manufacturing process and further improve the performance and reliability of the device.

Disclosure of Invention

An object of the present invention is to provide a semiconductor memory device, which can simultaneously set a memory and a resistor on the same device, and further can form a resistor with a reliable structure and a stable surface resistance value on the premise of simplifying the manufacturing process.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate, a bit line, and a resistor structure. The substrate includes an active region and a plurality of insulating regions. The resistor structure is arranged on the insulating region, and further comprises a first semiconductor layer, a first cover layer arranged on the first semiconductor layer and a first gap wall. The first spacer is in direct physical contact with sidewalls of the first semiconductor layer and the first cap layer. Bit lines are disposed on the substrate and cross over the active regions and the insulating regions. The bit line further includes a second semiconductor layer, a first barrier layer disposed on the second semiconductor layer, a first conductive layer disposed on the first barrier layer, a second cap layer disposed on the first conductive layer, and a second spacer, wherein the second spacer is in direct physical contact with sidewalls of the second semiconductor layer, the first barrier layer, the conductive layer, the second cap layer, and the second spacer.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device, which includes a substrate, a bit line, and a resistor structure. The substrate includes an active region and a plurality of insulating regions. The resistor structure is arranged on the insulating region and sequentially comprises a first semiconductor layer and a first cover layer from bottom to top. The bit line is arranged on the substrate and crosses the active region and the insulating region, and the bit line sequentially comprises a second semiconductor layer, a first barrier layer, a first conductive layer and a second cover layer from bottom to top. The first semiconductor layer and the second semiconductor layer have mutually flush top surfaces and the same semiconductor material.

Compared with the prior art, the method has the following beneficial effects:

the utility model discloses a set up memory and resistor simultaneously on same device, namely, can set up resistance structure, bit line structure and gate line structure in different regions respectively, wherein, resistance structure comprises the first semiconductor layer that partly is the same with the bit line structure, not only has good structure reliability, and can also reach relatively higher, and stable surface resistance value, and then can form the resistor that has structure reliability and stable surface resistance value concurrently under the prerequisite of simplifying manufacturing process; the utility model discloses a semiconductor memory device wholly has comparatively optimized device efficiency.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

Fig. 2 to 9 are schematic diagrams illustrating steps of a method for forming a semiconductor memory device according to an embodiment of the present invention, wherein:

FIG. 2 is a cross-sectional view of a semiconductor memory device after forming contact openings;

FIG. 3 is a cross-sectional view of a semiconductor memory device after forming a semiconductor material layer;

FIG. 4 is a schematic cross-sectional view of a semiconductor memory device after forming a mask layer;

FIG. 5 is a cross-sectional view of a semiconductor memory device after forming bit line contacts;

FIG. 6 is a cross-sectional view of a semiconductor memory device after forming a capping material layer;

FIG. 7 is a cross-sectional view of a semiconductor memory device after forming a mask layer;

FIG. 8 is a cross-sectional view of a semiconductor memory device after a patterning process; and

fig. 9 is a cross-sectional view of a semiconductor memory device after spacer formation.

Wherein the reference numerals are as follows:

10. semiconductor memory device with a plurality of memory cells

10A first region

10B second region

10C third region

11. Resistor structure

12. Bit line structure

13. Gate line structure

100. Substrate

101. 102, 103 insulating region

110. Dielectric layer

111. First silicon oxide layer

113. Silicon nitride layer

115. Second silicon oxide layer

120. Layer of semiconductor material

120a contact opening

121. First semiconductor layer

122. A second semiconductor layer

123. Third semiconductor layer

130. A first covering material layer

131. First cap layer

140. Layer of conductive material

141. Mask pattern

142. Bit line contact

150. Barrier material layer

152. The first barrier layer

153. The second barrier layer

160. Layer of conductive material

162. First conductive layer

163. Second conductive layer

170. Second cover material layer

172. Second cap layer

173. Third cap layer

181. First spacer

182. Second spacer

183. Third spacer

201. First mask layer

202. 203 second mask layer

210. Interlayer dielectric layer

220. Intermetal dielectric layer

231. 232, 233 plug

233a, 233b plug

Thickness of T1

Detailed Description

In order to further understand the present invention, the following description specifically exemplifies preferred embodiments of the present invention and describes the constituent elements and intended functions of the present invention in detail with reference to the attached drawings. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present invention.

Referring to fig. 1, a cross-sectional view of a semiconductor memory device 10 according to an embodiment of the present invention is shown. The semiconductor memory device 10 includes a substrate 100, such as a silicon substrate (silicon substrate), an epitaxial silicon substrate (epitaxial silicon substrate), or a Silicon On Insulator (SOI) substrate, wherein the substrate 100 includes a plurality of insulating regions 101, 102, 103, such as Shallow Trench Isolation (STI), and a plurality of active regions (not shown) are further defined in the substrate 100. The substrate 100 includes at least three regions, a first region 10A, a second region 10B, and a third region 10C, for disposing different semiconductor devices, respectively, and the insulation regions 101, 102, 103 are disposed in the first region 10A, the second region 10B, and the third region 10C, respectively. In the present embodiment, the first region 10A is, for example, a resistance region, in which a resistance structure 11 is disposed, the second region 10B is, for example, a memory region, in which at least a Bit Line (BL) structure 12 is disposed, and the third region 10C is, for example, a transistor region, in which a gate line structure 13 is disposed, but not limited thereto. For those skilled in the art, the first region 10A, the second region 10B and the third region 10C may be directly adjacent to each other, or other regions may be further disposed, for example, a peripheral region (not shown) may be additionally disposed between the second region 10B and the third region 10C, but not limited thereto.

As shown in fig. 1, the resistive structure 11 is disposed on the insulating region 101, and a dielectric layer 110 is disposed between the resistive structure 11 and the insulating region 101. The detailed portion of the resistor structure 11 includes the first semiconductor layer 121 and the first cap layer 131 sequentially disposed from bottom to top, and further includes a first spacer 181, it is noted that the first spacer 181 is directly disposed on the top surface of the dielectric layer 110 and physically contacts the sidewalls of the first semiconductor layer 121 and the first cap layer 131 of the resistor structure 11, as shown in fig. 1. The dielectric layer 110 covers the active region and the insulating regions 101 and 102 simultaneously, and preferably has a composite structure, such as, but not limited to, a first silicon oxide layer 111-a silicon nitride layer 113-a second silicon oxide layer 115 (oxide-nitride-oxide, ONO) structure sequentially arranged from bottom to top, so that the bottom surface of the first spacer 181 can directly contact the top surface of the second silicon oxide layer 115.

On the other hand, the bit line structure 12 is disposed on the substrate 100 and extends along a direction (not shown) to simultaneously cross the active region and the insulation region 102, and a dielectric layer 110 is also disposed between the bit line structure 12 and the substrate 100. Although the overall extending directions of the active regions, the insulation regions 102 and the bit line structures 12 are not specifically shown in the drawings of the present embodiment, it should be easily understood by those skilled in the art that the extending directions of the bit line structures 12 should be different from the extending directions of the active regions in a top view, and may be arranged in an interlaced manner. In detail, the bit line structure 12 further includes a second semiconductor layer 122, a first barrier layer 152, a first conductive layer 162, a second cap layer 172, and a second spacer 182, which are sequentially stacked from bottom to top, and it should be noted that the second spacer 182 is also directly disposed on the top surface of the dielectric layer 110 and simultaneously physically contacts the sidewalls of the second semiconductor layer 122, the first barrier layer 152, the first conductive layer 162, and the second cap layer 172 of the bit line structure 12, so that the top surface of the second spacer 182 may be significantly higher than the top surface of the first spacer 181, as shown in fig. 1. A Bit Line Contact (BLC) 142 is further disposed below the bit line structure 12, and the bit line contact 142 penetrates through the second semiconductor layer 122 of the bit line structure 12 and the underlying dielectric layer 110, and may further extend into the active region of the substrate 100 to directly contact the active region. In the present embodiment, the bit line contact 142 and the second semiconductor layer 122 of the bit line structure 12 are formed by different processes, and may include different semiconductor materials, for example, the bit line contact 142 includes silicon phosphorus (SiP), and the second semiconductor layer 122 includes polysilicon (polysilicon), but not limited thereto.

It should be noted that, in the present embodiment, the first semiconductor layer 121 of the resistor structure 11 and the second semiconductor layer 122 of the bit line structure 12 may be formed simultaneously by the same manufacturing process, and thus, the first semiconductor layer 121 and the second semiconductor layer 122 may have the same semiconductor material (e.g., both include polysilicon), arrangement position (e.g., both are located on the second silicon oxide layer 115 of the dielectric layer 110), and the same thickness T1, but not limited thereto. In other words, the first semiconductor layer 121 and the second semiconductor layer 122 may have top surfaces flush with each other, as shown in fig. 1. In addition, the first cap layer 131 of the resistor structure 11 includes materials such as silicon oxide or silicon oxynitride; the first barrier layer 152 of the bit line structure 12 includes titanium (Ti) and/or titanium nitride (TiN), tantalum (Ta) and/or tantalum nitride (TaN), the first conductive layer 162 includes a low-resistance metal such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W), and the second capping layer 172 includes silicon nitride or silicon oxycarbide (sic), preferably, but not limited to, a material different from that of the first capping layer 131.

It should be noted that besides the bit line structure 12, a plurality of gates (not shown) may be further disposed in the substrate 100 of the second region 10B, and at least one transistor element (not shown) and at least one capacitor element (not shown) are disposed to jointly form a Dynamic Random Access Memory (DRAM) with a recessed gate (buried gate), where the transistor element (not shown) and the capacitor element may be used as a minimum cell (memory cell) in a DRAM array and receive voltage signals from the bit line 160 structure 12 and a Word Line (WL).

On the other hand, the gate line structure 13 is disposed on the substrate 100 and isolated from other components by the insulating region 103 in the substrate 100. In which, only the first silicon oxide layer 111 is disposed between the gate line structure 13 and the substrate 100, and can be directly located on the top surface of the first silicon oxide layer 111, as shown in fig. 1. In detail, the gate line structure 13 further includes a third semiconductor layer 123, a second barrier layer 153, a second conductive layer 163, and a third cap layer 173 sequentially stacked from bottom to top, and further includes a third spacer 182, it is noted that the third spacer 182 is directly disposed on the first silicon oxide layer 111 and simultaneously physically contacts sidewalls of the third semiconductor layer 123, the second barrier layer 153, the second conductive layer 163, and the third cap layer 173 of the gate line structure 13, so that a top surface of the third spacer 183 may be slightly lower than a top surface of the second spacer 182. In the present embodiment, for example, the gate line structure 13 and the bit line structure 12 are formed simultaneously by the same manufacturing process, so that the third semiconductor layer 123, the second barrier layer 153, the second conductive layer 163, the third cap layer 173, and the third spacer 183 of the gate line structure 13 may have the same material and thickness as the second semiconductor layer 122, the first barrier layer 152, the first conductive layer 162, the second cap layer 172, and the second spacer 182 of the bit line structure 12, respectively, but not limited thereto. In addition, the third semiconductor layer 123 of the gate line structure 13, the first semiconductor layer 121 of the resistor structure 11, and the second semiconductor layer 122 of the bit line structure 12 may be formed together, and all have the same material (e.g., all include polysilicon) and thickness T1; however, since the third semiconductor layer 123 of the gate line structure 13 is directly on the first silicon oxide layer 111, the horizontal position of the first semiconductor layer 121 and the second semiconductor layer 122 in the direction perpendicular to the substrate 100 is relatively lower than the horizontal position of the third semiconductor layer 123 in the direction perpendicular to the substrate 100, as shown in fig. 1.

As further shown in fig. 1, the semiconductor memory device 10 further includes a plurality of plugs 231, 232, and 233 electrically connected to the resistor structure 11 in the first region 10A, the bit line structure 12 in the second region 10B, and the gate line structure 13 in the third region 10C, wherein the plugs 231, 232, and 233 are respectively disposed in an inter-layer dielectric layer (inter-metal dielectric layer) 210 and an inter-metal dielectric layer (inter-metal dielectric layer) 220 sequentially stacked on the substrate 100. The inter-layer dielectric layer 210 completely covers the resistor structure 11 in the first region 10A and the gate line structure 13 in the third region 10C, and a top surface of the inter-layer dielectric layer 210 may be flush with a top surface of the second cap layer 172 of the bit line structure 12. It should be noted that, in the embodiment, each plug 231 electrically connected to the resistor structure 11 directly physically contacts the resistor structure 11 through the first cap layer 131, and since the first semiconductor layer 121 includes semiconductor materials such as polysilicon, a metal silicide layer 231a may be further disposed between each plug 231 and the first semiconductor layer 121 to improve the electrical connection between the first semiconductor layer 121 and the plug 231. The plug 232 electrically connected to the second region 10B directly and physically contacts the first conductive layer 162 through the second cap layer 172, and the plug 233 electrically connected to the third region 10C further includes a plug 233a directly and physically contacting the second conductive layer 163 of the gate line structure 13 through the third cap layer 173, and a plug 233B directly and physically contacting two doped regions (not shown) in the substrate 100 at two sides of the gate line structure 13 through the second silicon oxide layer 111.

Therefore, the semiconductor memory device 10 according to an embodiment of the present invention can separately provide the resistor structure 11, the bit line structure 12, and the gate line structure 13 in different regions (including the first region 10A, the second region 10B, and the third region 10C), wherein the resistor structure 11 is formed by the first semiconductor layer 121 partially identical to the bit line structure 12, which not only has good structural reliability, but also can achieve a relatively high and stable surface resistance. Thus, the semiconductor memory device 10 of the present invention can have a more optimized device performance as a whole.

It will be apparent to those skilled in the art that other embodiments of the semiconductor memory device 10 may be implemented to meet the actual product requirements, and are not limited to the foregoing. Furthermore, in order to enable a person skilled in the art to realize the semiconductor memory device 10 of the present invention, a method for manufacturing the semiconductor memory device 10 of the present invention will be further described in detail.

Referring to fig. 2 to 9, steps of a method for fabricating a semiconductor memory device 10 according to an embodiment of the present invention are shown. First, as shown in fig. 2, a substrate 100 is provided, which includes at least three regions, such as a first region 10A, a second region 10B, and a third region 10C, and a plurality of active regions (not shown) and a plurality of insulating regions 101, 102, and 103 are formed in the substrate 100 and respectively located in the first region 10A, the second region 10B, and the third region 10C. Then, a plurality of deposition processes are sequentially performed on the substrate 100 to form a dielectric layer 110, a semiconductor material layer 120 and a first cover material layer 130 sequentially stacked from bottom to top, wherein the dielectric layer 110 preferably has a composite structure, for example, a structure including a first silicon oxide layer 111, a silicon nitride layer 113 and a second silicon oxide layer 115 sequentially disposed from bottom to top, the semiconductor material layer 120 includes a semiconductor material such as polysilicon, and the first cover material layer 130 includes an insulating material such as silicon oxide, silicon oxynitride, but not limited thereto.

It should be noted that the dielectric layer 110 initially covers the active regions and the insulation regions 101, 102, 103 in the first, second and third regions 10A, 10B, 10C, and then, before the deposition process of the semiconductor material layer 120, the second silicon oxide layer 115 and the silicon nitride layer 113 in the third region 10C are removed, so that the active regions and the insulation regions 103 in the third region 10C are covered by the first silicon oxide layer 111 only, as shown in fig. 1. Thus, the semiconductor material layer 120 and the first cover material layer 130 subsequently formed in the third region 10C may have a relatively lower disposition position than the semiconductor material layer 120 and the first cover material layer 130 formed in other regions. Alternatively, in another embodiment, the dielectric layer 110 in the third region 10C may be completely removed to expose the surface of the substrate 100, and then a silicon oxide layer (not shown) is formed on the surface of the substrate 100 by a thermal oxidation process. In addition, as shown in fig. 1, after the first cover material layer 130 is formed, an etching process is performed through a mask layer (not shown) to define a contact opening 120a in the second region 10B, wherein the contact opening 120a sequentially penetrates through the first cover material layer 130, the semiconductor material layer 120 and the dielectric layer 110 to expose a portion of the substrate 100.

As shown in fig. 3, another deposition process is performed to form a conductive material layer 140 on the substrate 100, filling the contact opening 120A in the second region 10B, and entirely covering the first region 10A, the second region 10B, and the third region 10C. In an embodiment, the conductive material layer 140 includes, for example, a semiconductor material such as polysilicon, silicon phosphorus, etc., and preferably includes silicon phosphorus, but not limited thereto.

As shown in fig. 4, a first mask layer 201 is formed in the first region 10A to cover the conductive material layer 140, and then a patterning process is performed through the first mask layer 201 to transfer the pattern of the first mask layer 201 into the underlying conductive material layer 140, thereby forming a mask pattern 141 as shown in fig. 5. Meanwhile, after the patterning process is performed, the conductive material layer 140 covering the first covering material layer 130 is completely removed, and the conductive material layer 140 filled in the contact opening 120a is partially removed, so as to form a contact, which is a bit line contact 142, in the contact opening 120a, as shown in fig. 5. Also, the first mask layer 201 is removed.

As shown in fig. 6, another patterning process is performed through the mask pattern 141, so as to transfer the pattern of the mask pattern 141 into the underlying first capping material layer 130, so as to form the first capping layer 131 in the first region 10A, and simultaneously completely remove the first capping material layer 130 in the second region 10B and the third region 10C. Then, a plurality of deposition processes are sequentially performed on the substrate 100 again to form the barrier material layer 150, the conductive material layer 160 and the second capping material layer 170 sequentially stacked from bottom to top on the first capping layer 131. The barrier material layer 150, the conductive material layer 160, and the second capping material layer 170 cover the first region 10A, the second region 10B, and the third region 10C in a conformal manner, the barrier material layer 150 includes titanium and/or titanium nitride, tantalum and/or tantalum nitride, the conductive material layer 160 includes low-resistance metal such as aluminum, titanium, copper, or tungsten, and the second capping material layer 170 includes silicon nitride or silicon oxycarbide, but not limited thereto.

As shown in fig. 7, second mask layers 202 and 203 are respectively formed in the second region 10B and the third region 10C to cover the second capping material layer 170, and then a further patterning process is performed through the second mask layers 202 and 203 to transfer the patterns of the second mask layers 202 and 203 to the underlying stacked layers (including the second capping material layer 170, the conductive material layer 160, the barrier material layer 150, and the semiconductor material layer 120, which are sequentially stacked), so as to form the stacked layer structure shown in fig. 8 in each region (including the first region 10A, the second region 10B, and the third region 10C). It should be noted that the second mask layers 202 and 203 are only formed in the second region 10B and the third region 10C, so that the second capping material layer 170, the conductive material layer 160 and the barrier material layer 150 covering the first region 10A can be completely removed to expose the first capping layer 131, and then the semiconductor material layer 120 covering the first region 10A is further patterned by using the first capping layer 131 as an etching mask to form the first semiconductor layer 121. On the other hand, the stacked layer structure in the second region 10B includes the second semiconductor layer 122, the first barrier layer 152, the first conductive layer 162, and the second cap layer 172 stacked in sequence from bottom to top, and the stacked layer structure in the third region 10C includes the third semiconductor layer 123, the second barrier layer 153, the second conductive layer 163, and the third cap layer 173 stacked in sequence from bottom to top, as shown in fig. 8. And the second masking layers 202, 203 are removed.

Then, as shown in fig. 9, deposition and etch back processes are sequentially performed to form a first spacer 181 on sidewalls of the first semiconductor layer 121 and the first cap layer 131 sequentially stacked in the first region 10A, form a second spacer 182 on sidewalls of the second semiconductor layer 122, the first barrier layer 152, the first conductive layer 162, and the second cap layer 172 sequentially stacked in the second region 10B, and form a third spacer 183 on sidewalls of the third semiconductor layer 123, the second barrier layer 153, the second conductive layer 163, and the third cap layer 173 sequentially stacked in the third region 10C. Thus, the first spacer 181, the second spacer 182, and the third spacer 183 may comprise the same material, such as silicon nitride, silicon carbonitride, etc., and preferably comprise the same material as the second cap layer 172 and the third cap layer 173, but not limited thereto. Subsequently, an inter-level dielectric layer 210, an inter-metal dielectric layer 220, and a plurality of plugs 231, 232, and 233 may be sequentially formed on the substrate 100, wherein the inter-level dielectric layer 210 completely covers the resistor structure 11 in the first region 10A and the gate line structure 13 in the third region 10C, and a top surface of the inter-level dielectric layer 210 may be flush with a top surface of the second cap layer 172 of the bit line structure 12, thereby forming the semiconductor memory device 10 shown in fig. 1.

Thus, the method for manufacturing the semiconductor memory device 10 according to an embodiment of the present invention is completed. Through the above steps, the resistor structure 11 and the bit line structure 12 can be formed in the first region 10A and the second region 10B, respectively. In other words, the manufacturing method of the present embodiment integrates the manufacturing of the resistor structure 11 into the general manufacturing process of the bit line structure 12, and the first semiconductor layer 121 of the resistor structure 11 is formed at a time by using the manufacturing process of the second semiconductor layer 122 of the bit line structure 12. Thus, when a memory is formed in the memory region (i.e., the second region 10B) of the semiconductor memory device 10, a resistor is formed in another region (i.e., the first region 10A) to effectively improve the manufacturing efficiency of the resistive structure 11. In addition, the manufacturing method of the present embodiment may also form the gate line structure 13 in the third region 10C, that is, the manufacturing of the gate line structure 13 is also integrated into the general manufacturing process of the bit line structure 12, which not only effectively improves the efficiency of the overall manufacturing process, but also further improves the performance and reliability of the semiconductor memory device 10.

For those skilled in the art, the semiconductor memory device and the method for fabricating the same of the present invention may have other aspects without being limited to the foregoing aspects, so as to meet the requirements of actual products. For example, in another embodiment, the gate line structure 13 in the semiconductor memory device 10 may not be integrated into the general process flow of the bit line structure 12, for example, the gate line structure 13 is formed separately in the third region 10C after the bit line structure 12 is formed, but not limited thereto.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A semiconductor memory device characterized by comprising:

a substrate including an active region and a plurality of insulating regions;

a resistor structure disposed on the insulating region, the resistor structure further comprising:

a first semiconductor layer;

a first capping layer disposed on the first semiconductor layer; and

a first spacer in direct physical contact with sidewalls of the first semiconductor layer and the first cap layer; and

a bit line structure disposed on the substrate and spanning the active region and the insulating region, the bit line structure further comprising:

a second semiconductor layer;

a first barrier layer disposed on the second semiconductor layer;

a first conductive layer disposed on the first barrier layer;

a second capping layer disposed on the first conductive layer; and

and the second gap wall is in direct physical contact with the second semiconductor layer, the first barrier layer, the first conductive layer, the second cover layer and the side wall of the second gap wall.

2. The semiconductor memory device according to claim 1, further comprising:

and the dielectric layer is arranged on the substrate and simultaneously covers the active region and the insulating region, wherein the dielectric layer comprises a composite structure, and the composite structure comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are sequentially stacked from bottom to top.

3. The semiconductor memory device according to claim 2, wherein the first spacer of the resistance structure and the second spacer of the bit line structure are respectively disposed on the dielectric layer.

4. The semiconductor memory device according to claim 3, wherein a bottom surface of the first spacer of the resistive structure directly contacts a top surface of the second silicon oxide layer of the dielectric layer; the second spacer of the bit line structure directly contacts a top surface of the dielectric layer.

5. The semiconductor memory device according to claim 1, further comprising:

and the interlayer dielectric layer is arranged on the substrate, and the top surface of the interlayer dielectric layer is flush with the top surface of the second cover layer.

6. The semiconductor memory device according to claim 5, wherein the interlayer dielectric layer completely covers the resistive structure.

7. The semiconductor memory device according to claim 1, further comprising:

and a plurality of plugs arranged on the substrate, wherein one of the plugs is in direct physical contact with the first semiconductor layer of the resistor structure, and the other of the plugs is in direct physical contact with the first conductive layer of the bit line structure.

8. The semiconductor memory device according to claim 7, further comprising:

and a metal silicide layer disposed between only one of the plugs and the first semiconductor layer.

9. The semiconductor memory device according to claim 5, further comprising:

gate line structure, set up on the active area, gate line structure still includes from bottom to top according to the preface and piles up:

a third semiconductor layer;

a second barrier layer;

a second conductive layer;

a third cap layer;

a third spacer.

10. The semiconductor memory device according to claim 9, wherein the interlayer dielectric layer completely covers the gate line structure.

11. The semiconductor memory device according to claim 9, wherein a top surface of the third spacer is lower than a top surface of the second spacer.

12. The semiconductor memory device according to claim 1, wherein a top surface of the first spacer is lower than a top surface of the second spacer.

13. The semiconductor memory device of claim 1, wherein the first cap layer and the second cap layer comprise different materials.

14. A semiconductor memory device characterized by comprising:

a substrate including an active region and a plurality of insulating regions;

the resistance structure sets up on the insulating region, the resistance structure still includes according to the preface from bottom to top:

a first semiconductor layer; and

a first cap layer; and

a bit line structure disposed on the substrate and crossing the active region and the insulating region, the bit line structure further comprising, in order from bottom to top:

the first semiconductor layer and the second semiconductor layer are provided with mutually flush top surfaces and the same semiconductor material;

a first barrier layer;

a first conductive layer; and

a second cap layer.

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