CN110634841A - 一种半导体元件及其形成方法 - Google Patents

一种半导体元件及其形成方法 Download PDF

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Publication number
CN110634841A
CN110634841A CN201810947246.8A CN201810947246A CN110634841A CN 110634841 A CN110634841 A CN 110634841A CN 201810947246 A CN201810947246 A CN 201810947246A CN 110634841 A CN110634841 A CN 110634841A
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conductive layer
die
semiconductor device
layer
redistribution structure
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王茂盈
黄沛霖
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Nanya Technology Corp
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Nanya Technology Corp
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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Abstract

本公开提供一种半导体元件及其形成方法。该半导体元件包括一第一晶粒及一导电层。该第一晶粒经配置以在一方向上与该半导体元件外部的一第二晶粒接合。该导电层在该方向上位于该第一晶粒及该第二晶粒之间，经配置以实现一参考接地。

Description

一种半导体元件及其形成方法
相关文献的交叉引用
本公开主张2018/06/22申请的美国正式申请案第16/015,559号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
技术领域
本公开关于一种半导体元件及其形成方法，特别涉及封装系统的一种半导体元件及其形成方法。
背景技术
系统级封装(system in package，SiP)是将多个集成电路封装在单个模块(封装)中。SiP执行电子系统的所有或大多数功能，并且通常使用在手机、数字音乐播放器或其他电子设备的内部。包含集成电路的晶粒可以垂直堆叠在基板上。晶粒通过接合打线以在内部彼此连接。SiP解决方案可能包括多种封装技术，如覆晶技术(flip chip)、打线接合(wire bonding)，晶圆级封装(wafer-level packaging)等。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开提供一种半导体元件。该半导体元件包括一第一晶粒与一导电层。该第一晶粒经配置以在一方向上与该半导体元件外部的一第二晶粒接合。该导电层设置在该方向上且位于该第一晶粒和该第二晶粒之间，经配置以实现一参考接地。
在一些实施例中，该第二晶粒经配置以接合该第一晶粒，以及通过将该第二晶粒投影至该第一晶粒上界定出一投影区域，并且该导电层占据该投影区域。
在一些实施例中，该半导体元件还包括一重布结构。该重布结构经配置以做为该第一晶粒的走线，并且围绕并覆盖该导电层。
在一些实施例中，该导电层是一第一导电层。该重布结构包括一第二导电层。该第二导电层经配置以当该第二导电层传送除该参考接地之外的一信号时，与该第一导电层电性隔离。
在一些实施例中，该导电层是一第一导电层。该重布结构包括一第二导电层。该第二导电层经配置以当该第二导电层传送该参考接地时，被耦合到该第一导电层。
在一些实施例中，该重布结构还包括该导电层上的一介电层。该半导体元件还包括一插栓。该插栓设置在该介电层中，并且经配置以耦合该第一导电层到该第二导电层。
在一些实施例中，该第二晶粒经配置以接合该第一晶粒，并且通过将该第二晶粒投影至该第一晶粒上界定出一投影区域，该导电层延伸至该投影区域之外。
在一些实施例中，该第一晶粒包括一钝化层，其中该导电层经设置于该钝化层上。
在一些实施例中，该导电层包括铜，且该导电层具有一网状结构。
本公开另提供一半导体元件。该半导体元件包括一第一晶粒、一导电层及一重布结构。该导电层设置在该第一晶粒上并在该第一晶粒上延伸，经配置以一实现参考接地。该重布结构覆盖并围绕该导电层。
在一些实施例中，该导电层是一第一导电层。该重布结构包括一介电层及一第二导电层。该介电层覆盖该导电层。该第二导电层经设置在该介电层上。该半导体元件还包括一插栓。该插栓设置在该介电层中。该第二导电层通过该插栓提供该第一导电层该参考接地。
在一些实施例中，该第一晶粒包括该第一晶粒一顶表面上的一钝化层，该钝化层接触该导电层。
本公开另提供一种半导体元件的形成方法。该形成方法包括：提供一第一晶粒，以及在该第一晶粒和将与该第一晶粒接合的该第二晶粒之间形成一导电层。
在一些实施例中，该形成方法还包括形成一重布结构覆盖该导电层。
在一些实施例中，该形成方法还包括在一投影区域中的该第一晶粒上形成该导电层。该第二晶粒经配置以接合该第一晶粒，并且通过将该第二晶粒投影至该第一晶粒上界定出该投影区域。
在比较的半导体元件中，如果该第一晶粒及该第二晶粒同时以相对较高操作频率操作时，该第一晶粒及该第二晶粒彼此会出现射频(radio frequency，RF)的干扰。
在本公开中，导电层能够有效地屏蔽该第一晶粒和该第二晶粒。因此，即使该第一晶粒及该第二晶粒同时以相对较高的操作频率操作时，该第一晶粒不再受到来自该第二晶粒的RF干扰。此外，不需要大幅改变电路设计。原始电路设计仍然可以使用，唯一改变是添加导电层和插栓，这减少了电路设计者的负担。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1是一比较封装半导体元件的示意图；
图2是图1中该比较封装半导体元件沿A-A线的剖面图；
图3是剖面图，例示本公开一些实施例的一封装半导体元件沿与图1中相同A-A线的剖面图；
图4是剖面图，例示本公开一些实施例图3的封装半导体元件沿与图1中相同B-B线的剖面图；
图5是剖面图，例示本公开一些实施例的另一封装半导体元件沿与图1中相同A-A线的剖面图；
图6是剖面图，例示本公开一些实施例图5的封装半导体元件沿与图1中相同B-B线的剖面图；
图7至图12例示本公开一些实施例的形成一封装半导体元件的中间阶段的剖面图；
图13是流程图，例示本公开一些实施例的一封装半导体元件的形成方法。
附图标记说明：
1 比较封装半导体元件
2 半导体元件
3 半导体元件
4 半导体元件
5 方法
10 第一晶粒
14 重布结构
16 导线
20 第二晶粒
30 导电层
31 投影区域
32 插栓
40 导电层
50 操作
52 操作
54 操作
56 操作
100 基底
102 接垫
104 钝化层
110 接垫
112 接垫
120 接垫
122 接垫
140 介电层
142 导电层
144 介电层
212 接垫
222 接垫
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了实施方式之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于实施方式的内容，而是由权利要求定义。
图1是一比较封装半导体元件1的示意图。参照图1，比较封装半导体元件1包括一半导体元件2，半导体元件2包括一第一晶粒10及半导体元件2外的一第二晶粒20。
第一晶粒10包括例如一动态随机存取存储器(dynamic random access memory，DRAM)。在一些实施方式中，第一晶粒10可包括逻辑芯片(例如，中央处理单元、微控制器)、存储器芯片(例如，静态随机存取存储器(static random access memory，SRAM)芯片)、电源管理芯片(例如，电源管理集成电路(power management integrated circuit，PMIC)芯片、射频(radio frequency，RF)芯片、感测芯片、微机电系统(micro-electro-mechanical-system，MEMS)芯片、信号处理芯片(例如，数字信号处理(digital signal processing，DSP)芯片、前段芯片(例如，模拟前端(analog front-end，AFE)芯片)或其组合。
第二晶粒20在一方向(例如，一垂直方向)上，通过例如系统级封装(system inpackage，SiP)技术堆叠并接合到第一晶粒10。在一些实施方式中，第二晶粒20通过例如直接表面接合、金属对金属接合、混合接合或其它接合制程而接合到第一晶粒10。第二晶粒20包括例如一系统单芯片(system on chip，SoC)。第二晶粒20执行的功能可以与第一晶粒10的不同。在本比较例示中的第二晶粒20的面积小于第一晶粒10的面积。但是，本公开不限于此。在一些实施方式中，第二晶粒20可包括逻辑芯片(例如，中央处理单元、微控制器)、存储器芯片(例如，静态随机存取存储器(SRAM)芯片)、电源管理芯片(例如，电源管理集成电路(PMIC)芯片、射频(RF)芯片、感测芯片、微机电系统(MEMS)芯片、信号处理芯片(例如，数字信号处理(DSP)芯片、前段芯片(例如，模拟前端(AFE)芯片)或其组合。
第一晶粒10通过第一晶粒10上的接垫110、112、120和122以及第二晶粒20上的接垫212和222与第二晶粒20连通。为简洁和清楚起见，仅描绘四个接垫110、112、120及122。但是，本公开不限于此。
更详细地说，第一晶粒10分别通过第一晶粒10上的接垫110和第二晶粒20上的接垫212将一参考接地与第二晶粒20连通。然而，接垫110可能经设置地离接垫212很远。如果接垫110直接接合到接垫212，则需要具有相对较长的导线将接垫110接合到接垫212。这种导线可能会导致不利的影响。为了解决这种问题，导入了接垫112和半导体元件2的一重布结构14，其中重布结构14经配置以做为第一晶粒10的走线，请参考图2详细说明。通过重布结构14(将于图2详细说明)，接垫110为接垫112提供参考接地，而相较于于接垫110，接垫112相对较靠近接垫212。
同样地，第一晶粒10分别通过第一晶粒10上的接垫120和第二晶粒20上的接垫222，将不同于参考接地的一信号与第二晶粒20连通。此信号例如包括数据信号、时钟信号或其他合适的信号。为解决上述问题，通过重布结构14，接垫120提供一信号到接垫122，而接垫122相较于接垫120，相对较靠近接垫222。
在操作中，如果第一晶粒10和第二晶粒20均以相对较高的操作频率操作，则第一晶粒10和第二晶粒20彼此会出现出射频(radio frequency，RF)的干扰。理论上，消除这种RF干扰的可能方法是调整第一晶粒10和第二晶粒20的操作频率，如此第一晶粒10和第二晶粒20，例如，以交错的方式，在不同时间以高操作频率操作。但是，这种方法有其困难度或不可能实施。此外，在不大幅度变更半导体元件2的电路设计的情况下，例如，改变布局和(或)电路结构，难以或不可能消除、减轻RF的干扰。
图2是图1中比较封装半导体元件1沿A-A线的剖面图。参照图2，第一晶粒10包括一基底100、一接垫102及一钝化层104。
基底100可以包括例如本体硅(bulk silicon)、掺杂或未掺杂、或绝缘层上半导体(semiconductor-on-insulator，SOI)基底的主动层。通常，SOI基底包括在绝缘层上形成的半导体材料层，例如硅。此绝缘层可以是例如下埋氧化(buried oxide，BOX)层或氧化硅层。此绝缘体层设置在基底上，通常是硅基底或玻璃基底。其他基底，例如多层或梯度基底也可以使用。在另一实施方式中，基底100可以包括一基底，一集成电路晶粒可以附接到该基底。例如，基底100可以包括中介层、封装基板、高密度互连、印刷电路板，另一集成电路晶粒等。
应当注意的是，在一些实施方式中，特别是在基底100包括一集成电路电路晶粒的实施方式中，基底100可以包括电路(未示出)。在一种实施方式中，此电路包括形成在基底100上的电子元件，其中一个或多个介电层覆盖在电子元件上。可以在介电层之间形成金属层，以在电子元件之间路由电子信号。也可以在一个或多个介电层中形成电子元件。
例如，电路可以包括各种N型金属氧化物半导体(n-type metal-oxidesemiconductor，NMOS)和(或)P型金属氧化物半导体(p-type metal-oxidesemiconductor，PMOS)元件，例如晶体管、电容器、电阻器，二极管、光电二极管、熔丝等等，相互连接以执行一个或多个功能。这些功能可以包括存储器结构、处理结构、感测器、放大器、功率分配、输入或输出电路等。本领域通常技术人员将理解，提供上述例示仅用于说明目的，以进一步解释一些说明性实施方式的应用，并且不意味着以任何方式限制本公开。可以依照给定的应用，适当地使用其他的电路。在基底100是一中介层情况下，此中介层可以包括无源元件(被动元件)、主动元件、皆为主动元件和皆为无源元件，或者两者都不包括。
此外，基底100可以是晶圆，其可以形成多个晶粒及于之后分离，因此形成单个的集成电路晶粒。如此，图示说明单个晶粒以便于说明，同时应理解的是，可以将晶圆的一部分制造为晶粒。
接垫102设置在基底100的上表面中以提供外部电连接。在本公开中，接垫102是在金属层(metal-3，M3)中。但是，本公开不限于此。应注意的是，接垫102可表示与在基底100上形成的电路的一电连接。接垫102可以包括例如铜的导电材料，但是可以替代地使用其他导电材料，例如钨，铝或铜合金。接垫102可以通过任何合适的制程形成，例如沉积和蚀刻，镶嵌或双镶嵌等，以及任何合适的导电材料，例如铝。
钝化层104可以由介电材料形成，例如聚酰亚胺(polyimide，PI)，聚合物、氧化物、氮化物等，并且在基底100的表面上形成图案，以在接垫102上方提供一开口并且保护下层避免受各种环境污染物的影响。在一实施例中，钝化层104包括氮化硅层和氧化物层的复合层。氮化硅层可以采用化学气相沉积(chemical vapor deposition，CVD)技术，使用硅烷和氨作为前趋气气体(precursor gas)来形成，厚度约为2000埃氧化物层可以通过任何氧化制程来形成，例如在包含氧化物、H2O、NO或其组合的周围环境中的湿式或干式热氧化，或通过使用四乙基原硅酸盐(tetra-ethyl-ortho-silicate，TEOS)的CVD技术形成，并且以氧气作为前趋气体。
可以使用任何合适的制程来形成以上所讨论的结构，在此不再更详细讨论。如本领域通常技术人员所了解的，以上描述提供了对此实施例的此特征的一般性描述，此实施例并且可以存在许多其他特征。例如，可以存在其他电路、衬垫，阻障层、凸块下金属化配置、附加钝化层等。单层导电或接合垫及一钝化层仅出于说明性目的而示出。其他实施例可包括任何数量的导电层和(或)钝化层。以上描述仅意在提供本文所讨论的实施例的上下文，并不意味着限制本公开或对特定实施例的任何权利要求的范围。
依旧参考图2，重布结构14包括一介电层140、一导电层142及一介电层144。
介电层140形成在钝化层104上方。介电层140用作为一模具，在后续处理步骤中以形成导电柱或插栓。在一实施方式中，介电层140包括聚合物，例如环氧树脂、聚酰亚胺(PI)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazol，PBO)等。在聚合物层是例如PBO的一实施方案中，聚合物层可以通过旋转涂布(Spin coating)形成例如约2微米(μm)至约5微米的厚度，并使用光学光刻(photolithography)技术进行图案化。PBO是光感材料，可以通过根据所需图案曝光PBO层、显影和固化予以图案化。
如图2所示，于介电层140表面及接垫102的暴露部分之上形成导电层142。在一个实施方式中，导电层142可以通过使用CVD或PVD技术沉积薄导电层例如钛(Ti)、钽(Ta)、铜(Cu)、氮化钛(TiN)、氮化钽(TaN)的薄层来形成。例如，在一种实施方式中，导电层142包括通过PVD制程沉积的Ti层。
介电层144具有与介电层140相同的材料。因此，为简洁起见，省略了详细描述。
尽管明确说明两个介电层140和144，但是重布结构14可以还包括任何数量、其中设置有导电特征的介电层，这取决于封装的设计。
接垫112形成在重布结构14上，并且在接合打线制程之后，经由导线16耦合到第二晶粒20上的接垫212。此外，接垫110形成在重布结构14上。
封装半导体元件1沿B-B线的剖面图类似于图2所示的剖面图，除了图2的接垫112和212替换为接垫122和222。因此，为简洁起见，省略了此剖面图。
图3是剖面图，例示本公开一些实施例的一封装半导体元件3沿与图1中相同A-A线的剖面图。参照图3，半导体元件3类似于图2描述和例示的半导体元件2，除了例如半导体元件3包括在钝化层104上的一导电层30和一插栓32之外。
导电层30在在一方向上位于第一晶粒10和第二晶粒20之间，用以屏蔽第一晶粒10与第二晶粒2，其中该第一晶粒10将接合第二晶粒20，如下面详细描述。导电层30经设置在钝化层104上，在一些实施例中延伸并接触钝化层104。此外，导电层30被重布结构14包围及覆盖。更详细地，导电层30被介电层140覆盖。在一些实施例中，导电层30包括铜，且导电层30具有网状结构。通常，由铜组成的物体只能承受很小的应力但是，由于本公开的网状结构，可以减轻导电层30上的应力，因此保护导电层30的结构不会破裂。
导电层30仅占据投投影区域31。详言之，第二晶粒20将接合第一晶粒10。通过将第二晶粒20投影至第一晶粒10上界定出投影区域31。
投影区域31是通过将与第一晶粒10接合的第二晶粒20投影到第一晶粒10上来定义。导电层30不延伸至投影区域31之外。
插栓32，在介电层140中，用以耦合导电层30到导电层142。
如前所述，接垫110用于经由接垫102将参考接地传输到第一晶粒10。在此情况下，接垫102作为接地接垫。此外，接垫110也用于经由接垫102将参考接地传输到第二晶粒20。更详细地说，接垫110与导电层142短路。导电层142传送参考接地，并且经由插栓32提供导电层30此参考接地。因此，导电层30具有或实现参考接地。
因为导电层30具有参考接地且导电层30占据投影区域31，所以导电层30能够有效地屏蔽第一晶粒10与第二晶粒20。因此，即使第一晶粒10及第二晶粒10同时以相对较高的操作频率操作，第一晶粒10不再受到来自第二晶粒20RF的干扰。
此外，不需要大幅改变电路设计。原始电路设计仍然可以使用，唯一的改变是添加导电层32和插栓32，这减少了电路设计者的负担。
图4是剖面图，例示本公开一些实施例图3的封装半导体元件沿与图1中相同B-B线的剖面图。参照图4，如前所述，接垫120用于经由接垫102将除了参考接地之外的一信号传输到第一晶粒10。在此情况下，接垫102作为一信号接垫。此外，接垫120也用于经由接垫222将此信号传输到第二晶粒20。更详细地说，接垫120与导电层142短路。导电层142传送此信号。为了允许导电层30持续传送参考接地，导电层142与导电层30电性隔离。更详细地说，与图3实施例不同的是，没有插栓将导电层142耦合到导电层30。
图5是剖面图，例示本公开一些实施例的另一包括一半导体元件的封装半导体元件4，沿与图1中相同A-A线的剖面图。参照图5，半导体元件4类似于图3描述和例示的半导体元件3，除了例如半导体元件4包括一导电层40之外。
导电层40在钝化层104上延伸，并延伸至投影区域31之外。钝化层104的一整个表面实质上被导电层40覆盖。因此，即使第一晶粒10和第二晶粒20同时以相对较高的操作频率操作，不但第一晶粒10不再显示出受到来自第二晶粒20RF的干扰，而且第二晶粒20也不再显示出受到来自第一晶粒10RF的干扰。
图6是剖面图，例示本公开一些实施例图5的封装半导体元件沿与图1中相同B-B线的剖面图。参照图6，类似于图5的实施例，导电层40在钝化层104上延伸，且延伸至投影区域31之外。钝化层104的一整个表面实质上被导电层40覆盖。
图7至图12例示本公开一些实施例的形成一封装半导体元件的中间阶段的剖面图。参照图7，提供第一晶粒10。更详细地，提供基底100，并在其上形成集成电路晶粒。其次，通过任何合适的制程在基底100上形成接垫102，例如沉积或蚀刻、镶嵌或双镶嵌等，以及任何合适的导电材料，例如铝。接下来，通过例如图案化制程在基底100和接垫102上形成钝化层104。
参照图8，通过例如溅镀制程在钝化层104上形成导电层40。
参照图9，通过例如图案化制程在导电层40和接垫102上形成重布结构14。
参照图10，接垫110和112形成在重布结构14中。
参照图11，提供第二晶粒20，其上具有接垫212。
参照图12，第二晶粒20通过导线16通过例如接合打线制程接合到第一晶粒10。
图13是流程图，例示本公开一些实施例的一封装半导体元件的形成方法5。参照图13，形成方法5包括操作50、52、54和56。
形成方法5从操作50开始，其中提供包括一钝化层的一第一晶粒。
形成方法5进行至操作52，其中在该钝化层上及在该第一晶粒和一第二晶粒之间形成一导电层。该第二晶粒经配置以接合该第一晶粒。
形成方法5继续操作54，其中在该第一晶粒的一接垫上形成一重布结构。此外，该重布结构覆盖该导电层。
形成方法5进行至操作56，其中在该重布结构中形成一第二接垫，该第二接垫将与该第二晶粒的一接垫打线接合。
形成方法5仅是本公开的一个实施例，非意图限制权利要求所定义的本公开的构思与范围。在形成方法5之前、期间和之后可以有额外的操作，并可替换、删除或移动一些操作以用于此方法的另外实施例。
在比较的半导体元件2中，如果第一晶粒10及第二晶粒20同时以相对较高操作频率操作时，第一晶粒10及第二晶粒20彼此会出现射频(RF)的干扰。
在本公开中，导电层30能够有效地屏蔽第一晶粒10和第二晶粒20。因此，即使第一晶粒10及第二晶粒10同时以相对较高的操作频率操作，第一晶粒10不再受到来自第二晶粒20RF的干扰。此外，不需要大幅改变电路设计。原始电路设计仍然可以使用，唯一的改变是添加导电层32和插栓32，这减少了电路设计者的负担。
本公开一实施例提供一半导体元件。该半导体元件包括一第一晶粒及一导电层。该第一晶粒经配置以在一方向上与该半导体元件外部的一第二晶粒接合。该导电层设置在该方向上且位于该第一晶粒和该第二晶粒之间，经配置以实现一参考接地
本公开另一实施例提供一半导体元件。该半导体元件包括一第一晶粒、一导电层及一重布结构。该导电层设置在该第一晶粒上并在该第一晶粒上延伸，经配置以一实现参考接地。该重布结构，覆盖并围绕该导电层。
本公开另提供一种半导体元件的形成方法。该形成方法包括：提供一第一晶粒，以及在该第一晶粒和将与该第一晶粒接合的该第二晶粒之间形成一导电层。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本公开的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，这些制程、机械、制造、物质组成物、手段、方法、或步骤包含于本公开的权利要求内。

Claims (19)

1.一种半导体元件，包括：
一第一晶粒，经配置以在一方向上与该半导体元件外部的一第二晶粒接合；以及
一导电层，设置在该方向上且位于该第一晶粒和该第二晶粒之间，经配置以实现一参考接地。
2.如权利要求1所述的半导体元件，其中该第二晶粒经配置以接合该第一晶粒，以及通过将该第二晶粒投影至该第一晶粒上界定出一投影区域，并且该导电层占据该投影区域。
3.如权利要求2所述的半导体元件，还包括：
一重布结构，经配置以做为该第一晶粒的走线，围绕并覆盖该导电层。
4.如权利要求3所述的半导体元件，其中该导电层是一第一导电层，以及其中该重布结构包括：
一第二导电层，经配置以当该第二导电层传送除该参考接地以外的一信号时，与该第一导电层电性隔离。
5.如权利要求3所述的半导体元件，其中该导电层是一第一导电层，以及其中该重布结构包括：
一第二导电层，经配置以当该第二导电层传送该参考接地时，被耦合到该第一导电层。
6.如权利要求5所述的半导体元件，其中该重布结构还包括该导电层上的一介电层，其中该半导体元件还包括：
一插栓，设置在该介电层中，经配置以耦合该第一导电层到该第二导电层。
7.如权利要求1所述的半导体元件，其中该第二晶粒经配置以接合该第一晶粒，以及通过将该第二晶粒投影至该第一晶粒上界定出一投影区域，并且该导电层延伸至该投影区域之外。
8.如权利要求7所述的半导体元件，还包括：
一重布结构，经配置以做为该第一晶粒的走线，围绕并覆盖该导电层。
9.如权利要求8所述的半导体元件，其中该导电层是一第一导电层，以及其中该重布结构包括：
一第二导电层，经配置以当该第二导电层传送除该参考接地以外的一信号时，与该第一导电层电性隔离。
10.如权利要求8所述的半导体元件，其中该导电层是一第一导电层，以及其中该重布结构包括：
一第二导电层，经配置以当该第二导电层传送该参考接地时，被耦合到该第一导电层。
11.如权利要求10所述的半导体元件，其中该重布结构还包括该导电层上的一介电层，其中该半导体元件还包括：
一插栓，设置在该介电层中，经配置以耦合该第一导电层到该第二导电层。
12.如权利要求1所述的半导体元件，其中该第一晶粒包括一钝化层，其中该导电层位于该钝化层上。
13.如权利要求1所述的半导体元件，其中该导电层包括铜，且该导电层具有一网状结构。
14.一种半导体元件，包括：
一第一晶粒；
一导电层，设置在该第一晶粒上并在该第一晶粒上延伸，经配置以实现一参考接地；以及
一重布结构，覆盖并围绕该导电层。
15.如权利要求14所述的半导体元件，其中该导电层是一第一导电层，以及其中该重布结构包括：
一介电层，覆盖该导电层；以及
一第二导电层，设置在该介电层上，
其中该半导体元件还包括：
一插栓，设置在该介电层中，其中该第二导电层通过该插栓提供该第一导电层该参考接地。
16.如权利要求14所述的半导体元件，其中该第一晶粒包括该第一晶粒的一顶表面上的一钝化层，该钝化层接触该导电层。
17.一种半导体元件的形成方法，包括：
提供一第一晶粒；以及
在该第一晶粒上，以及在该第一晶粒和将与该第一晶粒接合的一第二晶粒之间形成一导电层。
18.如权利要求17所述的形成方法，还包括：
形成一重布结构覆盖该导电层。
19.如权利要求17所述的形成方法，还包括：
在一投影区域中的该第一晶粒上形成该导电层，其中该第二晶粒经配置以接合该第一晶粒，以及通过将该第二晶粒投影至该第一晶粒上界定出该投影区域。
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