CN110620553A - Millimeter wave cascade frequency multiplier circuit - Google Patents

Millimeter wave cascade frequency multiplier circuit Download PDF

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Publication number
CN110620553A
CN110620553A CN201910925044.8A CN201910925044A CN110620553A CN 110620553 A CN110620553 A CN 110620553A CN 201910925044 A CN201910925044 A CN 201910925044A CN 110620553 A CN110620553 A CN 110620553A
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tube
frequency multiplier
circuit
transmission line
capacitor
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CN110620553B (en
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杨守军
魏国辉
谢建法
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XIAMEN IMSEMI SEMICONDUCTOR SCIENCE & TECHNOLOGY Co Ltd
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XIAMEN IMSEMI SEMICONDUCTOR SCIENCE & TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device

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Abstract

The invention discloses a millimeter wave cascade frequency multiplier circuit, which comprises a frequency multiplier core circuit, an input matching network and an output matching network, wherein the input matching network is connected with the output matching network; the core circuit of the frequency multiplier comprises a pseudo-differential amplifier and a transmission line TL3Capacitor C3The pseudo-differential amplifier is of a Cascode structure and is formed by longitudinally and serially overlapping a plurality of first-stage BJT transistors and second-stage BJT transistors, the number of the first-stage BJT transistors is n times of that of the second-stage BJT transistors, and n is larger than or equal to 2. The invention fully utilizes the amplification performance of the second stage BJT of the pseudo-differential amplifier in the core circuit of the frequency multiplier, can output larger amplitude signals and improves the conversion gain and the stability of the frequency multiplier.

Description

Millimeter wave cascade frequency multiplier circuit
Technical Field
The invention relates to the technical field of frequency multipliers, in particular to a millimeter wave cascade frequency multiplier circuit.
Background
With the rapid development of wireless technology, people have higher and higher requirements on data transmission rate, and spectrum resources become more and more precious, and on the basis, the millimeter wave and sub-millimeter wave frequency bands gradually attract attention of people. The millimeter wave frequency is between 30GHz and 300GHz, and the available spectrum resources are quite abundant, so the millimeter wave technology has very wide application in the aspects of radar, microwave relay, satellite communication and the like.
Millimeter wave frequency sources are mainly classified into two main categories: an electric vacuum source and a solid state source. The electric vacuum source is realized by using an electric vacuum device, which has the greatest advantage of generating higher output power, but has the obvious defects of large volume, poor stability, low pressure resistance and short service cycle, so that most of signal sources in a millimeter wave frequency band are finished by adopting solid-state sources which can be structurally divided into two types: the first is a millimeter wave oscillation source, namely, the required frequency is generated in an oscillation mode, and a signal source designed by the method has a simple structure, but has poor stability and large phase noise; the second implementation mode of the millimeter wave solid-state source is a frequency doubling mode, the output frequency of the millimeter wave solid-state source is the N-th harmonic of the input frequency, and the frequency of the input signal source is low, so that good phase noise characteristics and high frequency stability can be guaranteed.
The invention patent with publication number CN102104362A discloses a millimeter wave frequency multiplier and a cascade frequency multiplier, which comprises a pseudo-differential amplifier, an LC parallel resonant cavity and an LC series resonant cavity, wherein the pseudo-differential amplifier is a pseudo-differential common-emitter amplifier and has low power consumption, and the technical scheme adopts a one-stage pseudo-differential structure, and has low output and input isolation and low conversion gain.
Disclosure of Invention
The invention aims to provide a millimeter wave cascade frequency multiplier circuit to improve the conversion gain and the stability of a frequency multiplier. In order to achieve the purpose, the invention adopts the following technical scheme:
the invention discloses a millimeter wave cascade frequency multiplier circuit, which comprises a frequency multiplier core circuit, an input matching network and an output matching network, wherein the input matching network is connected with the output matching network; the core circuit of the frequency multiplier comprises a pseudo-differential amplifier and a transmission line TL3Capacitor C3The pseudo-differential amplifier is of a Cascode structure and is formed by longitudinally and serially overlapping a plurality of first-stage BJT transistors and second-stage BJT transistors, the number of the first-stage BJT transistors is n times of that of the second-stage BJT transistors, and n is more than or equal to 2; the first stage BJT transistor comprises Q1Tube and Q2The second stage BJT transistor includes Q3Tube and Q4A tube; the above-mentionedQ of (2)1Tube and Q2The emitter of the tube is connected with GND, Q1Tube and Q2The collector electrodes of the tubes are respectively connected with Q3Tube and Q4An emitter of the tube; q3Tube and Q4The collector of the tube is connected as the output end out of the core circuit of the frequency multiplier; the transmission line TL3The output end of the pseudo-differential amplifier is connected with VDD; the capacitor C3Is connected at Q3Tube and Q4Between the base electrode of the tube and GND; two access points v of input matching networkin_p'、vin_n' separately accessing Q in core circuit of frequency multiplier1Tube, Q2The base of the tube, the output port out' of the output matching network is connected to the output end out of the frequency multiplier core circuit.
Furthermore, the frequency multiplier core circuit also comprises a first bias circuit and a second bias circuit, and the resistor R2Resistor R3 and resistor R4Said Q1Tube and Q2The base electrodes of the tubes are respectively connected with resistors R2Resistance R3One terminal of (1), resistance R2The other end and a resistor R3The other end of which is connected to a first-stage bias access point V serving as the pseudo-differential amplifierbias1'The base electrodes of the Q3 tube and the Q4 tube are connected and connected with one end of a resistor R4, and the other end of the resistor R4 is a second-stage bias access point V of the pseudo-differential amplifierbias2'Bias voltage supply point V of the first bias circuitbias1Accessing a first level offset access point Vbias1'(ii) a Bias voltage supply point V of second bias circuitbias2Accessing second level offset access point Vbias2'。
Wherein, said Q1Tube, Q2The working state of the tube is Class _ B, Q3Tube, Q4The working state of the tube is Class _ A or Class _ AB.
Preferably, the transmission line TL3Length of twice input frequency 2foCorresponding to a quarter of wavelength lambda.
Wherein the first bias circuit comprises Q0Tube, resistance R0Resistance R1Capacitor C0Said Q0The transistor is a BJT transistor, and the Q0The emitter of the tube is connected with GND, and Q0Base electrode connecting resistor R of tube1One terminal of (1), resistance R1Is connected with the other end of Q0The collector of the tube is used as a bias voltage supply point V of the first bias circuitbias1(ii) a The resistor R0Is connected at Q0Between the collector of the tube and VDD; the capacitor C0Is connected at Q0Between the collector of the tube and VDD.
Wherein the second bias circuit comprises Q5Tube, Q6Tube, resistance R5Resistance R6Said Q5Tube and Q6The transistor is a BJT transistor, and the resistor R5Is connected at Q5Between the emitter of the tube and GND, Q5The base electrode and the collector electrode of the tube are connected; q6Emitter and Q of a tube5Collector electrode of the tube, Q6The base electrode and the collector electrode of the tube are connected to serve as a bias voltage supply point V of the second bias circuitbias2(ii) a Resistance R6Is connected at Q6Between the collector of the tube and VDD.
Wherein the input matching network comprises a transmission line TL0Transmission line TL1Transmission line TL2Capacitor C1And a capacitor C2Transmission line TL0Two ends of the input port v are respectively connected with the input port v of the frequency multiplierin_p、vin_nConnecting; transmission line TL1Is connected at port vin_pAnd a capacitor C1C to1The other end of the first and second switches is used as an access point v for accessing a core circuit of the frequency multiplierin_p'(ii) a Transmission line TL2Is connected at port Vin_nAnd a capacitor C2C to2The other end of the first and second switches is used as an access point v for accessing a core circuit of the frequency multiplierin_n'。
Wherein the output matching network comprises a transmission line TL4Transmission line TL5Capacitor C4Said transmission line TL4One end is used as an output port out', and the other end is connected with a capacitor C4Capacitor C4The other end is connected with the output port v of the frequency multiplierout(ii) a Transmission line TL5Connected to the frequency multiplicationOutput port v of the deviceoutAnd GND.
Preferably, the power supply further comprises a single-to-double passive transformer, wherein the passive transformer and the output port v of the frequency multiplier are connected with each otheroutAnd (4) connecting.
Due to the adoption of the structure, the invention has the following beneficial effects:
1. the core circuit of the frequency multiplier adopts a pseudo-differential amplifier Cascode structure, namely a two-stage pseudo-differential structure, under the same process size, the number proportion of a first stage BJT (bipolar junction transistor) and a second stage BJT of the pseudo-differential amplifier is n times, the amplification performance of the second stage BJT of the pseudo-differential amplifier in the core circuit of the frequency multiplier is fully utilized, a larger amplitude signal is output, and the frequency multiplier can obtain better isolation between output and input.
2. A capacitor C3 with a higher capacitance value is indirectly connected between the base electrode of the second-stage BJT tube and GND in the pseudo-differential amplifier, so that the common-base amplification performance of the second-stage BJT tube is improved, the frequency multiplier has higher conversion gain and better output and input isolation, and the capacitor C3 short-circuits the single-side parasitic negative resistance of the pseudo-differential amplifier, so that the frequency multiplier obtains better stability.
3. The first stage BJT of the pseudo-differential amplifier of the core circuit power consumption of the frequency multiplier works in a Class _ B state, the bias current is low, and the overall power consumption of the circuit is low.
4. The frequency multiplier is a circuit system with double-end input and single-end output, and a capacitor C with a large capacitance value is adopted in a first bias circuit0And the common mode stability of the frequency multiplier is improved by connecting the frequency multiplier with VDD.
Drawings
Fig. 1 is a schematic diagram of a circuit configuration according to a first embodiment of the present invention.
FIG. 2 shows a fundamental frequency signal f according to the present invention0From the input port of the frequency multiplier into the input matching network and into the partial circuit diagram of the pseudo-differential amplifier.
FIG. 3a is a graph formed by Q3Tube, Q4Generation of frequency-doubled signals 2f at the tube emitter0Schematic representation of (a).
FIG. 3b is a graph formed by Q3Tube, Q4Pipe non-lineGenerated frequency-doubled signal 2f0Schematic representation of (a).
Fig. 3c is a schematic diagram of a pseudo-differential amplifier having a frequency multiplier to obtain a doubled frequency amplitude.
FIG. 4 is a graph of the amplitude of the DC component and the harmonic components of 1 st order to 5 th order in the output current of the BJT transistor as a function of conduction angle.
Fig. 5 is a schematic circuit structure diagram according to a second embodiment of the invention.
The main reference symbols are as follows:
100: first bias circuit, 200: frequency multiplier core circuit, 300: input matching network, 400: second bias circuit, 500: and outputting the matching network.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the present invention discloses a millimeter wave cascaded frequency multiplier circuit, which includes a first bias circuit 100, a frequency multiplier core circuit 200, an input matching network 300, a second bias circuit 400, and an output matching network 500.
The frequency multiplier core circuit 200 includes a pseudo-differential amplifier, a transmission line TL3Capacitor C3Resistance R2Resistor R3 and resistor R4. The pseudo-differential amplifier is of a Cascode structure (Cascode structure). The pseudo-differential amplifier is formed by longitudinally and serially overlapping a plurality of first-stage BJT transistors and second-stage BJT transistors, the number of the first-stage BJT transistors is n times of the number of the second-stage BJT transistors, and n is larger than or equal to 2.
The first stage BJT transistor includes Q1Tube and Q2The second stage BJT transistor includes Q3Tube and Q4A tube. Namely Q1Pipe (or Q)2Tubes) is Q3Pipe (or Q)4Tubes) is n times the number of the tubes, and n is more than or equal to 2.
Q1Tube and Q2The emitter of the tube is connected with GND, Q1Tube and Q2The collector electrodes of the tubes are respectively connected with Q3Tube and Q4The emitter of the tube. Q1Tube and Q2Base electrodes of the tubes are respectively connectedConnecting resistor R2Resistance R3One terminal of (1), resistance R2Another terminal of (1) and a resistor R3The other end of the first stage is connected with a first stage bias access point V serving as a pseudo-differential amplifierbias1'. The base electrodes of the Q3 tube and the Q4 tube are connected and connected with one end of a resistor R4, and the other end of the resistor R4 is a second-stage bias access point V of the pseudo-differential amplifierbias2'。Q3Tube and Q4The collector of the tube is connected as the output out of the frequency multiplier core circuit 200. Transmission line TL3A transmission line TL connected between the output of the pseudo-differential amplifier and VDD3Length of twice input frequency 2foCorresponding to a quarter of wavelength λ, i.e. transmission line TL3Length l = λ/4@2fo. Capacitor C3Is connected at Q3Tube and Q4The base electrode of the tube and GND.
The first bias circuit 100 includes Q0Tube, resistance R0Resistance R1Capacitor C0。Q0The transistor is a BJT transistor, Q0The emitter of the tube is connected with GND, Q0Base electrode connecting resistor R of tube1One terminal of (1), resistance R1Is connected with the other end of Q0Collector of the tube as a bias voltage supply point V of the first bias circuit 100bias1. Resistance R0Is connected at Q0Between the collector of the tube and VDD. Capacitor C0Is connected at Q0Between the collector of the tube and VDD. Bias voltage supply point V of first bias circuit 100bias1Accessing a first level offset access point Vbias1'. Capacitor C0The common mode stability of the frequency multiplier can be improved.
The second bias circuit 400 includes Q5Tube, Q6Tube, resistance R5Resistance R6。Q5Tube and Q6The transistor is a BJT transistor, and the resistor R5Is connected at Q5Between the emitter of the tube and GND, Q5The base and collector of the tube are connected. Q6Emitter and Q of a tube5Collector electrode of the tube, Q6The base and collector of the tube are connected as a bias voltage supply point V of the second bias circuit 400bias2. Resistance R6Is connected at Q6Between the collector of the tube and VDD. First, theBias voltage supply point V of two-bias circuit 400bias2Accessing second level offset access point Vbias2'。
Input matching network 300 includes transmission line TL0Transmission line TL1Transmission line TL2Capacitor C1And a capacitor C2. Transmission line TL0Two ends of the input port v are respectively connected with the input port v of the frequency multiplierin_p、vin_nAre connected. Transmission line TL1Is connected at port vin_pAnd a capacitor C1C to1The other end of which serves as an access point v to the multiplier core circuit 200in_p'. Transmission line TL2Is connected at port Vin_nAnd a capacitor C2C to2The other end of which serves as an access point v to the multiplier core circuit 200in_n'. Two access points v of input matching network 300in_p'、vin_n' separate access to Q in the multiplier core circuit 2001Tube, Q2The base of the tube.
The output matching network 500 includes a transmission line TL4Transmission line TL5Capacitor C4. Transmission line TL4One end is used as an output port out', and the other end is connected with a capacitor C4. Capacitor C4The other end is connected with the output port v of the frequency multiplierout. Transmission line TL5Is connected with the output port v of the frequency multiplieroutAnd GND. An output port out' of the output matching network 500 is connected to an output port out of the frequency multiplier core circuit 200.
Q1Tube, Q2The working state of the tube is Class _ B, Q3Tube, Q4The working state of the tube is Class _ A or Class _ AB.
The working principle of the invention is detailed as follows:
as shown in fig. 2, the differential fundamental frequency signal foInput port v of slave frequency multiplierin_p、vin_nEnters the input matching network 300 and enters the pseudo-differential amplifier in the frequency multiplier core circuit 200 through the input matching network 300. Q for base frequency signal entering first stage BJT tube1Tube and Q2Base of tube because of Q1Tube, Q2The tube has strong strength when working in a Class _ B stateIs not linear, so Q1Tube, Q2The collector electrodes of the tubes respectively output fundamental frequencies f with 180 DEG phase differenceoSecond harmonic signal 2f having the same phaseoFundamental frequency signal foAnd second harmonic signal 2foQ into second stage BJT transistor of pseudo-differential amplifier3Tube, Q4The emitter of the tube.
As shown in fig. 3a, because of Q3Tube, Q4The base electrode of the tube and the GND are connected with a capacitor C with a large capacitance value3So that Q is3Tube, Q4Better tube-common-base amplification, Q3Tube, Q4Second harmonic signals 2f of the same phase at the tube emitteroQ through second stage BJT transistor of pseudo-differential amplifier3Tube, Q4The tube amplification, pseudo-differential amplifier output can obtain the double frequency signal 2f with larger amplitudeo ' 。
As shown in FIG. 3b, Q 3Tube, Q4Fundamental frequency signal f with 180-degree phase difference at tube emitteroThrough Q3Tube, Q4The tube amplifies, the fundamental frequency signals with 180 degrees phase difference cancel each other at the output end of the pseudo-differential amplifier, and meanwhile Q is used for3Tube, Q4The second harmonic signal generated by the nonlinearity of the tube is accumulated at the output end of the pseudo-differential amplifier to generate a frequency doubling signal 2fo ”。
As shown in FIG. 3c, the pseudo-differential amplifier, Q, in the frequency multiplier3Tube, Q4The input signal at the tube emitter comprises a fundamental frequency signal foAnd a frequency-doubled signal 2fo. As can be seen in FIG. 4, Q3、Q4Working in the Class _ A or Class _ AB state can satisfy the requirement that the frequency multiplier obtains larger frequency doubling amplitude. As shown in FIG. 2, Q1Tube, Q2Tube and Q3Tube, Q4The size ratio of the tube is n:1 and n is more than or equal to 2, thereby satisfying Q1Tube, Q2The tube is operating in Class _ B, Q3Tube, Q4The tube is operating in either Class _ A or Class _ AB mode.
FIG. 3a generates a frequency-doubled signal 2f, as shown in FIG. 3co ’And the frequency-doubled signal 2f generated in fig. 3bo ”AccumulationTherefore, the amplitude of the frequency doubling signal is increased, and the integral conversion gain of the frequency multiplier is improved. Because the frequency multiplier core circuit 200 includes a pseudo-differential amplifier, the inverse isolation between the output and input of the frequency multiplier is better. Finally, the double frequency signal enters the load through the output matching network 500.
Example two
As shown in fig. 5, the present embodiment is different from the first embodiment in that: also comprises a single-to-double passive transformer (Balun) connected with the output end v of the frequency multiplieroutAnd (4) connecting. The rest of the circuit structure is the same as the first embodiment.
The input signal is the differential baseband signal f in this embodiment0The positive terminal of which is connected to vin_pNegative terminal connected to vin_nThe output signal is a frequency-2 multiplied signal 2f0. The single-ended output frequency doubling signal is converted into a differential frequency doubling output signal through a single-to-double passive transformer.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (9)

1. A millimeter-wave cascaded frequency multiplier circuit, characterized in that: the frequency multiplier comprises a frequency multiplier core circuit, an input matching network and an output matching network;
the core circuit of the frequency multiplier comprises a pseudo-differential amplifier and a transmission line TL3Capacitor C3The pseudo-differential amplifier is of a Cascode structure and is formed by longitudinally and serially overlapping a plurality of first-stage BJT transistors and second-stage BJT transistors, the number of the first-stage BJT transistors is n times of that of the second-stage BJT transistors, and n is more than or equal to 2;
the first stage BJT transistor comprises Q1Tube and Q2The second stage BJT transistor includes Q3Tube and Q4A tube; said Q1Tube and Q2The emitter of the tube is connected with GND, Q1Tube and Q2The collector electrodes of the tubes are respectively connected with Q3Tube and Q4An emitter of the tube; q3Tube and Q4The collector of the tube is connected as the output end out of the core circuit of the frequency multiplier; the transmission line TL3The output end of the pseudo-differential amplifier is connected with VDD; the capacitor C3Is connected at Q3Tube and Q4Between the base electrode of the tube and GND;
two access points v of input matching networkin_p'、vin_n' separately accessing Q in core circuit of frequency multiplier1Tube, Q2The base of the tube, the output port out' of the output matching network is connected to the output end out of the frequency multiplier core circuit.
2. The millimeter-wave cascaded frequency multiplier circuit of claim 1, wherein: the frequency multiplier core circuit also comprises a resistor R2Resistor R3 and resistor R4，
Said Q1Tube and Q2The base electrodes of the tubes are respectively connected with resistors R2Resistance R3One terminal of (1), resistance R2The other end and a resistor R3The other end of which is connected to a first-stage bias access point V serving as the pseudo-differential amplifierbias1'The base electrodes of the Q3 tube and the Q4 tube are connected and connected with one end of a resistor R4, and the other end of the resistor R4 is a second-stage bias access point V of the pseudo-differential amplifierbias2'，
Bias voltage supply point V of first bias circuitbias1Accessing a first level offset access point Vbias1'(ii) a Bias voltage supply point V of second bias circuitbias2Accessing second level offset access point Vbias2'。
3. The millimeter-wave cascaded frequency multiplier circuit of claim 3, wherein: said Q1Tube, Q2The working state of the tube is Class _ B, Q3Tube, Q4The working state of the tube is Class _ A or Class _ AB.
4. The millimeter wave cascade of claim 1A frequency multiplier circuit, characterized by: the transmission line TL3Length of twice input frequency 2foCorresponding to a quarter of wavelength lambda.
5. The millimeter-wave cascaded frequency multiplier circuit of claim 2, wherein: the first bias circuit comprises Q0Tube, resistance R0Resistance R1Capacitor C0Said Q0The transistor is a BJT transistor, and the Q0The emitter of the tube is connected with GND, and Q0Base electrode connecting resistor R of tube1One terminal of (1), resistance R1Is connected with the other end of Q0The collector of the tube is connected as the bias voltage supply point V of the first stage bias circuitbias1(ii) a The resistor R0Is connected at Q0Between the collector of the tube and VDD; the capacitor C0Is connected at Q0Between the collector of the tube and VDD.
6. The millimeter-wave cascaded frequency multiplier circuit of claim 2, wherein: the second bias circuit comprises Q5Tube, Q6Tube, resistance R5Resistance R6Said Q5Tube and Q6The transistor is a BJT transistor, and the resistor R5Is connected at Q5Between the emitter of the tube and GND, Q5The base electrode and the collector electrode of the tube are connected; q6Emitter and Q of a tube5Collector electrode of the tube, Q6The base electrode and the collector electrode of the tube are connected to serve as a bias voltage supply point V of the second bias circuitbias2(ii) a Resistance R6Is connected at Q6Between the collector of the tube and VDD.
7. The millimeter wave cascaded frequency multiplier circuit of any of claims 1 to 6, wherein: the input matching network comprises a transmission line TL0Transmission line TL1Transmission line TL2Capacitor C1And a capacitor C2Transmission line TL0Two ends of the input port v are respectively connected with the input port v of the frequency multiplierin_p、vin_nConnecting; transmission line TL1Is connected at port vin_pAnd a capacitor C1C to1The other end of the first and second switches is used as an access point v for accessing a core circuit of the frequency multiplierin_p'(ii) a Transmission line TL2Is connected at port Vin_nAnd a capacitor C2C to2The other end of the first and second switches is used as an access point v for accessing a core circuit of the frequency multiplierin_n'。
8. The millimeter wave cascaded frequency multiplier circuit of any of claims 1 to 6, wherein: the output matching network comprises a transmission line TL4Transmission line TL5Capacitor C4Said transmission line TL4One end is used as an output port out', and the other end is connected with a capacitor C4Capacitor C4The other end is connected with the output port v of the frequency multiplierout(ii) a Transmission line TL5Is connected with the output port v of the frequency multiplieroutAnd GND.
9. The millimeter-wave cascaded frequency multiplier circuit of claim 8, wherein: the power supply also comprises a single-to-double passive transformer, and the passive transformer and the output port v of the frequency multiplieroutAnd (4) connecting.
CN201910925044.8A 2019-09-27 2019-09-27 Millimeter wave cascade frequency multiplier circuit Active CN110620553B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2303575A (en) * 1940-04-29 1942-12-01 Farnsworth Television & Radio Frequency multiplier
US3710146A (en) * 1970-07-09 1973-01-09 Sony Corp Frequency doubler circuit
CN102104363A (en) * 2011-03-01 2011-06-22 北京大学 Tera-hertz silica-based quadrupler and frequency multiplier
CN104052405A (en) * 2013-03-12 2014-09-17 英飞凌科技股份有限公司 System and method for frequency doubler
CN104901674A (en) * 2014-03-06 2015-09-09 昆山启达微电子有限公司 Current mode four-quadrant CMOS analog multiplication circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2303575A (en) * 1940-04-29 1942-12-01 Farnsworth Television & Radio Frequency multiplier
US3710146A (en) * 1970-07-09 1973-01-09 Sony Corp Frequency doubler circuit
CN102104363A (en) * 2011-03-01 2011-06-22 北京大学 Tera-hertz silica-based quadrupler and frequency multiplier
CN104052405A (en) * 2013-03-12 2014-09-17 英飞凌科技股份有限公司 System and method for frequency doubler
CN104901674A (en) * 2014-03-06 2015-09-09 昆山启达微电子有限公司 Current mode four-quadrant CMOS analog multiplication circuit

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