CN110619835A

CN110619835A - Display panel and display device

Info

Publication number: CN110619835A
Application number: CN201910939905.8A
Authority: CN
Inventors: 刘芬
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2019-12-27
Anticipated expiration: 2039-09-30
Also published as: CN110619835B

Abstract

The embodiment of the invention provides a display panel and a display device. The display area of display panel has the breach, two first display areas are located the both sides of breach in the first direction, the second display area is located at least one side of breach in the second direction, non-display area includes breach non-display area and two first non-display areas, breach non-display area is half at least around the breach setting, the first gate line and the first second gate line of the first pixel row of 3m +1 th row and 3m +2 th row in the drive two first display areas are by unilateral drive, and not at the non-display area wire winding of breach. Two first gate lines driving the first pixel rows of the corresponding 3m +3 th row in the two first display areas are electrically connected through a connecting line positioned in the gap non-display area. According to the invention, two thirds of winding wires are reduced in the gap non-display area, the space is saved, the density of the winding wires in the gap non-display area can be weakened, the coupling effect among the metal winding wires can be weakened, and the display stability is improved.

Description

Display panel and display device

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a display panel and a display device.

[ background of the invention ]

In the conventional display device technology, the display panel is mainly divided into two mainstream technologies, namely a liquid crystal display panel and an organic self-luminous display panel. The liquid crystal display panel forms an electric field capable of controlling the deflection of liquid crystal molecules by applying voltage on the pixel electrode and the common electrode, and further controls the transmission of light rays to realize the display function of the display panel; the organic self-luminous display panel adopts an organic electroluminescent material, and when current passes through the organic electroluminescent material, the luminescent material can emit light, so that the display function of the display panel is realized.

With the application of display technology in smart wearable and other portable electronic devices, smooth user experience is continuously pursued in the design of electronic products, and meanwhile, sensory experience of users is also increasingly pursued, for example: the wide viewing angle, high resolution, narrow frame, high screen ratio and other performances become selling points of various electronic products. And in the display panel that has the breach in current display area, because the scanning line in the display area ends in breach department, and the scanning line of breach both sides need be connected through the wire winding electricity at the breach periphery, leads to the breach around the metal to walk the line densely, the coupling effect of metal walking the line is great, influences and shows stability, and dense metal is walked the line and is taken up great space around the breach in addition, and visual effect is poor.

[ summary of the invention ]

In view of this, embodiments of the present invention provide a display panel and a display device, so as to solve the problem in the prior art that the display stability and the visual effect are affected due to dense metal routing around the notch.

In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area, where the display area has a gap, the display area includes a first display area and a second display area, the two first display areas are located on two sides of the gap in a first direction, the second display area is located on at least one side of the gap in a second direction, the non-display area includes a gap non-display area and two first non-display areas, the gap non-display area is at least half arranged around the gap, the first non-display area is located on a side of the first display area away from the gap, and the first direction is crossed with the second direction;

the display panel comprises a plurality of gate lines extending along a first direction, wherein the gate lines comprise a first gate line and a second gate line, the first gate line is positioned in the first display area, and the second gate line is positioned in the second display area; the first gate lines include first a gate lines and first b gate lines, the first a gate lines and the first b gate lines are alternately arranged in the second direction, the first display region includes first pixel rows arranged in the second direction, and one first pixel row is connected to one first a gate line and one first b gate line, respectively;

the first gate line comprises a first end far away from the notch and a second end close to the notch, the second end of the 3m +1 th first A gate line is electrically connected with the second end of the 3m +2 th first A gate line, the second end of the 3m +1 th first B gate line is electrically connected with the second end of the 3m +2 th first B gate line, wherein m is more than or equal to 0, and m is an integer; the second ends of two 3m +3 first A grid lines respectively positioned at two sides of the notch in the first direction are electrically connected through an A connecting line, the second ends of two 3m +3 first B grid lines respectively positioned at two sides of the notch in the first direction are electrically connected through a B connecting line, and the A connecting line and the B connecting line are positioned in the notch non-display area;

the display panel comprises a grid driving circuit, the grid driving circuit comprises a first grid shifting register and a second grid shifting register, a plurality of cascaded first grid shifting registers are positioned in one first non-display area, and a plurality of cascaded second shifting registers are positioned in the other first non-display area;

on one side of the notch in the first direction: the first ends of the 3m +1 th first gate line A and the 3m +3 th first gate line B are electrically connected with the output end of the 2m +1 th stage first gate shift register; the first end of the 3m +1 th first B grid line is electrically connected with the output end of the 2 m-th stage first grid shift register; the first end of the 3m +3 first gate line is electrically connected with the output end of the 2m +2 stage first gate shift register;

on the other side of the notch in the first direction: the first end of the 3m +1 th first gate line is electrically connected with the output end of the 2m +1 th-stage second gate shift register; the first end of the 3m +1 th first B grid line is electrically connected with the output end of the 2 m-th-stage second grid shift register; the first ends of the 3m +3 th first A gate line and the 3m +3 th first B gate line are not electrically connected with the output end of the second shift register.

Based on the same inventive concept, in a second aspect, an embodiment of the present invention provides a display device including any one of the display panels provided by the embodiments of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects:

according to the embodiment of the invention, the first gate line in the first display area and the grid shift register are connected, so that two thirds of winding wires are reduced in the gap non-display area compared with the related art, the space is saved, and the narrowing of the gap non-display area is facilitated. And moreover, the concentration degree of the windings in the gap non-display area can be weakened, the coupling effect among the metal windings can be weakened, and the display stability is improved. The three first pixel rows which are sequentially arranged are driven by the two cascaded gate shift registers, the driving mode is favorable for balancing the voltage drop on each first gate line A and each first gate line B, the voltage drop on each gate line in the first display area is ensured to be approximately the same, the brightness of the sub-pixels driven by each gate line is ensured to be approximately the same, and the display brightness of the display panel is ensured to be uniform. Meanwhile, the number of grid shift registers arranged in the first non-display area can be reduced, the space is saved, and the first non-display area is narrowed.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a partial schematic view of a display panel according to an embodiment of the invention;

fig. 2 is a schematic diagram of an alternative implementation of a pixel circuit in a display panel according to an embodiment of the present invention;

FIG. 3 is a timing diagram of the pixel circuit illustrated in FIG. 2;

FIG. 4 is a partial schematic view of an alternative embodiment of a display panel according to an embodiment of the invention;

FIG. 5 is a partial schematic view of an alternative embodiment of a display panel according to an embodiment of the invention;

FIG. 6 is a partial schematic view of an alternative embodiment of a display panel according to an embodiment of the invention;

FIG. 7 is a partial schematic view of an alternative embodiment of a display panel according to an embodiment of the invention;

FIG. 8 is a schematic diagram of another alternative embodiment of a display panel according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another alternative embodiment of a display panel according to an embodiment of the present invention;

fig. 10 is a schematic view of a display device according to an embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Fig. 1 is a partial schematic view of a display panel according to an embodiment of the present invention, as shown in fig. 1, the display panel includes a display area AA and a non-display area BA, the display area AA has a gap K, the display area AA includes a first display area AA1 and a second display area AA2, the two first display areas AA1 are located on two sides of the gap K in a first direction a, the second display area AA2 is located on at least one side of the gap K in a second direction b, the non-display area BA includes a gap non-display area BAK and two first non-display areas BA1, the gap non-display area BAK is at least half around the gap K, the first non-display area BA1 is located on a side of the first display area AA1 away from the gap K, and the first direction a intersects with the second direction b; the shape of the notch K is not limited in the embodiment of the present invention, and the notch K may be a rectangle illustrated in fig. 1, or may also be a circle, a triangle, a trapezoid, or another shape. In the embodiment of the present invention, the two first display areas AA1 are respectively located at two sides of the notch K, wherein the two first display areas AA1 may have the same size or different sizes, and the lengths of the two first display areas AA1 along the first direction a may be the same or different. Alternatively, in one embodiment, the gap K is located at the center of the display area in the first direction, that is, the lengths of the two first display areas AA1 along the first direction a are the same.

The display panel includes a plurality of gate lines S extending along a first direction a, the gate lines S including a first gate line 1S and a second gate line 2S, the first gate line 1S being located in the first display area AA1, and the second gate line 2S being located in the second display area AA 2; the first gate line 1S includes first a gate lines 1SA and first b gate lines 1SB, the first a gate lines 1SA and the first b gate lines 1SB are alternately arranged in the second direction b, the first display area AA1 includes first pixel rows PL1 arranged in the second direction b, one first pixel row PL1 is connected to one first a gate line 1SA and one first b gate line 1SB, respectively, that is, one first pixel row PL1 is commonly driven by one first a gate line 1SA and one first b gate line 1 SB. As illustrated in fig. 1, the first a gate line 1SA and the first b gate line 1SB electrically connected to one first pixel row PL1 are located on both sides of the first pixel row PL1 in the second direction b. In fig. 1, in order to clearly distinguish the first a-gate line 1SA from the first b-gate line 1SB, the first a-gate line 1SA is represented by a thick line, and the first b-gate line 1SB is represented by a thin line, where the thick line and the thin line do not represent the line width relationship between the first a-gate line 1SA and the first b-gate line 1SB in an actual product.

Taking the first display area AA1 on the left side of the gap K as an example, which is schematically shown in fig. 1, from top to bottom, the 1 st first gate line, the 1 st second gate line, the 2 nd first gate line, the 2 nd second gate line, the 3 rd first gate line, the 3 rd second gate line, the 4 th first gate line, the 4 th second gate line, and so on are sequentially arranged. From top to bottom, the first pixel row in the 1 st row, the first pixel row in the 2 nd row, the first pixel row in the 3 rd row, the first pixel row in the 4 th row, and so on are arranged in sequence. Optionally, each pixel row includes a plurality of sub-pixels electrically connected to the gate lines.

Fig. 2 is a schematic diagram of an alternative implementation of a pixel circuit in a display panel according to an embodiment of the present invention, and fig. 3 is a timing diagram of the pixel circuit shown in fig. 2. As shown in fig. 2, taking only the pixel circuit including 7 transistors (T1 to T7) and 1 capacitor C as an example, the pixel circuit includes a first Scan signal terminal Scan1, a second Scan signal terminal Scan2, a data signal terminal D, a positive electrode power terminal PVDD, a negative electrode power terminal PVEE, a reset signal terminal Ref, and a light emission signal terminal Emit, and a first node N1, a second node N2, a third node N3, and a fourth node N4. In the first display area AA1 of the display panel according to the embodiment of the invention, the first b gate line 1SB is electrically connected to the first Scan signal terminal Scan1, and the first a gate line 1SA is electrically connected to the second Scan signal terminal Scan 2.

Referring to the timing diagram shown in fig. 3, the operation phases of the pixel circuit can be divided into: an initialization phase t1, a data writing phase t2 and a pixel light emission phase t 3. At initialization stage t 1: the first Scan signal terminal Scan1 receives an active level signal, the reset signal received from the reset signal terminal Ref initializes the first node N1, and the reset signal resets the fourth node N4. At the data writing stage t 2: at this stage, the transistor T4 supplies the signal of the third node N3 to the first node N1 under the control of the active level signal, so that the threshold compensation of the driving transistor T7 is realized. In the pixel lighting period t 3: the emission signal end Emit inputs an effective level signal to control the transistor T5 to be turned on, an anode power supply signal input by an anode power supply end PVDD is provided to the second node N2, the driving transistor T7 maintains a certain on-state for a certain time until being turned off, at this stage, the second node N2 provides a voltage signal to the third node N3, the transistor T6 is in an on-state, and a signal of the third node N3 is provided to the fourth node N4, so that the light-emitting device emits light after the anode of the light-emitting device is charged by the fourth node N4 to reach a lighting voltage. Wherein one sub-pixel includes one light emitting device.

It should be noted that the schematic diagrams of fig. 2 and 3 are only for illustrating the operation principle of the first a gate line 1SA and the first b gate line 1SB, and the pixel circuit is not limited to the invention.

The first gate line 1S includes a first end far away from the notch K and a second end close to the notch K, that is, the first end is an end of the first gate line 1S close to the first non-display area BA1, and the second end is an end of the first gate line 1S close to the notch K, which are not labeled in the figure. Each of the first a gate line 1SA and the first b gate line 1SB includes a first end and a second end. The second end of the 3m +1 th first A gate line is electrically connected with the second end of the 3m +2 th first A gate line, the second end of the 3m +1 th first B gate line is electrically connected with the second end of the 3m +2 th first B gate line, wherein m is more than or equal to 0, and m is an integer; the second ends of two first gate lines (3 m +3) located on two sides of the notch K in the first direction a are electrically connected through a first connecting line LXA, the second ends of two first second gate lines (3 m +3) located on two sides of the notch K in the first direction a are electrically connected through a second connecting line LXB, and the first connecting line LXA and the second connecting line LXB are both located in the notch non-display area BAK.

Taking m as 0 as an example, in the position of the area Q1 in fig. 1, the second end of the 1 st first gate line and the second end of the 2 nd first gate line are electrically connected; referring to the location of the area Q2 in fig. 1, the second end of the 1 st first second gate line is electrically connected to the second end of the 2 nd first second gate line. Second ends of two 3 rd first gate lines respectively positioned at two sides of the notch K in the first direction a are electrically connected through a first connecting line LXA, and second ends of two 3 rd first second gate lines respectively positioned at two sides of the notch K in the first direction a are electrically connected through a second connecting line LXB. The above explanation explains the respective connection relationships of the three first a gate lines and the three first b gate lines that drive the 1 st to 3 rd first pixel rows. By analogy, it can be seen that when m is 1, the respective connection relationships of the three first a gate lines and the three first b gate lines of the 4 th to 6 th first pixel rows are driven.

The display panel includes a gate driving circuit including a first gate shift register S1VSR and a second gate shift register S2VSR, the plurality of cascaded first gate shift registers S1VSR are located in one first non-display area BA1, and the plurality of cascaded second gate shift registers S2VSR are located in another first non-display area BA 1. The cascade-connected first gate shift registers S1VSR are connected in series, namely the output end of the first gate shift register S1VSR at the previous stage is electrically connected with the input end of the first gate shift register S1VSR at the next stage; the plurality of cascaded second gate shift registers S2VSR, that is, the output terminal of the previous stage second gate shift register S2VSR is electrically connected to the input terminal of the next stage second gate shift register S2 VSR. Referring to the illustration in fig. 1, in the first non-display area BA1 on the left side of the notch K, a plurality of cascaded first gate shift registers S1VSR includes sequentially cascaded: a 0 th stage first gate shift register S1VSR0, a1 st stage first gate shift register S1VSR1, a2 nd stage first gate shift register S1VSR2, a 3 rd stage first gate shift register S1VSR3, and so on; in the first non-display area BA1 on the right side of the notch K, a plurality of cascaded second gate shift registers S2VSR include sequentially cascaded: the 0 th stage second gate shift register S2VSR0, the 1 st stage second gate shift register S2VSR1, the 2 nd stage second gate shift register S2VSR2, the 3 rd stage second gate shift register S2VSR3, and so on.

On the side of the notch K in the first direction a: the first ends of the 3m +1 th first gate line A and the 3m +3 th first gate line B are electrically connected with the output end of the 2m +1 th stage first gate shift register; the first end of the 3m +1 th first B grid line is electrically connected with the output end of the 2 m-th stage first grid shift register; the first end of the 3m +3 first gate line is electrically connected with the output end of the 2m +2 stage first gate shift register; on the other side of the notch K in the first direction a: the first end of the 3m +1 th first gate line is electrically connected with the output end of the 2m +1 th-stage second gate shift register; the first end of the 3m +1 th first B grid line is electrically connected with the output end of the 2 m-th-stage second grid shift register; the first ends of the 3m +3 th first A gate line and the 3m +3 th first B gate line are not electrically connected with the output end of the second shift register.

Continuing with the description when m is 0, as illustrated in fig. 1, on the left side of the notch K in the first direction a: the first end of the 1 st first gate line A and the first end of the 3 rd first gate line B are electrically connected with the output end of the 1 st stage first gate shift register S1VSR 1; the first end of the 1 st first B gate line is electrically connected with the output end of the 0 th stage first gate shift register S1VSR 0; the first end of the 3 rd first gate line is electrically connected to the output end of the 2 nd stage first gate shift register S1VSR 2. That is, the output terminal of the 0 th stage first gate shift register S1VSR0 is electrically connected to the first terminal of the 1 st first second gate line and the input terminal of the 1 st stage first gate shift register S1VSR 1; the output end of the 1 st stage first gate shift register S1VSR1 is electrically connected with the first end of the 1 st first A gate line, the first end of the 3 rd first B gate line and the input end of the 2 nd stage first gate shift register S1VSR 2; the output terminal of the 2 nd stage first gate shift register S1VSR2 is electrically connected to the first terminal of the 3 rd first A gate line, the first terminal of the 4 th first B gate line, and the input terminal of the 3 rd stage first gate shift register S1VSR 3. On the right side of the notch K in the first direction a: the first end of the 1 st first gate line is electrically connected with the output end of the 1 st-stage second gate shift register S2VSR 1; the first end of the 1 st first B gate line is electrically connected with the output end of the 0 th-stage second gate shift register S2VSR 0; the first end of the 3 rd first A gate line and the first end of the 3 rd first B gate line are not electrically connected with the output end of the second shift register.

In the display panel provided in the embodiment of the present invention, the two first display areas are respectively located at two sides of the notch in the first direction, the first a gate line and the first b gate line that drive the first pixel row of the 3m +1 th row and the 3m +2 th row in the two first display areas are both driven by a single side, and no wire is wound in the notch non-display area. Two first grid lines of the first pixel rows of the 3m +3 th rows in the two first display areas are driven to be electrically connected through first connecting lines positioned in the gap non-display areas; and two first B gate lines driving the corresponding first pixel rows in the 3m +3 th row in the two first display areas are electrically connected through B connecting lines positioned in the gap non-display areas. And, the first a gate line and the first b gate line driving the first pixel row of the 3m +3 th row in the two first display areas are also driven by a single side. Compared with the prior art, the invention reduces two thirds of winding in the gap non-display area, saves space and is beneficial to narrowing the gap non-display area. And moreover, the concentration degree of the windings in the gap non-display area can be weakened, the coupling effect among the metal windings can be weakened, and the display stability is improved.

In addition, in the embodiment of the present invention, on one side of the notch, two first gate lines driving the first pixel rows in the 3m +1 th row and the 3m +2 th row are electrically connected at one side close to the notch, and two first gate lines driving the first pixel rows in the 3m +1 th row and the 3m +2 th row are electrically connected at one side close to the notch. And only the first gate line a and the first gate line b driving the 3m +1 th row are respectively and electrically connected with the gate shift register at the side far away from the notch, so that the first pixel row of the 3m +2 th row is equivalent to the extension of the first pixel row of the 3m +1 th row, that is, the output end of one gate shift register can be used for driving the first pixel row of the 3m +1 th row and the first pixel row of the 3m +2 th row at the same time after outputting signals. Meanwhile, the first pixel rows of the two 3m +3 th rows respectively positioned at the two sides of the notch are also driven by signals output by the output end of the same grid shift register. The voltage drop on each first gate line A and each first gate line B can be balanced, the voltage drop on each gate line in the first display area is approximately the same, the brightness of sub-pixels driven by each gate line is approximately the same, and the display brightness of the display panel is uniform.

In addition, the connection mode of the first gate lines and the gate shift registers provided in the embodiment of the present invention is equivalent to that two cascaded gate shift registers drive three first pixel rows arranged in sequence, so that the number of the gate shift registers arranged in the first non-display region is reduced, the space is saved, and the narrowing of the first non-display region is facilitated.

In an embodiment, fig. 4 is a partial schematic view of an alternative implementation manner of the display panel according to the embodiment of the invention, as shown in fig. 4, the second gate line 2S includes a second gate line 2SA and a second gate line 2SB, the second gate line 2SA and the second gate line 2SB are alternately arranged in the second direction b, the second display area AA2 includes a second pixel row PL2 arranged in the second direction b, and one second pixel row PL2 is respectively connected to one second gate line 2SA and one second gate line 2 SB; the principle that the second gate line 2SA and the second gate line 2SB drive the sub-pixels in the second pixel line PL2 for displaying can refer to the principle description of the pixel circuit illustrated in fig. 2, and is not repeated herein. In fig. 4, in order to clearly distinguish the second gate line 2SA from the second gate line 2SB, the second gate line 2SA is represented by a thick line, and the second gate line SB is represented by a thin line, where the thick line and the thin line do not represent the line width relationship between the second gate line 2SA and the second gate line SB in an actual product.

The gate driving circuit further includes a third gate shift register S3VSR and a fourth gate shift register S4VSR, the plurality of cascaded third gate shift registers S3VSR are located in one first non-display area BA1, and the plurality of cascaded fourth gate shift registers S4VSR are located in another first non-display area BA 1; for the cascade connection manner of the gate shift registers, reference may be made to the explanation of the plurality of cascaded first gate shift registers S1VSR, which is not described herein again.

In the embodiment of the invention, one end of the 2n +1 th second gate line and one end of the 2n +2 nd second gate line are electrically connected with the output end of the 2n +1 th-stage third gate shift register; the other end of the 2n +1 th second grid line and the other end of the 2n +2 th second grid line are electrically connected with the output end of the 2n +1 th-stage fourth grid shift register, wherein n is not less than 0 and is an integer; taking the case where n is 0 as an example, as illustrated in fig. 4, taking gate lines from top to bottom as an example, one end of the 1 st second gate line 2SA and one end of the 2 nd second gate line 2SB are both electrically connected to the output end of the 1 st third gate shift register S3VSR 1; the other end of the 1 st second gate line 2SA and the other end of the 2 nd second gate line 2SB are electrically connected to the output end of the 1 st stage fourth gate shift register S4VSR 1.

One end of the 2n +1 second gate line is electrically connected with the output end of the 2 n-th-stage third gate shift register, and the other end of the 2n +1 second gate line is electrically connected with the output end of the 2 n-th-stage fourth gate shift register; taking the case where n is equal to 0 as an example, as illustrated in fig. 4, one end of the 1 st second gate line 2SB is electrically connected to the output end of the 0 th-stage third gate shift register S3VSR0, and the other end of the 1 st second gate line 2SB is electrically connected to the output end of the 0 th-stage fourth gate shift register S4VSR 0.

One end of the 2n +2 th second gate line is electrically connected with the output end of the 2n +2 nd stage third gate shift register, and the other end of the 2n +2 th second gate line is electrically connected with the output end of the 2n +2 nd stage fourth gate shift register. Taking the case where n is 0 as an example, as illustrated in fig. 4, one end of the 2 nd second gate line 2SA is electrically connected to the output terminal of the 2 nd third gate shift register S3VSR2, and the other end of the 2 nd second gate line 2SA is electrically connected to the output terminal of the 2 nd fourth gate shift register S4VSR 2.

The display panel provided by the embodiment is firstly arranged in a mode of connecting the first gate line in the first display area and the gate shift register, and compared with the related art, two thirds of winding wires are reduced in the gap non-display area, so that the space is saved, and the narrowing of the gap non-display area is facilitated. And moreover, the concentration degree of the windings in the gap non-display area can be weakened, the coupling effect among the metal windings can be weakened, and the display stability is improved. The three first pixel rows which are sequentially arranged are driven by the two cascaded gate shift registers, the driving mode is favorable for balancing the voltage drop on each first gate line A and each first gate line B, the voltage drop on each gate line in the first display area is ensured to be approximately the same, the brightness of the sub-pixels driven by each gate line is ensured to be approximately the same, and the display brightness of the display panel is ensured to be uniform. Meanwhile, the number of grid shift registers arranged in the first non-display area can be reduced, the space is saved, and the first non-display area is narrowed. In addition, in this embodiment, the output end of the gate shift register driving the second gate line is electrically connected to one second gate line and one second gate line, and the one second gate line respectively drive two adjacent second pixel rows, so that one gate shift register drives two adjacent second pixel rows. And the two ends of one second gate line in the second display area are respectively and electrically connected with the output end of one gate shift register, so that the bilateral driving of the second gate line is realized, the voltage drop at each position of one second gate line is favorably ensured to be the same, the brightness of each sub-pixel in the second pixel row is ensured to be consistent, and the display effect is improved.

Continuing to refer to the illustration in fig. 4, the first gate shift register S1VSR and the third gate shift register S3VSR are located in the same first non-display area BA1, and the first gate shift register S1VSR is not cascaded with the third gate shift register S3 VSR; the second gate shift register S2VSR and the fourth gate shift register S4VSR are located in the same first non-display area BA1, and the second gate shift register S2VSR is not cascaded with the fourth gate shift register S4 VSR. In fig. 4, for example, when the gate lines are driven, the second gate lines 2S in the second display area AA2 are sequentially driven first, and then the first gate lines 1S in the first display area AA1 are sequentially driven. The last stage of gate shift register driving the last row of second gate lines 2S is not electrically connected to the first stage of gate shift register driving the first row of first gate lines 1S. Taking the left side of the notch K in the figure as an example, the 5 th stage third gate shift register S3VSR5 is not electrically connected to the 1 st stage first gate shift register S1VSR 1. That is, the gate shift register driving the first display area AA1 needs to be re-supplied with a driving signal. Because the connection mode of the first gate line and the gate shift register is different from the connection mode of the second gate line and the gate shift register, the embodiment can set corresponding driving signals for driving the cascaded gate shift registers of each display area according to the connection mode, thereby avoiding abnormal driving and ensuring normal display of the first display area and the second display area.

In an embodiment, fig. 5 is a partial schematic view of an alternative implementation manner of the display panel according to the embodiment of the present invention, as shown in fig. 5, the display panel includes a plurality of light-emitting control lines E extending along a first direction a, where the light-emitting control lines E include a first light-emitting control line 1E and a second light-emitting control line 2E, the first light-emitting control line 1E is located in a first display area AA1, and the second light-emitting control line 2E is located in a second display area AA 2; in the first display area AA1, one first pixel line PL1 is connected to one first light-emitting control line 1E; referring to the pixel circuit illustrated in fig. 2 described above, the emission control line E is electrically connected to the emission signal terminal Emit in the pixel circuit, and supplies an emission control signal to the emission signal terminal Emit when the pixel is driven to Emit light.

The display panel further includes a light emission driving circuit including a first light emission shift register E1VSR, the plurality of cascaded first light emission shift registers E1VSR being located in the first non-display area BA 1; the output end of the first cascaded light emitting shift register E1VSR, that is, the output end of the first light emitting shift register E1VSR at the previous stage, is electrically connected to the input end of the first light emitting shift register E1VSR at the next stage. Referring to the illustration in fig. 5, in the first non-display area BA1 on one side of the notch K, a plurality of cascaded first light emitting shift registers E1VSR includes sequentially cascaded: the first light emitting shift register E1VSR1 of stage 1, the first light emitting shift register E1VSR2 of stage 2, the first light emitting shift register E1VSR3 of stage 3, and so on.

On either side of the notch K in the first direction a: the pth first light emission control line 1E is electrically connected to an output end of the pth first light emission shift register, where p >0, and p is an integer. As shown in fig. 5 only on the side of the notch K. From top to bottom, the first display area AA1 includes a1 st first emission control line 1E, a2 nd first emission control line 1E, a 3 rd first emission control line 1E, and so on, which are arranged in sequence. Wherein, the output end of the 1 st stage first light emitting shift register E1VSR1 is electrically connected with the 1 st first light emitting control line 1E and the input end of the 2 nd stage first light emitting shift register E1VSR 2; the output terminal of the 2 nd stage first light emitting shift register E1VSR2 is electrically connected to the 2 nd first light emitting control line 1E and the input terminal of the 3 rd stage first light emitting shift register E1VSR3, the output terminal of the 3 rd stage first light emitting shift register E1VSR3 is electrically connected to the 3 rd first light emitting control line 1E and the input terminal of the 4 th stage first light emitting shift register E1VSR4, and so on.

It should be noted that, in order to clearly illustrate the connection between the light-emitting control line and the light-emitting shift register in the first display area, the gate line in the display area is not shown in fig. 5, and as for the connection manner between the gate line and the gate shift register, reference may be made to any one of the above embodiments, that is, the embodiment may be combined with any one of the above embodiments.

The display panel provided by the embodiment is firstly arranged in a mode of connecting the first gate line and the gate shift register in the first display area, two thirds of winding wires are reduced in the gap non-display area, the space is saved, and the narrowing of the gap non-display area is facilitated. And moreover, the concentration degree of the windings in the gap non-display area can be weakened, the coupling effect among the metal windings can be weakened, and the display stability is improved. The voltage drop on each first gate line A and each first gate line B can be balanced, the voltage drop on each gate line in the first display area is approximately the same, the brightness of sub-pixels driven by each gate line is approximately the same, and the display brightness of the display panel is uniform. In addition, the first light-emitting control line in the first display area is driven by a single side in the embodiment, and a winding wire connected with the first light-emitting control line is not required to be arranged in the gap non-display area, so that the space of the gap non-display area is further saved, and the density of wiring in the gap non-display area is further reduced. In addition, in the first display area, two first light-emitting control lines respectively connected with the 3m +1 th first pixel row and the 3m +2 th first pixel row are electrically connected with different light-emitting shift registers, so that the 3m +1 th first pixel row and the 3m +2 th first pixel row can be prevented from being simultaneously lighted.

In an embodiment, fig. 6 is a partial schematic view of an alternative implementation manner of the display panel according to the embodiment of the present invention, as shown in fig. 6, the display panel includes a plurality of light-emitting control lines E extending along a first direction a, where the light-emitting control lines E include a first light-emitting control line 1E and a second light-emitting control line 2E, the first light-emitting control line 1E is located in a first display area AA1, and the second light-emitting control line 2E is located in a second display area AA 2; in the first display area AA1, one first pixel line PL1 is connected to one first light-emitting control line 1E;

the display panel further includes a light emission driving circuit including a first light emission shift register E1VSR, the plurality of cascaded first light emission shift registers E1VSR being located in the first non-display area BA 1;

on either side of the notch K in the first direction a: the q-th first light-emitting control line and the q + 2-th first light-emitting control line are electrically connected with the output end of the (q + 1)/2-th-stage first light-emitting shift register, wherein q is 4u +1, u is not less than 0, and u is an integer; and the (q +1) th first light-emitting control line and the (q +3) th first light-emitting control line are electrically connected with the output end of the (q + 3)/2-stage first light-emitting shift register. As schematically illustrated in fig. 6, the first display area AA1 includes a1 st first emission control line 1E, a2 nd first emission control line 1E, a 3 rd first emission control line 1E, and so on, which are sequentially arranged from top to bottom.

When u is 0, q is 1, and as illustrated in fig. 6, the 1 st first emission control line 1E and the 3 rd first emission control line 1E are electrically connected to the output terminal of the 1 st stage first emission shift register E1VSR 1; the 2 nd first light emission control line 1E and the 4 th first light emission control line 1E are electrically connected to the output terminal of the 2 nd stage first light emission shift register E1VSR 2. That is, the output terminal of the 1 st stage first light emitting shift register E1VSR1 is electrically connected to the 1 st and 3 rd first light emitting control lines 1E and the input terminal of the 2 nd stage first light emitting shift register E1VSR 2; the output terminal of the 2 nd stage first light emitting shift register E1VSR2 is electrically connected to the 2 nd and 4 th first light emitting control lines 1E and the input terminal of the 3 rd stage first light emitting shift register E1VSR 3.

When u is 1, q is 5, as illustrated in fig. 6, the 5 th first light emission control line 1E and the 7 th first light emission control line 1E are electrically connected to the output terminal of the 3 rd stage first light emission shift register E1VSR 3; the 6 th and 8 th first light emission control lines 1E and 1E are electrically connected to the output terminal of the 4 th stage first light emission shift register E1VSR 4.

It should be noted that, in order to clearly illustrate the connection between the light-emitting control line and the light-emitting shift register in the first display area, the gate line in the display area is not shown in fig. 6, and as for the connection manner between the gate line and the gate shift register, reference may be made to any one of the above embodiments, that is, this embodiment may be combined with any one of the above embodiments.

In this embodiment, the first light-emitting control line in the first display region is driven by a single side, and a winding connected to the first light-emitting control line is not required to be disposed in the notched non-display region, which is beneficial to further saving the space of the notched non-display region and further reducing the density of the wiring in the notched non-display region. In addition, one first light emitting shift register is electrically connected with the two first light emitting control lines, so that the number of the first light emitting shift registers can be reduced, and the space of the first non-display area can be saved. Two first light-emitting control lines for driving two adjacent first pixel rows are electrically connected with different light-emitting shift registers, and two first light-emitting control lines respectively connected with the 3m +1 th first pixel row and the 3m +2 th first pixel row are electrically connected with different light-emitting shift registers, so that the 3m +1 th first pixel row and the 3m +2 th first pixel row can be prevented from being simultaneously lighted.

In an embodiment, fig. 7 is a partial schematic view of an alternative implementation manner of the display panel according to the embodiment of the invention, as shown in fig. 7, the second display area AA2 includes second pixel rows PL2 arranged in the second direction b, and one second pixel row PL2 is driven by one second light emission control line 2E;

the light-emission driving circuit includes a second light-emission shift register E2VSR and a third light-emission shift register E3VSR, the plurality of cascaded second light-emission shift registers E2VSR are located at one first non-display area BA1, and the plurality of cascaded third light-emission shift registers E3VSR are located at the other first non-display area BA 1; for the cascade connection manner of the plurality of cascaded second light-emitting shift registers E2VSR and the cascade connection manner of the plurality of cascaded third light-emitting shift registers E3VSR, reference may be made to the above description of the plurality of cascaded first light-emitting shift registers E1VSR, which is not described herein again.

As shown in fig. 7, one second light emission control line 2E has one end electrically connected to the second light emission shift register E2VSR and the other end electrically connected to the third light emission shift register E3 VSR.

In this embodiment, two ends of one second light-emitting control line are respectively electrically connected to one light-emitting shift register, so that bilateral driving of the second light-emitting control line is realized, voltage drops at all positions of one second light-emitting control line are guaranteed to be the same, brightness of sub-pixels in a second pixel row is guaranteed to be consistent, and display effect is improved.

In fig. 7, the connection manner between the first emission control line and the emission shift register in the first display region is only illustrated in the case of the embodiment of fig. 5. Optionally, the connection manner of the first light-emitting control line and the light-emitting shift register provided in the embodiment of fig. 6 may also be applied in the embodiment corresponding to fig. 7, and is not described herein again.

As shown in fig. 7, the first emission shift register E1VSR and the second emission shift register E2VSR located in the same first non-display area BA1 are not cascaded, and the first emission shift register E1VSR and the third emission shift register E3VSR located in the same first non-display area BA1 are not cascaded. In fig. 7, the emission control lines are driven by sequentially driving the second emission control lines 2E in the second display area AA2 first and then sequentially driving the first emission control lines 1E in the first display area AA 1. The last stage of the light emitting shift register driving the last row of the second light emitting control line 2E is not electrically connected to the first stage of the gate shift register driving the first row of the first light emitting control line 1E. Taking the left side of the notch K in the figure as an example, the 5 th-stage second light-emitting shift register E2VSR5 is not electrically connected to the 1 st-stage first light-emitting shift register E1VSR 1. That is, the light emitting shift register driving the first display area AA1 needs to be given a driving signal again. Because the connection mode of the first light-emitting control line and the light-emitting shift register is different from the connection mode of the second light-emitting control line and the light-emitting shift register, the embodiment can set corresponding driving signals for driving the cascaded light-emitting shift registers of each display area according to the connection mode, thereby avoiding abnormal driving and ensuring that the first display area and the second display area can normally display.

In an embodiment, fig. 8 is a schematic diagram of another alternative implementation of the display panel according to the embodiment of the present disclosure. As shown in fig. 8, the edge of the display area AA is recessed inward in the second direction b to form a notch K. In this embodiment, two first display areas AA1 are respectively located at both sides of the notch K in the first direction a, and one second display area AA2 is located at one side of the notch K in the second direction b. In the display panel provided in this embodiment, the connection manner between the first gate line in the first display area and the gate shift register, the connection manner between the first light-emitting control line in the first display area and the light-emitting shift register, the connection manner between the second gate line in the second display area and the gate shift register, the connection manner between the second light-emitting control line in the second display area and the light-emitting shift register, and the like may all adopt the implementation manners in any of the above embodiments.

In an embodiment, fig. 9 is a schematic diagram of another alternative implementation of the display panel according to the embodiment of the present disclosure. As shown in fig. 9, the display areas AA surround the gap K, and two second display areas AA2 are respectively located at both sides of the gap K in the second direction b. In the display panel provided in this embodiment, the connection manner between the first gate line in the first display area and the gate shift register, the connection manner between the first light-emitting control line in the first display area and the light-emitting shift register, the connection manner between the second gate line in the second display area and the gate shift register, the connection manner between the second light-emitting control line in the second display area and the light-emitting shift register, and the like may all adopt the implementation manners in any of the above embodiments.

In addition, in the embodiment corresponding to fig. 9, a plurality of a connection lines LXA and a plurality of b connection lines LXB (not shown in fig. 9) are disposed in the notch non-display area BAK. Optionally, when the plurality of first connecting lines LXA and the plurality of second connecting lines LXB are wound in the notch non-display area BAK, the plurality of first connecting lines LXA and the plurality of second connecting lines LXB can be uniformly dispersed and arranged on two sides of the notch K in the second direction b, so that the widths of the notch non-display area BAK on two sides of the notch K are approximately the same, and the attractiveness of the display panel is improved.

Based on the same inventive concept, the present invention further provides a display device, and fig. 10 is a schematic view of the display device according to the embodiment of the present invention, and as shown in fig. 10, the display device includes the display panel 100 according to any embodiment of the present invention. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 10 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A display panel is characterized by comprising a display area and a non-display area, wherein the display area is provided with a gap and comprises a first display area and a second display area, the two first display areas are positioned at two sides of the gap in a first direction, the second display area is positioned at least one side of the gap in a second direction, the non-display area comprises a gap non-display area and two first non-display areas, the gap non-display area is at least semi-arranged around the gap, the first non-display areas are positioned at one side of the first display areas far away from the gap, and the first direction is crossed with the second direction;

the display panel comprises a plurality of gate lines extending along the first direction, the gate lines comprise a first gate line and a second gate line, the first gate line is located in the first display area, and the second gate line is located in the second display area; the first gate lines include first a gate lines and first b gate lines, the first a gate lines and the first b gate lines are alternately arranged in the second direction, the first display region includes first pixel rows arranged in the second direction, and one first pixel row is connected to one first a gate line and one first b gate line, respectively;

the first gate line comprises a first end far away from the notch and a second end close to the notch, the second end of the 3m +1 first A gate line is electrically connected with the second end of the 3m +2 first A gate line, the second end of the 3m +1 first B gate line is electrically connected with the second end of the 3m +2 first B gate line, wherein m is more than or equal to 0, and m is an integer; the second ends of two 3m +3 first grid lines respectively positioned at two sides of the notch in the first direction are electrically connected through a first connecting line, the second ends of two 3m +3 first grid lines respectively positioned at two sides of the notch in the first direction are electrically connected through a second connecting line, and the first connecting line and the second connecting line are positioned in the notch non-display area;

on one side of the notch in the first direction: the first end of the 3m +1 th first gate line and the first end of the 3m +3 th first gate line are electrically connected with the output end of the 2m +1 th stage first gate shift register; the first end of the 3m +1 th second grid line is electrically connected with the output end of the 2 m-th stage first grid shift register; the first end of the 3m +3 first gate line is electrically connected with the output end of the 2m +2 stage first gate shift register;

on the other side of the notch along the first direction: the first end of the 3m +1 th first gate line is electrically connected with the output end of the 2m +1 th stage second gate shift register; the first end of the 3m +1 th second grid line is electrically connected with the output end of the 2 m-th-stage second grid shift register; the 3m +3 first ends of the first gate lines and the 3m +3 first ends of the first second gate lines are not electrically connected with the output end of the second shift register.

2. The display panel according to claim 1,

the second gate lines include second gate lines and second gate lines, the second gate lines and the second gate lines are alternately arranged in the second direction, the second display region includes second pixel rows arranged in the second direction, and one of the second pixel rows is connected to one of the second gate lines and one of the second gate lines, respectively;

the grid driving circuit further comprises a third grid shifting register and a fourth grid shifting register, wherein a plurality of cascaded third grid shifting registers are located in one first non-display area, and a plurality of cascaded fourth grid shifting registers are located in the other first non-display area;

one end of the 2n +1 th second gate line and one end of the 2n +2 th second gate line are electrically connected with the output end of the 2n +1 th stage third gate shift register; the other end of the 2n +1 th second grid line and the other end of the 2n +2 th second grid line are electrically connected with the output end of the 2n +1 th fourth grid shift register, wherein n is not less than 0 and is an integer;

one end of the 2n +1 th second gate line is electrically connected with the output end of the 2 n-th stage third gate shift register, and the other end of the 2n +1 th second gate line is electrically connected with the output end of the 2 n-th stage fourth gate shift register;

one end of the 2n +2 th second gate line is electrically connected with the output end of the 2n +2 th stage third gate shift register, and the other end of the 2n +2 th second gate line is electrically connected with the output end of the 2n +2 th stage fourth gate shift register.

3. The display panel according to claim 2,

the first grid electrode shift register and the third grid electrode shift register are positioned in the same first non-display area, and the first grid electrode shift register is not cascaded with the third grid electrode shift register;

the second grid electrode shift register and the fourth grid electrode shift register are located in the same first non-display area, and the second grid electrode shift register is not in cascade connection with the fourth grid electrode shift register.

4. The display panel according to claim 1,

the display panel comprises a plurality of light emitting control lines extending along the first direction, the light emitting control lines comprise a first light emitting control line and a second light emitting control line, the first light emitting control line is located in the first display area, and the second light emitting control line is located in the second display area;

in the first display area, one first pixel row is connected with one first light-emitting control line;

the display panel further comprises a light-emitting driving circuit, wherein the light-emitting driving circuit comprises a first light-emitting shift register, and a plurality of cascaded first light-emitting shift registers are positioned in the first non-display area;

either side of the notch in the first direction: the p-th first light-emitting control line is electrically connected with the output end of the p-th first light-emitting shift register, wherein p >0 and p is an integer.

5. The display panel according to claim 1,

either side of the notch in the first direction: the q-th first light-emitting control line and the q + 2-th first light-emitting control line are electrically connected with the output end of the (q + 1)/2-th stage first light-emitting shift register, wherein q is 4u +1, u is not less than 0, and u is an integer; and the (q +1) th first light-emitting control line and the (q +3) th first light-emitting control line are electrically connected with the output end of the (q + 3)/2-th stage first light-emitting shift register.

6. The display panel according to claim 4 or 5,

the second display region includes second pixel rows arranged in the second direction, one of the second pixel rows being driven by one of the second emission control lines;

the light-emitting driving circuit comprises a second light-emitting shift register and a third light-emitting shift register, wherein a plurality of cascaded second light-emitting shift registers are positioned in one first non-display area, and a plurality of cascaded third light-emitting shift registers are positioned in the other first non-display area; wherein the content of the first and second substances,

one end of one of the second light-emitting control lines is electrically connected with the second light-emitting shift register, and the other end of the one of the second light-emitting control lines is electrically connected with the third light-emitting shift register.

7. The display panel according to claim 6,

the first light-emitting shift register and the second light-emitting shift register in the same first non-display area are not cascaded, and the first light-emitting shift register and the third light-emitting shift register in the same first non-display area are not cascaded.

8. The display panel according to claim 1,

the edge of the display area is inwards recessed along the second direction to form the notch.

9. The display panel according to claim 1,

the display areas surround the gap, and in the second direction, the two second display areas are respectively located on two sides of the gap.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.