CN1106145A - Signal processing method between analog driver and power amplifier and interface circuit - Google Patents
Signal processing method between analog driver and power amplifier and interface circuit Download PDFInfo
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- CN1106145A CN1106145A CN 94105897 CN94105897A CN1106145A CN 1106145 A CN1106145 A CN 1106145A CN 94105897 CN94105897 CN 94105897 CN 94105897 A CN94105897 A CN 94105897A CN 1106145 A CN1106145 A CN 1106145A
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Abstract
The signal processing method between analog activator and power amplifier of long wave/ultra-long wave transmitter features that a trigger timing sequence for squar-wave inverse transforming devices to form stepped sine wave is obtained by transverse shearing method and different sine signals are obtained by triggering different numbers of inverse transforming devices. Its interface is composed of amplitude comparing timer, pulse order inverter and drive pulse generator. With said method and interface, the messages in different formats (OKK, FSK, MSK1, MSK2 and MSK4) may be amplified without distortion.
Description
The present invention relates to signal processing method (analog-signal transitions is become switching pulse signal) and interface circuit between a kind of transmitter analog driver that particularly long wave/the myriameter waves transmitter is used and the switch power amplifier.
The present invention relates to a kind of like this prior art: promptly as a kind of digital controllable direct current-sine-inverter of forming by digit driver and switch power amplifier that is used for the very low frequency (VLF) transmitter that " is applied in the high power DC-sinewave inverter transistorization power combination of very low frequency (VLF) transmitter " and introduced of one piece of translation in " the radio and television communication technology " (monograph) " myriameter waves ELF to dive communication collected works ".Switch power amplifier is nearly ten years high efficiency amplifiers that grow up.It is characterized in that:
1. two groups of direct current-sinewave inverters are arranged, produce two waveforms on all four ladder sine wave, advance wave and retarded waves respectively.
2. with 256 time sequential pulses that are divided in full week of sine wave, counter is as the serialization of ladder, and frequency synthesizer is supplied with counter to clock signal, and two ROM (read-only memory) of central control unit control produce the base drive signal on request.
3. the constant amplitude of each ladder sine wave, to requiring the output of different amplitudes, the phase place of the backfeed loop control lead and lag ripple of being formed by the analog and digital signal processor meets the requirements synthetic amplitude.
The advantage of above-mentioned solid power device is: 1. efficient height, only consider that solid state device itself can reach 95%; 2. easily realize the numerical control modulation; 3. can reach optimum Working with microporocessor software technology and FEEDBACK CONTROL; 4. a large amount of solid state device power are synthetic to have improved reliability, and the complete machine failure rate reduces.
The enforcement of above-mentioned technology has certain difficulty, particularly under the working condition of multichannel MSK.
The invention still further relates to analog driver-electron tube simulated power amplifier technology.Analog driver has been realized all indicator transmitters except that power, and performance is good, function is complete, easily realization.Analog driver with a long history reached perfection.And electron tube simulated power amplifier efficient is very low, generally can only reach 50%.
Task of the present invention is that high performance analog driver and high efficiency switch power amplifier are combined the composition high-power transmitter, particularly long wave/myriameter waves transmitter.Give full play to the advantage of these two kinds of technology.The technical problem underlying that solves is signal processing method and the interface circuit between analog driver and the power amplifier.
The present invention has provided the signal processing method between a kind of analog driver and the power amplifier, it is characterized in that:
A) sine voltage signal of simulating signal driver is compared with the way of hardware or software with reference voltage obtain a series of time pulses.Promptly obtain the unlatching and the turn-off time pulse of each ladder square wave with the sinusoidal simulating signal of the voltage cutting of certain amplitude.
B) obtain the sine wave of different amplitudes with the method for the different square-wave inverter quantity of conducting.
C) amplitude of maximum amplitude sine wave is divided into the n section, and n is the arbitrary value in the positive integer.
In the above-mentioned signal processing method, when each square-wave inverter output voltage amplitude was identical, the reference voltage of comparer was: E
REFn=(2n-1)/(2n) E.E is the maximum voltage value of analog sine voltage signal in the formula.n＝1，2，3，…。
When each square wave inverter output voltage amplitude not simultaneously, each reference voltage should be done corresponding change.
The reference voltage of being tried to achieve can be done suitably to change according to minimum requirement of sinusoidal wave distortion.
The present invention has provided a kind of analog driver of Fig. 2 stacked system and the interface circuit between the power amplifier, it is characterized in that: relatively timer (1) of an amplitude a) is arranged.Its input termination analog driver, output termination drive-pulse generator (2) and pulse sequence inversor (3).Simulating signal in timer relatively with reference voltage mutually the square wave of specific output two row different delayed time open and the turn-off time pulse.B) a pulse sequence inversor (3) is arranged, its input termination amplitude is timer (1) relatively, output termination drive-pulse generator (2).The square wave turn-off time pulse that amplitude comparison timer is produced obtains the different shutoff pulse of two row order inversion time-delay behind pulse order inversion device (3).C) drive-pulse generator (2) is arranged, form by n A, B, C, d type flip flop.Its input termination amplitude is timer (1) and pulse sequence inversor (3) relatively.The corresponding brachium pontis of output termination square-wave inverter.The time pulse of amplitude comparison timer and the output of pulse sequence inversor send corresponding A, B, C, d type flip flop in the drive-pulse generator respectively, produces a series of square wave drive pulses, triggers A, B, C, the D brachium pontis of n direct current-square-wave inverter respectively.
The present invention gives a kind of interface circuit of Fig. 1 stacked system, it is characterized in that: relatively timer (1) of an amplitude a) is arranged, its input termination analog driver, output termination drive-pulse generator (2).Simulating signal is through amplitude timer and the reference voltage time pulse of specific output two row different delayed time mutually relatively.
B) drive-pulse generator (2) is arranged, its input termination amplitude is timer relatively, the corresponding brachium pontis of output termination direct current-square-wave inverter.Drive-pulse generator is made up of n A, B, C, d type flip flop.
The present invention gives and a kind ofly realizes it is characterized in that the interface circuit of above-mentioned two kinds of square wave stacked systems with software: an A/D converter (4) a) is arranged, and is digital signal with the analog-signal transitions of analog driver output.Its input termination analog driver, output terminal connects digital signal processor (5) by data bus, and the control port of its control port and digital signal processor is interconnected.B) digital signal processor (5), its output terminals A are arranged
1, B
1, C
1, D
1, A
2, B
2, C
2, D
2... A
n, B
n, C
n, D
nMeet the A of n direct current-square-wave inverter respectively
1, B
1, C
1, D
1... A
n, B
n, C
n, D
nBrachium pontis.
Here the digital signal processor (ASDSP) that said digital signal processor can be a special use, but also can add what the parallel interface of input interface and one group of step-by-step set/reset was formed by a computing machine.
Description of drawings:
Fig. 1 is the overlaid waveforms figure of wide square wave not.
Fig. 2 is the overlaid waveforms figure of accurate wide square wave.
Fig. 3 is accurate wide direct current-square-wave inverter interface circuit schematic diagram.
Fig. 4 is the interface circuit schematic diagram that computing machine or digital signal processor are realized with software.
Fig. 5 is the relatively circuit theory diagrams of timer of amplitude.
Fig. 6 is the circuit theory diagrams of pulse sequence inversor.
Fig. 7 is the circuit theory diagrams of drive-pulse generator.
Below in conjunction with drawings and Examples interface circuit of the present invention and signal processing method are described further.
Forming sinusoidal wave technology with the stack square wave has two kinds of schemes, as shown in Figure 1 and Figure 2.Among Fig. 1, sine wave 6, its positive half cycle are to be superposeed and approximate obtaining by square-wave pulse 61,62 and 63.Equally, negative half period is to be obtained by square- wave pulse 71,72 and 73 stacks.As can be seen from Figure 1, the square wave 61 of sinusoidal wave base portion and 71 wideer than the width of square wave 62,63,72 and 73 constitutes each sinusoidal wave square wave and is narrowed down gradually to the top by the bottom.We call not wide square wave stacked system to this stacked system.Ladder sine wave shown in Figure 2, its positive half cycle be by square wave 81,82 ... obtain Deng stack, constitute each square width of sinusoidal wave 8 as seen from the figure about equally, its width changes in 90 ° to 120 ° scope.We call accurate wide square wave stacked system to this stacked system.
The interface circuit of the accurate wide direct current-square-wave inverter of Fig. 3, relatively timer 1, pulse sequence inversor 3 and drive-pulse generator 2 are formed by amplitude.The sine voltage signal that analog driver provides amplitude relatively in the timer with a series of reference voltage E
REF, E
REF... E
REFThe a series of t of output compare
1, t
2, t
3, t
4Time pulse.Compare the t of output the timer 1 from amplitude
1, t
3Series of pulses has the time-delay of τ or τ+0.2 microsecond, t
2, t
4Series of pulses is not delayed time.t
2, t
4 Pulse sequence inversor 3 is sent in pulse, obtains the pulse of a series of sequential inverted time-delay τ or τ+0.2 microsecond.The t of different delayed time
1, t
2, t
3, t
4Spike train connects the corresponding port of drive-pulse generator 2 respectively.Drive-pulse generator will provide among a series of and Fig. 2 81,82 ..., 91,92 ... the corresponding corresponding brachium pontis A of square wave excitation trigger action direct current-square-wave inverter, B, C, D.
The pulse of time-delay τ+0.2 microsecond is the unbalanced pulse of trigger output square wave, and the pulse of time-delay τ is the pulse of closing of trigger output square wave, and the effect of 0.2 microsecond of delaying time is that A, C arm or B, the conducting simultaneously of D arm of avoiding square-wave inverter cause short circuit.
The interface circuit of the not wide square wave stack of Fig. 1 and the difference of the wide interface circuit of above-mentioned standard are: no pulse order inversion device 3; And each trigger pulse of drive-pulse generator 2 is different from each trigger pulse order of accurate wide interface circuit in proper order; The unbalanced pulse of all outputs all has the time-delay of τ '+0.2 microsecond, closes the time-delay that pulse all has τ ' microsecond, and τ ' is less than τ.
The unbalanced pulse of amplitude comparison timer output and close pulse connects drive-pulse generator 2 respectively by order shown in Figure 7 corresponding port: t
11+ 0.2 microsecond meets B
1The S end of trigger, t
31Meet B
1R end; t
41+ 0.2 microsecond meets A
1S end, t
21Meet A
1R end; t
31+ 0.2 microsecond meets D
1S end, t
11Meet D
1R end; t
21+ 0.2 microsecond meets C
1S end, t
41Meet C
1R end, the m group pulse connects corresponding S end of m group trigger or R end.Trigger is exported corresponding square wave driving pulse and is triggered corresponding inverter brachium pontis, obtains the square-wave voltage of different in width.These square-wave voltage stacks obtain ladder sine wave.
The said amplitude comparison of the present invention timer is by comparer (11), and differentiating circuit (12) and chronotron (13) are formed, and see Fig. 5.Comparer has 2n, and each n of positive-negative half-cycle, 11
1... 11
m... 11
nAnd 11
1' ... 11
m', 11
n'.Each comparer has two input ends, an input termination analog driver, another input termination reference voltage generator, output termination differentiating circuit.Connect a differentiating circuit (12) behind each comparer (11), 2n altogether.The comparer output waveform gets rising edge pulse and negative edge pulse through differential.For the wide stacked system of standard, the output of differentiating circuit divides two-way, and one the tunnel connects chronotron (13), and another road connects pulse sequence inversor (3).Connect a chronotron (13) (2n altogether) behind each differentiating circuit.The rising edge pulse t that differential obtains
1And t
3Obtain a series of pulses through time-delay with time-delay τ and τ+0.2 microsecond.t
2, t
4The pulse sequence inversor is sent in the pulse of series, obtains the time-delay τ of two row order inversion and the pulse of τ+0.2 microsecond.The output of chronotron (13) connects the respective input of drive-pulse generator (2).For not wide stacked system, connect 2 chronotrons behind the differentiating circuit, 4n altogether.The rising edge pulse t that differential obtains
1, t
3With negative edge pulse t
2, t
4All through chronotron, obtain the pulse that two row time-delays are respectively τ ' and τ '+0.2 microsecond, the output of chronotron (13) connects the respective input of drive-pulse generator (2).
The said pulse sequence inversor of the present invention is made up of amplitude limit phase inverter (31), mixer (32), counter (33), code translator (34), differentiating circuit (35) and delay circuit (36), sees Fig. 6.Phase inverter (31) has 2n input port, and the corresponding port with amplitude comparison timer (1) joins respectively.Phase inverter (31) has 2n output port to connect mixer (32).The output of mixer (32) connects counter (33).The reseting port of counter (33) meets relatively first square wave unbalanced pulse t of timer of amplitude
11Or t
31Output terminal.The output of counter connects code translator (34).Each output port of code translator all connects a differentiating circuit (35).The output of differentiating circuit (35) divides two-way, and one the tunnel connects chronotron (36), and another road is the pulse output end mouth of the time-delay τ microsecond of pulse sequence inversor.Chronotron (36) is output as the pulse output end mouth of τ+0.2 microsecond of pulse sequence inversor.The output port of pulse sequence inversor connects the respective input of drive-pulse generator (2) respectively.
Spike train t
21T
2m; t
41T
4mBecome the positive pulse row through phase inverter (31) and send into mixer (32).Counter is sent in mixed pulse.Counter output connects code translator (34).The port one output and the t of code translator
2mCorresponding, port 2 output and t
2m-1Corresponding, the output of port m then with t
21Corresponding.The code translator output signal gets an order through differential and is t
2m+ τ, t
2m-1+ τ ... t
21The spike train of+τ is through delaying time: t
2m+ τ+0.2 μ S, t
2(m-1)+ τ+0.2 μ s ... t
21The spike train of+τ+0.2 μ s.Same negative half period pulse t
41T
4mBehind pulse order inversion device, get t
4m+ τ ... t
41+ τ, through delay time t
4m+ τ+0.2 μ s ... t
41+ τ+0.2 μ s, two row pulses.
Output pulse t
2m+ τ and t
4m+ τ replaces the t among Fig. 7 respectively
21And t
41Just can make among the waveform of ground floor square wave and Fig. 2 square wave 81 corresponding.Each port output pulse triggers each relative trigger device among Fig. 7 in order, just can obtain the respective party wave impulse among a series of Fig. 2.
Fig. 4 by A/D converter (4) and by input interface (21), computing machine (22) but the interface circuit of realizing with software that the digital signal processor (5) that the parallel interface sheet (23) of step-by-step set/reset is formed is formed.
The data port of the input data port of input interface (21) and A/D converter (4) is by data bus DB
1Link to each other.Control port passes through CB
1Link to each other with the control port of A/D converter.Data-out port by data bus with computing machine (22) but link to each other with the parallel interface sheet (23) of step-by-step set/reset.The data port of computing machine (22), address mouth and control mouth respectively by data bus DB, address bus AB and control bus CB with input interface (21) but link to each other with the parallel interface sheet (23) of step-by-step set/reset.But the output terminals A of the parallel interface sheet of one group of step-by-step set/reset
1, B
1, C
1, D
1, A
2, B
2, C
2, D
2... A
n, B
n, C
n, D
nControl with A, the B of n direct current-square-wave inverter, C, D brachium pontis extremely links to each other respectively.
The simulating signal of analog driver output becomes digital signal through A/D converter (4).Digital signal is sent into interface (21) by data bus.Input interface (21) is given computing machine (22) by data bus with digital signal.Computing machine (22) is compared the digital signal of sending into according to software program and is produced the instruction of a series of opsition dependents 1 and step-by-step zero setting with the reference voltage digital signal of setting.But again these instructions are given the parallel interface sheet group (23) of step-by-step set/reset by correct address.The output terminal of parallel interface sheet group provides A
1, B
1, C
1, D
1, A
2, B
2, C
2, D
2... A
m, B
m, C
m, D
mThe square wave drive pulse, trigger A, B, C, the D brachium pontis of m direct current-square-wave inverter respectively.
M≤n, m are the sinusoidal wave divided square wave numbers of plies of concrete amplitude.
The invention provides a kind of efficient, low-cost, long wave/myriameter waves simulating signal driver that circuit is simple and signal processing method and the interface circuit between the high power switch power amplifier.Its outstanding effect is: the amplitude or the frequency that analog driver can be produced are amplified without distortion with the multichannel sinusoidal signal that message information changes.Signal format comprises 00K
1, FSK, MSK
1, MSK
2, MSK
4Deng.Particularly be operated in MSK
4Modulation system, a machine is equivalent to 4 machines, has improved the usefulness of equipment greatly, has shortened the circular time, has improved the capability to resist destruction of submarine.
Claims (8)
1, the particularly analog driver used of long wave/myriameter waves transmitter and the signal processing method between the power amplifier of a kind of transmitter is characterized in that:
A) sine voltage signal of simulating signal driver is compared with the method for hardware or software with reference voltage, obtain a series of unlatchings and turn-off time pulse;
B) obtain the sine wave of different amplitudes with the method for the different square-wave inverter quantity of conducting;
C) amplitude of maximum amplitude sine wave is divided into the n section, and n is the arbitrary value in the positive integer.
2, the particularly analog driver used of long wave/myriameter waves transmitter and the interface circuit between the power amplifier of a kind of transmitter is characterized in that:
A) relatively timer (1) of an amplitude is arranged, its input termination analog driver, output termination drive-pulse generator (2) and pulse sequence inversor (3), simulating signal in timer relatively with the reference voltage square wave unlatching and the turn-off time pulse of specific output two row different delayed time mutually;
B) a pulse sequence inversor (3) is arranged, its input termination amplitude is timer (1) relatively, output termination drive-pulse generator (2), the square wave turn-off time pulse that amplitude comparison timer is produced obtain the different shutoff pulse of two row order inversion time-delay behind pulse order inversion device (3);
C) drive-pulse generator (2) is arranged, form by n A, B, C, d type flip flop, its input termination amplitude is timer (1) and pulse sequence inversor (3) relatively, output terminal has 4n, connect the corresponding brachium pontis of square-wave inverter respectively, the time pulse of amplitude comparison timer and the output of pulse sequence inversor send corresponding A, B, C, d type flip flop in the drive-pulse generator respectively, produce a series of square wave drive pulses, trigger A, B, C, the D brachium pontis of n direct current-square-wave inverter respectively.
3, the particularly analog driver used of long wave/myriameter waves transmitter and the interface circuit between the power amplifier of a kind of transmitter is characterized in that:
A) relatively timer (1) of amplitude is arranged, its input termination analog driver, output termination drive-pulse generator (2), simulating signal is through amplitude timer and the reference voltage time pulse of specific output two row different delayed time mutually relatively;
B) drive-pulse generator (2) is arranged, its input termination amplitude is timer relatively, the corresponding brachium pontis of output termination direct current-square-wave inverter, and drive-pulse generator is made up of n A, B, C, d type flip flop.
4, the particularly analog driver used of long wave/myriameter waves transmitter and the interface circuit between the power amplifier of a kind of transmitter is characterized in that:
A) A/D converter (4), with the analog-signal transitions of analog driver output is digital signal, its input termination analog driver, its output terminal connects digital signal processor (5) by data bus, and the control port of its control port and digital signal processor is interconnected;
B) digital signal processor (5), its output terminals A are arranged
1, B
1, C
1, D
1, A
2, B
2, C
2, D
2... A
n, B
n, C
n, D
nMeet the A of n direct current-square-wave inverter respectively
1, B
1, C
1, D
1A
n, B
n, C
n, D
nBrachium pontis.
5, the interface circuit between said analog driver of claim 2 and the power amplifier is characterized in that amplitude compares timer and is made up of following part:
A) 2n comparer (11), 11 are arranged
1... 11
m... 11
nAnd 11
1' ... 11
m' ... 11
n', each comparer has two input ends, an input termination analog driver, and another input termination reference voltage generator, output termination differentiating circuit, simulating signal is compared with reference voltage through comparer (11), output high level and low level;
B) connect a differentiating circuit (12) behind each comparer (11), 2n altogether, the comparer output waveform gets rising edge pulse and negative edge pulse through differential, and the output of differentiating circuit connects chronotron (13) and pulse sequence inversor (3);
C) 2n chronotron (13) arranged, connect a chronotron behind each differentiating circuit (12), rising edge pulse that differential obtains and negative edge pulse obtain a series of pulses with certain time-delay through chronotron, and the output of chronotron (13) connects the respective input of drive-pulse generator (2).
6, the interface circuit between said analog driver of claim 3 and the power amplifier is characterized in that amplitude compares timer and is made up of following part:
A) 2n comparer (11), 11 are arranged
1... 11
m... 11
nAnd 11
1' ... 11
m' ... 11
n', each comparer has two input ends, and one connects analog driver, and another connects reference voltage generator, output termination differentiating circuit, simulating signal is compared with reference voltage through comparer (11), output high level and low level;
B) connect a differentiating circuit (12) behind each comparer (11), 2n altogether, the comparer output waveform gets rising edge pulse and negative edge pulse through differential, and the output of differentiating circuit connects chronotron (13);
C) 4n chronotron (13) arranged, connect 2 chronotrons behind each differentiating circuit (12), the output of chronotron connects drive-pulse generator, connects the respective input of drive-pulse generator (2) respectively without the pulse of time-delay with through the pulse of time-delay.
7, interface circuit between claim 2 or 5 said analog drivers and the power amplifier, it is characterized in that pulse sequence inversor (3) is by phase inverter (31), mixer (32), counter (33), code translator (34), differentiating circuit (35) and chronotron (36) are formed, phase inverter (31) has 2n input port to join with the corresponding port of amplitude comparison timer (1) respectively, phase inverter (31) has 2n output port to connect mixer (32), the output of mixer (32) connects counter (33), and the reseting port of counter (33) meets relatively first square wave unbalanced pulse t of timer of amplitude
11Or t
31Output terminal, the output of counter connects code translator (34), each output port of code translator all connects a differentiating circuit (35), the output of differentiating circuit (35) divides two-way, one the tunnel connects chronotron (36), another road is the pulse output end mouth of the time-delay τ microsecond of pulse sequence inversor, the output of chronotron (36) is as the pulse output end mouth of time-delay τ+0.2 microsecond of pulse sequence inversor, and delay pulse output port and delay pulse output port not connect the respective input of drive-pulse generator (2) respectively.
8, the interface circuit between said analog driver of claim 4 and the power amplifier is characterized in that digital signal processor (5) is made up of following part:
A) input interface (21), the data port of its input data port and A/D converter is by data bus DB
1Link to each other, control port passes through CB
1Link to each other with the control port of A/D converter, data-out port by data bus with computing machine (22) but link to each other with the parallel interface sheet (23) of step-by-step set/reset;
B) computing machine (22), its data port, address mouth and control mouth respectively by data bus DB, address bus AB and control bus CB with input interface (21) but link to each other with the parallel interface sheet (23) of step-by-step set/reset;
C) but the parallel interface sheet (23) of one group of step-by-step set/reset, its output terminals A
1, B
1, C
1, D
1, A
2, B
2, C
2, D
2... A
n, B
n, C
n, D
nControl with A, the B of n direct current-square-wave inverter, C, D brachium pontis extremely links to each other respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94105897A CN1048601C (en) | 1994-06-02 | 1994-06-02 | Signal processing method between analog driver and power amplifier and interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94105897A CN1048601C (en) | 1994-06-02 | 1994-06-02 | Signal processing method between analog driver and power amplifier and interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1106145A true CN1106145A (en) | 1995-08-02 |
| CN1048601C CN1048601C (en) | 2000-01-19 |
Family
ID=5032243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN94105897A Expired - Lifetime CN1048601C (en) | 1994-06-02 | 1994-06-02 | Signal processing method between analog driver and power amplifier and interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1048601C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916143A (en) * | 2013-01-05 | 2014-07-09 | 北京北广科技股份有限公司 | Non-equal-altitude step wave signal processing method and device for very-low-frequency long-wave transmitter |
| CN103916144A (en) * | 2013-01-05 | 2014-07-09 | 北京北广科技股份有限公司 | Self-adaptive correction method and device for power amplifier units of very-low-frequency long-wave transmitter |
-
1994
- 1994-06-02 CN CN94105897A patent/CN1048601C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916143A (en) * | 2013-01-05 | 2014-07-09 | 北京北广科技股份有限公司 | Non-equal-altitude step wave signal processing method and device for very-low-frequency long-wave transmitter |
| CN103916144A (en) * | 2013-01-05 | 2014-07-09 | 北京北广科技股份有限公司 | Self-adaptive correction method and device for power amplifier units of very-low-frequency long-wave transmitter |
| CN103916143B (en) * | 2013-01-05 | 2016-03-23 | 北京北广科技股份有限公司 | The non-contour step signal processing method of very low frequency long-wave transmitter and device |
| CN103916144B (en) * | 2013-01-05 | 2016-09-28 | 北京北广科技股份有限公司 | Very low frequency long-wave transmitter power amplifier unit self-adapting correction method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1048601C (en) | 2000-01-19 |
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