SU1599958A1 - Method of converting d.c.voltage to variable low-frequency quasi-sine voltage - Google Patents

Abstract

The invention relates to electrical engineering and can be used in secondary power supply and electric drive systems. The purpose of the invention is to increase efficiency. The converter that implements the proposed method contains an even number of inverter cells, the outputs of which are connected in series and connected to the input of the demodulator. The demodulator is made according to a bridge circuit on alternating current keys 5 - 8. The output of the demodulator is connected to the output pins of the converter. The keys of the inverter cells are controlled by the low-frequency voltage F, modulated by the modulating signal of the intermediate frequency F, which is 3 PL / 2 times higher than the frequency F, where L is the number of inverter cells, P is any integer number. The control demodulation signal supplied to the AC key control circuit also has a frequency F. With respect to this signal, the intermediate frequency modulating signals are shifted by an angle of + α / 2 and -α / 2, which determines zero pauses in the output voltage of the converter. Due to this shift, the switching of the AC keys occurs without voltage. 2 hp ff, 3 ill.

Description

The invention relates to electrical engineering and can be used in. secondary power systems. and electric drive. .

The purpose of the invention is to increase the efficiency of the device that implements the proposed method.

FIG. 1 shows timing diagrams illustrating the proposed: conversion method at. FIG. 2a, b is a block diagram of a variant of the power section of the device implementing the proposed method, and: a block diagram of the control system of the device; in fig. 3 - time diagrams illustrating the operation of the device implementing the method.

Consider the essence of the method on the example of L 2 (figure 1). The constant voltage is transformed into L successively shifted between them according to Aaz

at 1-variable angle

low frequency F (Vf, v /). L number

SP

co

00

set to even. Next, a control demodulating signal of the square wave type, of intermediate frequency, denoted n Lig, is formed. 1, Kak Vl "and two-analogous in shape with the phase shift My of the modulating signal of the frequency f (Vf ,,) symmetrically opposite to each other. Then modulate the low-frequency nag. yarn by modulating signals of frequency f, with each pair of low-frequency voltage shifted by an angle of 1f73, the positive half-waves of one voltage and the negative half-waves of the other voltage modulate the first modulating signal of the frequency f (p), and the negative half-waves of one and positive the other is modulated with the second modulating signal of the frequency f (y /.). After this, the transformed modulated voltages obtained (Uf Uj-) are transformed, followed by the summation of all the voltages. Then, the resulting resultant voltage (Uy.) Is demodulated using the demodulating signal Vf. The multiplicity of the hR is that -3L, where P is an even number

(the minimum value of the coefficient determines the minimum possible frequency of the intermediate high-frequency conversion, the period of which

2. equals

, T of elimination of double volt-square areas, phasing of different-frequency signals (p and 4. .Tf produced, based on the condition of changing the polarity of low-frequency voltages at the time corresponding to a quarter of the period of the demodulating signal (f (Fig. 3) In this case, the coefficient P is chosen by any integer (the minimum value of the coefficient

determines mi1: the possible frequency of the intermediate high-hour-, dot-conversion, half-period

2fr which is equal to).

Output value regulation5. low-frequency voltage is implemented by changing the phase shift between two modulating signals of frequency f (V / P.

One of the possible options for the practical implementation of the proposed

0

five

five

0

five

0

five

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five

The method may include a converter, the power part and control system of which is shown in FIG. 2a, b.

The converter contains an inverter unit 1 (NB, FIG. 2a), containing L identical inverter cells (RL1 - RLF) with a transformer output, made according to the zero-point power supply circuit. The secondary windings of the inverter cell transformers are connected in series to form the summation circuit of the output voltages of the inverter cells connected to the input pins 2 and 3 of demodulator 4. Demodulator 4 can be performed, for example, using a bridge circuit on fully controlled AC 5-8 keys . Lines 9 and 10 form the output of the converter.

The device control system (Fig. 26) contains a master oscillator 11, an output connected to the input of a pulse width modulator 12 (MUH), an input to the first divider 13 dividing the frequency of the master oscillator by P, and on the falling edge of the input signal and the information input D-flip-flop a 14, which divides the frequency of the master oscillator into two (the inverter output of the flip-flop is connected to information input D), and on the leading edge of the input signal (Vjp) The output of the divider 13 is connected to the information input of the shift register 15 and to the input of the divider 16 with a division factor of 3L. The output of the divider 16 is connected to. the counting input of the register 15 shift. You., One modulator 12 pulse width is connected to the information inputs of two D- and 1K-type flip-flops 17 and 18, respectively, dividing the output signal of the pulse-width modulator (vper Fig. 3) into two (respectively on the front - D- trigger and rear trigger - 1K-trigger fronts). The output signals of the flip-flops 17 and 18 (ff, and, ip, respectively), the shift register 15 (- (p, fig. 26) are fed to the input of the logical node 19 implementing the logical expressions:

V, - p; "F f, VPi 4 c /. where is L / 2

fpj. cpFj -Vf,

Where

Vj

Vy

The output signals of the logical node 19 (Vf, V, - Vp Vj, Fig. 26) are input | a block of 20 decoupling and amplification of 20, consisting of L identical amplifying and decoupling nodes УРУ1 - УРУ1. (Fig. 26). The output signals (v, ..... (t, ((}, fig. 26) of block 20 are fed to the corresponding keys of the corresponding inverter cells (HL1-HIN) of the inverter block 1 (Fig. 26).

The output signals of the D-flip-flop 14 are fed to the input of the amplifier-decoupling node 21, the output signals of which are supplied to the corresponding keys 5–8 of the alternating current of the modulator 4 ((| keys 5 and 8, to the key) chi 6 and 7).

Amplification and expansion units 21 and block 20 (URU1-URU) can be performed, for example, according to one of the inverter cell circuits with a transformer output, which allows easy replication of the required number of control signals.

The pulse modulator 12 (M M) contains a generator of triangular pulses of symmetrical shape (11 pc. Fig. 3) and a comparator, on one input of which a voltage of 11 t is applied to the second variable (within the maximum and minimum voltage values ff) this voltage.

Consider the work of the converter. FIG. 3 shows the algorithm for generating the output controlled voltage of the device, the primary modulation part of which is based on two inverter cells — with a zero power point, and the frequency of the intermediate high-frequency conversion j

f | 3LF 6F (,).

The constant voltage (And, Fig. 2a) is converted into two phases shifted between the coPIT by an angle (at,

: tr / 3) equal low voltage voltages F. Then these voltages are modulated with intermediate frequency high frequency signals (V /. b, with each low voltage voltage shifted between them by an angle F / 3. Positive half-waves one voltage (“t с) and negative half-waves of the other (vlJ voltage modulate with a signal, and negative half-wave f 1: HU

 GO (at Fa) is modulated by the Y signal.

Then, the resulting modulated stresses () - are transformed and summed all L stresses. The resulting voltage (U) is fed to the input of the demodulator 4 (Vigor 2 and 3). Sequence phasing

high frequency signals

ten

20

25

thirty

-; {

relatively low-frequency voltages are produced based on the polarity of the low-frequency voltages at the time corresponding to a quarter of the period of the Vr signal

The necessary control algorithm for the key elements of the inverter cells (IN1-ISH., Fig. 2a) of the inverter unit 1 and the demodulator 4 is provided by the control system shown in FIG. 26

The master oscillator 11 generates, at its output, rectangular pulses with a duty cycle of two (“f ar Fig. 3), followed by a wave with a frequency f g 2f.

In the example shown in FIG. 3 examples fj.r.12F ((). These pulses are fed to the input of the modulator 12 of the pulse width (), the input of the divider 13 and the D-flip-flop 14. The pulse width of the pulse modulator 12 consists of a triangular voltage generator of symmetrical form and a comparator. At the inputs of the comparator, the output voltage and the variable (within the maximum and minimum voltage values and the ") voltage level (Up) are applied. From the output of the modulator of the pulse width, a signal is obtained that has a frequency of the master oscillator with a controlled duty cycle ((p, V.per ° th is fed to the information; the ionic inputs of D- and 1K-type flip-flops (respectively 17 and 18). D-flip-flop 17 divides the frequency of the input signal (j; p into two (the inverse output of the trigger is connected 45 to its information input D) on its leading edge, and IK (18) on the rear. The output signals of the trigger 17 and 18 have an intermediate high-frequency conversion frequency f WITH a duty cycle of two.

The initial setting (at start-up) of the triggers 14,17 and 18 and the counters of the dividers 13 and 16 using the drop and set (R, S) inputs is carried out in accordance with the time diagrams in fig. 3

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40

50

55

Vf, -, and negative uujiyBUJi- Q output of the divider 1 frequency of one CVI,) and positive square-shaped other pulses with a frequency (v sf are fed to the counting

9958

Then, the resulting modulated stresses () - are transformed and summed all L stresses. The resulting voltage (U) is fed to the input of the demodulator 4 (Vigor 2 and 3). Sequence phasing

high frequency signals

ten

20

25

thirty

-; {

relatively low-frequency voltages are produced by changing the polarity of the low-frequency voltages at the time corresponding to a quarter of the period of the Vr signal

The required control algorithm for the key elements of the inverter cells (IN1-IC., Fig. 2a) of the inverter unit 1 and demodulator 4 is provided with the control system shown in FIG. 26

The master oscillator 11 generates, at its output, rectangular pulses with a duty cycle of two (“f ar Fig. 3), the next wave with a frequency f g 2f.

In the example shown in FIG. 3 examples fj.r.12F ((). These pulses are fed to the input of the modulator 12 of the pulse width (), the input of the divider 13 and the D-flip-flop 14. The pulse width of the pulse modulator 12 consists of a generator of a triangular voltage of a symmetrical shape and a comparator. At the inputs of the comparator, the output voltage and the variable (within the maximum and minimum voltage values and the „) voltage level (Up) are applied. From the output of the modulator of the pulse width, a signal is received that has a frequency of the master oscillator with an adjustable duty cycle ((p, V.per ° that serves on the information; ionic inputs of D- and 1K-type triggers (respectively 17 and 18). D-trigger 17 divides the input signal frequency (j; p for two (the inverse output of the trigger is connected 45 to its information input D) on its leading edge, and IK (18) on the rear. The output signals of the trigger 17 and 18 have an intermediate high-frequency conversion frequency f CO. two.

The initial installation (at start-up) of the triggers 14,17 and 18 and the counters of the dividers 13 and 16 using the reset and installation inputs (R, S) are carried out in accordance with the time diagrams in FIG. 3

35

40

50

55

shift register 15 and to the input of frequency divider 16 with division factor 6. Vcodal pulses of frequency divider 16 with frequency F and with a duty cycle of two arrive at the information input of shift register 15, at the outputs of which the formation of sequences of pulses with frequency (VF J tfp ... ) shifted relative to each other by the interval 1 / 6F (Vp

VF).,.

The input signals of the trigger 17 and 18 («« ,, f, t ft f 4) as well as the shift register 1 (VF, ... Vp,) are fed to the input. logical node 19 that implements logical expressions i

V, VF, -Vf,, - Vf V

Vf / cJ F -Vf,

Vi

The output signals of the logic node 19 through the amplifier-breaking units of the block 20 are fed to the corresponding keys of the inverter cells (IL1, IL2 of the inverter unit 1. The D-trigger 14 divides the pulses of the master oscillator 11 into two (the inverse output of the trigger is associated with its information). Anterior input D) on the leading edge. The output rectangular pulses of the trigger 14 ((p, Vf) with the frequency of the intermediate high-frequency conversion and a duty cycle of two through the amplifying-breaker node 21 are fed to the corresponding AC switches d modulator 4 (switches 5 and 8 - 6 and 7).

The adjustment of the output voltage of the converter is made by varying. a phase shift between two signals of intermediate high frequency (, F /) due to a change in the duty cycle of the output pulses of the pulse width modulator 12 (frig).

FIG. 3 shows the algorithm for generating the output voltage (114) of the converter with two values of the duty cycle per С Vper t per

To ensure the reliability of the flip-flops 17 and 18, a pulse limiter can be inserted into the device control system that can be switched between the pulse width modulator output 12 and the trigger trigger input 17 and 18. The pulse limiter prevents the pulse width modulator output from going to the boundary points logical 1 and Oh, i.e.

with

five ;

0

25 ZO

0 45

gs

eliminates the possibility of stalling. signals of intermediate high-frequency conversion ((f l

The proposed structural-algorithmic organization of the converter allows switching demodulator transistors at zero voltage, which significantly improves their operation mode, eliminating dynamic losses (see Fig. 3) in the keys, i.e. increases efficiency.

Claims (2)

1. A method of converting a direct voltage into an adjustable low-frequency quasi-sinusoidal voltage at which a constant voltage transform into L low-frequency alternating voltage F, mutually shifted by the angle I, modulate these voltages with the modulating signal of intermediate frequency f, an integer number of times K exceeding the frequency F, sum the modulated voltages and deduct the resulting voltage. using a control demodulator signal of intermediate frequency f, and adjust the value of the output voltage obtained by introducing a zero pause width d at each half-period of intermediate frequency f, characterized in that the efficiency of the device that implements this method choose the number JL even, 2F / 3L and K 3PL / 2, and the modulation is performed using two modulating signals of intermediate frequency f, the first of which is shifted by the angle W / 2, and the second by the angle -oil2 relative to the control, demodulating signal between internal frequency f, wherein in each pair of variable voltage low frequency F, the shifted between themselves an angle "R / W, the first half of the first and second half of said second voltage modulated with a first modulating an intermediate frequency signal as well. The second half-cycle of the first voltage and the first half-cycle of the second voltage are modulated by the second modulating signal of the intermediate frequency f. 2. A method according to claim 1, characterized in that the control demodulation signal of the intermediate frequency -f is phased on one of the fronts of the alternating voltage low often / ree g-I j-u-nLf-n g-1 g-1 f-11-1 g /; F / 2 P 51 and dg 1 P P pn U u u u PG ppp one S Uuu . reg H /, 1GIUSH1PGTs pn (t (jjt (jJi Uuuu (jJi b) i Uuuu figure 1 FIG. 26