GB1325193A - Signal generators - Google Patents

Abstract

1325193 Digital signal generator POST OFFICE 16 Aug 1971 [18 May 1970] 23863/70 Heading G4H A digital signal generator used for testing P.C.M. systems produces a series of binary numbers representing successive amplitudes of a sine or cosine wave of a selected frequency and amplitude via a successive adjustment of a piece-wise linear approximation, and employs a counter 7 and logic means operating on the output of the counter to produce, when the counter is driven at a steady rate by a clock source and controller 6, 8, a sequence of binary numbers representing equispaced points of a waveform consisting of at least two straight line sections formed end to end, the n<SP>th</SP> section having a slope 1 # n # p and wherein the n<SP>th</SP> section occurs for a time 1 # n # p-1, the p<SP>th</SP> section occurring for a time #, T being constants. The counter 7, Fig. 3, not shown, comprises a chain of bi-stable devices interconnected by monostable devices such that when a first bi-stable of the chain is driven by the clock source the n<SP>th</SP> stage will be set or reset at twice the rate of the (n + 1)th stage, thus the counter is adapted to be advanced from zero to a maximum and reset itself to zero. At this point a logic circuit including a further bi-stable selects the complement of the output and the counter counts steadily back to zero. A further bi-stable indicates the sign of the count and hence a triangular waveform is generated in the form of the sequence of binary numbers. The output of the counter 7 is modified at 9 by a logic circuit comprising a combination of AND, OR gates, interconnections of counter output bit channels with other preceding outputs, and inverters, and a sequence of binary numbers of the properties defined above is produced. This sequence is further modified by a logic circuit 10 and the final sequence represents a sine wave to the accuracy required. Each binary number in the sequence is then multiplied by a factor e.g. 1À5 at 13 which circuit comprises a plurality of shift registers used as binary dividers which may be selectively switched into the circuit and their outputs added to the original number to produce the multiplication. The 11 digit sequence is then compressed to a 7 digit output and converted to a series at 11 and read-out at 14 under suitable clock control 129, 130. A plurality of the bi-stable stages of the counter 7 may be selectively driven by the control 8 and this renders adjustable the frequency of the output sine wave and hence frequency modulation may be employed. Amplitude modulation may be employed by varying the multiplication factor at 13.