CN110610870A - Flip-chip method - Google Patents
Flip-chip method Download PDFInfo
- Publication number
- CN110610870A CN110610870A CN201810613773.5A CN201810613773A CN110610870A CN 110610870 A CN110610870 A CN 110610870A CN 201810613773 A CN201810613773 A CN 201810613773A CN 110610870 A CN110610870 A CN 110610870A
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- China
- Prior art keywords
- solder
- layer
- conductive connection
- column
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 229910000679 solder Inorganic materials 0.000 claims abstract description 114
- 230000004888 barrier function Effects 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000005476 soldering Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 47
- 230000008569 process Effects 0.000 claims description 29
- 230000001680 brushing effect Effects 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81051—Forming additional members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A flip-chip method comprising: providing a semiconductor chip and a conductive connection post having opposing first and second faces; fixing the conductive connecting column on the surface of the semiconductor chip, wherein the first surface faces the semiconductor chip; forming a first barrier layer on the side wall of the conductive connection column, wherein the second surface of the conductive connection column is exposed out of the first barrier layer; providing a carrier plate, wherein the surface of the carrier plate is provided with a solder column; after forming the first barrier layer, contacting the solder post with the second face, the conductive connection post being on the solder post; and after the solder column is contacted with the second surface, reflow soldering is carried out, and the solder column forms a solder layer. The method prevents the solder layer from being attached to the side wall of the conductive connecting column and the quality of the solder layer from being reduced.
Description
Technical Field
The invention relates to the field of packaging, in particular to a flip-chip method.
Background
The flip chip technology is not only a chip interconnection technology, but also an ideal chip bonding technology. IBM (international business machines corporation) has developed this technology as early as over 50 years ago. But until recently, flip chips have become the packaging form of choice for high-end devices and high-density packaging. At present, the application range of the flip chip packaging technology is increasingly wide, the packaging form tends to be diversified, and the requirements for the flip chip are also improved.
However, in the conventional flip-chip method, the solder layer is easily attached to the sidewalls of the conductive connection posts, resulting in a reduced quality of the solder layer.
Disclosure of Invention
The problem to be solved by the present invention is to provide a flip-chip method that avoids the solder layer from adhering to the sidewalls of the conductive connection stud and avoids the quality of the solder layer from degrading.
In order to solve the above problems, the present invention provides a flip chip method, including: providing a semiconductor chip and a conductive connection post having opposing first and second faces; fixing the conductive connecting column on the surface of the semiconductor chip, wherein the first surface faces the semiconductor chip; forming a first barrier layer on the side wall of the conductive connection column, wherein the second surface of the conductive connection column is exposed out of the first barrier layer; providing a carrier plate, wherein the surface of the carrier plate is provided with a solder column; after forming the first barrier layer, contacting the solder post with the second face, the conductive connection post being on the solder post; and after the solder column is contacted with the second surface, reflow soldering is carried out, and the solder column forms a solder layer.
Optionally, the method for forming the first barrier layer includes: forming a barrier material layer on the second face and the sidewall of the conductive connection column; and removing the barrier material layer on the second surface to form the first barrier layer.
Optionally, the method for removing the barrier material layer on the second surface is a polishing process.
Optionally, the first barrier layer is made of insulating glue; the method for forming the barrier material layer is a glue brushing process.
Optionally, a process of forming the barrier material layer is an oxidation process.
Optionally, the thickness of the first barrier layer is 10 micrometers to 30 micrometers.
Optionally, the number of the conductive connection posts is several, the number of the solder posts is several, and after the solder posts are contacted with the second surface, one solder post is connected with only one conductive connection post; the method of forming the solder column includes: forming a screen plate on the surface of the carrier plate, wherein the screen plate is provided with a plurality of through holes, and the distance between the centers of the adjacent through holes is equal to the distance between the centers of the adjacent conductive connecting columns; respectively forming solder columns in the through holes by adopting a printing process; and removing the screen after the printing process is carried out.
Optionally, the radial dimension of the solder columns is smaller than the radial dimension of the conductive connection columns.
Optionally, the radial dimension of the solder column is 2/5-3/5 of the radial dimension of the conductive connection column.
Optionally, the method further includes: removing the first barrier layer after the reflow soldering is carried out; after the first barrier layer is removed, forming a plastic package layer on the carrier plate, the semiconductor chip, the conductive connecting column and the solder layer; or after the reflow soldering is carried out, a plastic package layer is formed on the carrier plate, the semiconductor chip, the conductive connecting column and the solder layer, and the first barrier layer is covered by the plastic package layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the flip-chip method provided by the technical scheme of the invention, the first barrier layer is formed on the side wall of the conductive connection column before the solder column is contacted with the second surface, and the first barrier layer exposes out of the second surface of the conductive connection column, so that the first barrier layer can prevent the material of the solder column from flowing upwards along the side wall of the conductive connection column in the reflow soldering process. Thus, the solder layer is prevented from being attached to the side wall of the conductive connecting column, and the quality of the solder layer is prevented from being reduced.
Furthermore, the material of the first barrier layer is insulating glue, the difference between the material type of the first barrier layer and the material type of the solder column is large, the first barrier layer can effectively prevent the material of the solder column from flowing upwards along the side wall of the conductive connecting column in the reflow soldering process, and the quality of the solder layer is effectively prevented from being reduced.
Drawings
Fig. 1 to 2 are schematic structural views of a flip-chip method;
fig. 3 to 12 are schematic structural diagrams of a flip-chip method according to an embodiment of the invention.
Detailed Description
As described in the background, the flip-chip method of the prior art formation results in a reduced quality solder layer.
Fig. 1 to 2 are schematic structural views of a flip-chip method.
Referring to fig. 1, a semiconductor chip 100, a conductive connection post 110 and a carrier board 130 are provided, the conductive connection post 110 having opposite first and second faces; fixing the conductive connection column 110 on the surface of the semiconductor chip 100, with the first surface facing the semiconductor chip 100; solder balls 140 are fixedly disposed on the second surface of the conductive connection posts 110; then, the semiconductor chip 100, the conductive connection posts 110 and the solder balls 140 are placed on the surface of the carrier plate 130, and the solder balls 140 are in contact with the surface of the carrier plate 130.
Referring to fig. 2, after the semiconductor chip 100, the conductive connection post 110 and the solder ball 140 are placed on the surface of the carrier 130, reflow soldering is performed to form a solder layer 141 on the solder ball 140.
During the reflow process, the material of the solder balls 140 melts into a liquid. Since the materials of the solder ball 140 and the conductive connection column 110 are both metals, the material type of the solder ball 140 is the same as that of the conductive connection column 110, and the material of the solder ball 140 is easily attached to the surface of the material of the conductive connection column 110, during the reflow soldering process, the material of the solder ball 140 easily flows upwards along the sidewall of the conductive connection column 110, which results in the loss of the material of the solder layer 141, the formation of voids in the solder layer 141 is easy, and the quality of the solder layer 141 is reduced.
On the basis, the invention provides a flip-chip method, which comprises the following steps: forming a first barrier layer on the side wall of the conductive connecting column, wherein the second surface of the conductive connecting column is exposed out of the first barrier layer; after the first barrier layer is formed, the solder column is contacted with the second surface of the conductive connecting column, and the conductive connecting column is positioned on the solder column; thereafter, reflow is performed, and the solder column is formed into a solder layer. The method prevents the solder layer from being attached to the side wall of the conductive connecting column and the quality of the solder layer from being reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 12 are schematic structural diagrams of a flip-chip method according to an embodiment of the invention.
Referring to fig. 3, a semiconductor chip 200 and a conductive connection stud 210 are provided, the conductive connection stud 210 having opposing first and second faces 210a, 210 b; the conductive connection post 210 is fixed to the surface of the semiconductor chip 200 with the first surface 210a facing the semiconductor chip 200.
In this embodiment, the number of the conductive connection posts 210 is several. In other embodiments, the number of conductive connection posts is one.
In this embodiment, the first surface 210a and the second surface 210b are parallel to the surface of the semiconductor chip 200, and the sidewalls of the conductive connection pillar 210 are perpendicular to the surface of the semiconductor chip 200.
The conductive connection post 210 is made of metal, for example, the conductive connection post 210 is a copper post.
The function of the conductive connection post 210 includes: for electrically connecting the semiconductor chip 200 and the subsequent carrier board 300.
Next, a first barrier layer is formed on the sidewalls of the conductive connection pillar 210, and the first barrier layer exposes the second surface 210b of the conductive connection pillar 210.
Referring to fig. 4, a barrier material layer 220 is formed on the second face 210b and sidewalls of the conductive connection stud 210.
In this embodiment, the material of the blocking material layer 220 is an insulating adhesive, and the method for forming the blocking material layer 220 is a glue brushing process.
In this embodiment, since the barrier material layer 220 is formed on both the second surface 210b and the sidewall of the conductive connection pillar 210, the brushing position is not strictly controlled in the brushing process, so that the difficulty of the process for forming the barrier material layer 220 is reduced.
In other embodiments, the material of the barrier material layer 220 is a metal oxide, and the process of forming the barrier material layer 220 is an oxidation process, including dry oxidation or wet oxidation. For example, when the conductive connection pillar 210 is a copper pillar, the material of the barrier material layer 220 is copper oxide.
Referring to fig. 5, the blocking material layer 220 on the second surface 210b is removed, and a first blocking layer 221 is formed on the sidewall of the conductive connection pillar 210.
In this embodiment, the method of removing the barrier material layer 220 on the second surface 210b is a polishing process.
The role of the first barrier layer 221 includes: during subsequent reflow, the material of the solder columns is prevented from flowing up the sidewalls of the conductive connection columns 210.
In this embodiment, the material of the first blocking layer 221 is an insulating glue, the difference between the material type of the first blocking layer 221 and the material type of the subsequent solder column is relatively large, and the first blocking layer 221 can effectively prevent the material of the solder column from flowing upwards along the sidewall of the conductive connection column in the subsequent reflow process, thereby effectively avoiding the quality reduction of the solder layer. Moreover, since the material type of the first barrier layer 221 is different from that of the subsequent solder pillar, the material of the solder pillar does not flow upward along the sidewall of the first barrier layer 221.
In other embodiments, the material of the first barrier layer is a metal oxide.
In one embodiment, the first barrier layer 221 has a thickness of 10 microns to 30 microns, such as 10 microns, 15 microns, 20 microns, or 30 microns. The thickness of the first barrier layer 221 is selected in the sense that: if the thickness of the first blocking layer 221 is greater than 30 micrometers, process waste is caused, and secondly, if the thickness of the first blocking layer 221 is too large, the space between the subsequent adjacent conductive connection pillars 210 is too small, and a plastic encapsulation layer is difficult to fill between the adjacent conductive connection pillars 210; if the thickness of the first barrier layer 221 is less than 10 microns, this results in a reduced ability of the first barrier layer 221 to block the flow of solder pillar material up the sidewalls of the conductive connection pillar 210.
It should be noted that in other embodiments, the first barrier layer is directly formed on the sidewall of the conductive connection pillar by using a glue brushing process, in which case, the position of the glue brushing needs to be strictly controlled to avoid brushing the material of the first barrier layer on the second surface of the conductive connection pillar.
Referring to fig. 8, a carrier 300 is provided, and a surface of the carrier 300 has solder columns 320.
The number of the solder columns 320 is several. The number of the solder columns 320 is equal to the number of the conductive connection columns 210. In other embodiments, the number of solder columns is one.
After subsequent contact of the solder columns 320 with the second face 210b, one solder column 320 is connected to only one conductive connection column 210.
In this embodiment, the carrier 300 is exemplified by a substrate (substrate), for example, a PCB board or a BT board.
In other embodiments, the carrier is a lead frame (lead frame).
The solder column 320 is made of tin, tin-silver alloy, tin-silver-copper alloy or tin-lead alloy.
The method of forming the solder columns 320 includes: referring to fig. 6, a mesh plate 310 is formed on the surface of the carrier 300, the mesh plate 310 has a plurality of through holes therein, and the distance between the centers of adjacent through holes is equal to the distance between the centers of adjacent conductive connection posts 210; referring to fig. 7, solder columns 320 are respectively formed in the through-holes using a printing process; referring to fig. 8, after the printing process is performed, the screen 310 is removed.
The benefits of forming the solder columns 320 by the printing process described above include: the shape and the size of the plurality of solder columns 320 are more consistent, and the pitch of the plurality of solder columns 320 can be smaller.
In the subsequent reflow process, the solder columns 320 are melted, the height of the solder layer 321 is reduced compared with the height of the solder columns 320, and the radial dimension of the solder layer 321 is likely to become larger. In this embodiment, the radial dimension of the solder column 320 is designed to be smaller than the radial dimension of the conductive connection column 210, so that the radial dimension of the solder layer 321 is prevented from being too large, the risk of connection between adjacent solder layers 321 is reduced, the use of solder materials is reduced, and the process cost is reduced.
In one embodiment, the radial dimension of the solder post 320 is 2/5-3/5, such as 1/2, of the radial dimension of the conductive connection post 210.
Referring to fig. 9, after the first barrier layer 221 is formed, the solder post 320 is brought into contact with the second side 210b, and the conductive connection post 210 is positioned on the solder post 320.
The center of the conductive connection post 210 is aligned with the center of the solder post 320.
The conductive connection post 210 on the solder post 320 functions to: the molten material of the solder columns 320 is prevented from flowing toward the semiconductor chip 200 by gravity during the subsequent reflow process.
Referring to fig. 10, after the solder pillar 320 is contacted with the second surface 210b, reflow is performed, and the solder pillar 320 is formed into a solder layer 321.
In one embodiment, when the height of the solder pillar 320 is 20 micrometers to 100 micrometers, the height of the solder layer 321 is 5 micrometers to 30 micrometers.
In this embodiment, the solder layer 321 includes a solder top surface in contact with the second surface; the radial dimension of the solder top surface is less than or equal to the total radial dimension of the first barrier layer 221 and the conductive connection stud 210.
The total radial dimension of the first barrier layer 221 and the conductive connection stud 210 is equal to the radial dimension of the conductive connection stud 210 plus 2 times the thickness of the first barrier layer 221.
Referring to fig. 11, after the reflow soldering is performed, a molding layer 330 is formed on the carrier 300, the semiconductor chip 200, the conductive connection post 210 and the solder layer 321, and the molding layer 330 covers the first barrier layer 221.
In other embodiments, the first barrier layer is removed after the reflow soldering is performed; and after the first barrier layer is removed, forming a plastic package layer on the carrier plate, the semiconductor chip, the conductive connecting column and the solder layer.
In this embodiment, the carrier 300 is a substrate (substrate), and balls are further mounted on a surface of the carrier 300 opposite to the semiconductor chip 200, and solder balls 322 are formed on a surface of the carrier 300 opposite to the semiconductor chip 200 (see fig. 11).
In other embodiments, referring to fig. 12, when the carrier 301 is a lead frame (lead frame), it is not necessary to perform ball-planting on the surface of the carrier 301 facing away from the semiconductor chip 200.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of flipping, comprising:
providing a semiconductor chip and a conductive connection post having opposing first and second faces;
fixing the conductive connecting column on the surface of the semiconductor chip, wherein the first surface faces the semiconductor chip;
forming a first barrier layer on the side wall of the conductive connection column, wherein the second surface of the conductive connection column is exposed out of the first barrier layer;
providing a carrier plate, wherein the surface of the carrier plate is provided with a solder column;
after forming the first barrier layer, contacting the solder post with the second face, the conductive connection post being on the solder post;
and after the solder column is contacted with the second surface, reflow soldering is carried out, and the solder column forms a solder layer.
2. The flip-chip method of claim 1, wherein the method of forming the first barrier layer comprises: forming a barrier material layer on the second face and the sidewall of the conductive connection column; and removing the barrier material layer on the second surface to form the first barrier layer.
3. The flip-chip method of claim 2 wherein the step of removing the barrier material layer from the second side is a grinding process.
4. The flip-chip method according to claim 2, wherein the material of the first barrier layer is an insulating paste; the method for forming the barrier material layer is a glue brushing process.
5. The flip-chip method of claim 2, wherein the process of forming the barrier material layer is an oxidation process.
6. The flip-chip method of claim 1 wherein the first barrier layer has a thickness of 10 to 30 microns.
7. The method of claim 1, wherein the number of conductive connection studs is several, the number of solder studs is several, and one solder stud is connected to only one conductive connection stud after the solder stud is contacted to the second side; the method of forming the solder column includes: forming a screen plate on the surface of the carrier plate, wherein the screen plate is provided with a plurality of through holes, and the distance between the centers of the adjacent through holes is equal to the distance between the centers of the adjacent conductive connecting columns; respectively forming solder columns in the through holes by adopting a printing process; and removing the screen after the printing process is carried out.
8. The method of flipping according to claim 1, wherein a radial dimension of the solder columns is less than a radial dimension of the conductive connection columns.
9. The flip-chip method of claim 8 wherein the radial dimension of the solder columns is 2/5-3/5 of the radial dimension of the conductive connection columns.
10. The flip-chip method of claim 1, further comprising: removing the first barrier layer after the reflow soldering is carried out; after the first barrier layer is removed, forming a plastic package layer on the carrier plate, the semiconductor chip, the conductive connecting column and the solder layer;
or after the reflow soldering is carried out, a plastic package layer is formed on the carrier plate, the semiconductor chip, the conductive connecting column and the solder layer, and the first barrier layer is covered by the plastic package layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810613773.5A CN110610870A (en) | 2018-06-14 | 2018-06-14 | Flip-chip method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810613773.5A CN110610870A (en) | 2018-06-14 | 2018-06-14 | Flip-chip method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110610870A true CN110610870A (en) | 2019-12-24 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810613773.5A Pending CN110610870A (en) | 2018-06-14 | 2018-06-14 | Flip-chip method |
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| CN (1) | CN110610870A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| JP2003234362A (en) * | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | Semiconductor device |
| CN103730380A (en) * | 2013-12-05 | 2014-04-16 | 南通富士通微电子股份有限公司 | Forming method of packaging structure |
| CN104392941A (en) * | 2014-10-31 | 2015-03-04 | 南通富士通微电子股份有限公司 | Method of forming flip-chip semiconductor encapsulation device |
| US20150364410A1 (en) * | 2014-06-17 | 2015-12-17 | Ngk Spark Plug Co., Ltd. | Circuit board, manufacturing method therefor, and pillar-shaped terminal for circuit board |
| CN207097810U (en) * | 2017-08-25 | 2018-03-13 | 恒劲科技股份有限公司 | Packaging system and its carrying board structure |
-
2018
- 2018-06-14 CN CN201810613773.5A patent/CN110610870A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| JP2003234362A (en) * | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | Semiconductor device |
| CN103730380A (en) * | 2013-12-05 | 2014-04-16 | 南通富士通微电子股份有限公司 | Forming method of packaging structure |
| US20150364410A1 (en) * | 2014-06-17 | 2015-12-17 | Ngk Spark Plug Co., Ltd. | Circuit board, manufacturing method therefor, and pillar-shaped terminal for circuit board |
| CN104392941A (en) * | 2014-10-31 | 2015-03-04 | 南通富士通微电子股份有限公司 | Method of forming flip-chip semiconductor encapsulation device |
| CN207097810U (en) * | 2017-08-25 | 2018-03-13 | 恒劲科技股份有限公司 | Packaging system and its carrying board structure |
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Application publication date: 20191224 |