CN110610914A - Packaging structure - Google Patents
Packaging structure Download PDFInfo
- Publication number
- CN110610914A CN110610914A CN201810613771.6A CN201810613771A CN110610914A CN 110610914 A CN110610914 A CN 110610914A CN 201810613771 A CN201810613771 A CN 201810613771A CN 110610914 A CN110610914 A CN 110610914A
- Authority
- CN
- China
- Prior art keywords
- solder
- conductive connection
- layer
- semiconductor chip
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A package structure, comprising: a semiconductor chip; the conductive connecting column is provided with a first surface and a second surface which are opposite, and the first surface of the conductive connecting column is fixed with the surface of the semiconductor chip; a first barrier layer on a sidewall of the conductive connection stud and not covering the second face; the carrier plate is arranged opposite to the semiconductor chip, the conductive connecting column is positioned between the semiconductor chip and the carrier plate, and the second surface faces the carrier plate; and the solder layer is positioned between the surface of the carrier plate and the second surface. The performance of the package structure is improved.
Description
Technical Field
The invention relates to the field of packaging, in particular to a packaging structure.
Background
The flip chip technology is not only a chip interconnection technology, but also an ideal chip bonding technology. IBM (international business machines corporation) has developed this technology as early as over 50 years ago. But until recently, flip chips have become the packaging form of choice for high-end devices and high-density packaging. At present, the application range of the flip chip packaging technology is increasingly wide, the packaging form tends to be diversified, and the requirements for the flip chip are also improved.
However, the performance of the package structure formed by the existing flip chip process is poor.
Disclosure of Invention
The invention provides a packaging structure to improve the performance of the packaging structure.
To solve the above problems, the present invention provides a package structure, including: a semiconductor chip; the conductive connecting column is provided with a first surface and a second surface which are opposite, and the first surface of the conductive connecting column is fixed with the surface of the semiconductor chip; a first barrier layer on a sidewall of the conductive connection stud and not covering the second face; the carrier plate is arranged opposite to the semiconductor chip, the conductive connecting column is positioned between the semiconductor chip and the carrier plate, and the second surface faces the carrier plate; and the solder layer is positioned between the surface of the carrier plate and the second surface.
Optionally, the material of the first barrier layer is insulating glue.
Optionally, the material of the first barrier layer is a metal oxide.
Optionally, the conductive connection column is a copper column; the material of the first barrier layer is copper oxide.
Optionally, the thickness of the first barrier layer is 10 micrometers to 30 micrometers.
Optionally, the number of the conductive connection columns is several, the number of the solder layers is several, and the number of the solder layers between one conductive connection column and the surface of the carrier plate is one.
Optionally, the height of the solder layer is 5 micrometers to 30 micrometers.
Optionally, the solder layer includes a solder top surface in contact with the second surface; the radial dimension of the solder top surface is less than or equal to the total radial dimension of the first barrier layer and the conductive connection post.
Optionally, the method further includes: and the plastic packaging layer is positioned on the surface of the carrier plate and covers the semiconductor chip, the conductive connecting column, the solder layer and the first barrier layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the packaging structure provided by the technical scheme of the invention comprises a first barrier layer, wherein the first barrier layer is positioned on the side wall of the conductive connecting column and does not cover the second surface, and a solder layer is positioned between the surface of the carrier plate and the second surface of the conductive connecting column. The first barrier layer has a protective effect on the conductive connection column and prevents the material of the solder layer from contacting the surface of the side wall of the conductive connection column. Because the position of the solder layer is limited by the first barrier layer, a cavity is not easy to form in the solder layer, and the quality of the solder layer is improved. In conclusion, the performance of the packaging structure is improved.
Drawings
Fig. 1 to 2 are schematic structural views of a flip-chip method;
fig. 3 to 12 are schematic structural diagrams of a flip-chip method according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the package structure formed by the existing flip chip process is poor.
Fig. 1 to 2 are schematic structural diagrams of a flip-chip method forming process.
Referring to fig. 1, a semiconductor chip 100, a conductive connection post 110 and a carrier board 130 are provided, the conductive connection post 110 having opposite first and second faces; fixing the conductive connection column 110 on the surface of the semiconductor chip 100, with the first surface facing the semiconductor chip 100; solder balls 140 are fixedly disposed on the second surface of the conductive connection posts 110; then, the semiconductor chip 100, the conductive connection posts 110 and the solder balls 140 are placed on the surface of the carrier plate 130, and the solder balls 140 are in contact with the surface of the carrier plate 130.
Referring to fig. 2, after the semiconductor chip 100, the conductive connection post 110 and the solder ball 140 are placed on the surface of the carrier 130, reflow soldering is performed to form a solder layer 141 on the solder ball 140.
During the reflow process, the material of the solder balls 140 melts into a liquid. Since the materials of the solder ball 140 and the conductive connection column 110 are both metals, the material type of the solder ball 140 is the same as that of the conductive connection column 110, and the material of the solder ball 140 is easily attached to the surface of the material of the conductive connection column 110, during the reflow soldering process, the material of the solder ball 140 easily flows upwards along the sidewall of the conductive connection column 110, which results in the loss of the material of the solder layer 141, the formation of voids in the solder layer 141 is easy, and the quality of the solder layer 141 is reduced.
On this basis, the present invention provides a package structure, comprising: a semiconductor chip; the conductive connecting column is provided with a first surface and a second surface which are opposite, and the first surface of the conductive connecting column is fixed with the surface of the semiconductor chip; a first barrier layer on a sidewall of the conductive connection stud and not covering the second face; the carrier plate is arranged opposite to the semiconductor chip, the conductive connecting column is positioned between the semiconductor chip and the carrier plate, and the second surface faces the carrier plate; and the solder layer is positioned between the surface of the carrier plate and the second surface. The performance of the package structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 12 are schematic structural diagrams illustrating a flip-chip method according to an embodiment of the invention.
Referring to fig. 3, a semiconductor chip 200 and a conductive connection stud 210 are provided, the conductive connection stud 210 having opposing first and second faces 210a, 210 b; the conductive connection post 210 is fixed to the surface of the semiconductor chip 200 with the first surface 210a facing the semiconductor chip 200.
In this embodiment, the number of the conductive connection posts 210 is several. In other embodiments, the number of conductive connection posts is one.
In this embodiment, the first surface 210a and the second surface 210b are parallel to the surface of the semiconductor chip 200, and the sidewalls of the conductive connection pillar 210 are perpendicular to the surface of the semiconductor chip 200.
The conductive connection post 210 is made of metal, for example, the conductive connection post 210 is a copper post.
The function of the conductive connection post 210 includes: for electrically connecting the semiconductor chip 200 and the subsequent carrier board 300.
Next, a first barrier layer is formed on the sidewalls of the conductive connection pillar 210, and the first barrier layer exposes the second surface 210b of the conductive connection pillar 210.
Referring to fig. 4, a barrier material layer 220 is formed on the second face 210b and sidewalls of the conductive connection stud 210.
In this embodiment, the material of the blocking material layer 220 is an insulating adhesive, and the method for forming the blocking material layer 220 is a glue brushing process.
In this embodiment, since the barrier material layer 220 is formed on both the second surface 210b and the sidewall of the conductive connection pillar 210, the brushing position is not strictly controlled in the brushing process, so that the difficulty of the process for forming the barrier material layer 220 is reduced.
In other embodiments, the material of the barrier material layer 220 is a metal oxide, and the process of forming the barrier material layer 220 is an oxidation process, including dry oxidation or wet oxidation. For example, when the conductive connection pillar 210 is a copper pillar, the material of the barrier material layer 220 is copper oxide.
Referring to fig. 5, the blocking material layer 220 on the second surface 210b is removed, and a first blocking layer 221 is formed on the sidewall of the conductive connection pillar 210.
In this embodiment, the method of removing the barrier material layer 220 on the second surface 210b is a polishing process.
The role of the first barrier layer 221 includes: during subsequent reflow, the material of the solder columns is prevented from flowing up the sidewalls of the conductive connection columns 210.
In this embodiment, the material of the first blocking layer 221 is an insulating glue, the difference between the material type of the first blocking layer 221 and the material type of the subsequent solder column is relatively large, and the first blocking layer 221 can effectively prevent the material of the solder column from flowing upwards along the sidewall of the conductive connection column in the subsequent reflow process, thereby effectively avoiding the quality reduction of the solder layer. Moreover, since the material type of the first barrier layer 221 is different from that of the subsequent solder pillar, the material of the solder pillar does not flow upward along the sidewall of the first barrier layer 221.
In other embodiments, the material of the first barrier layer is a metal oxide.
In one embodiment, the first barrier layer 221 has a thickness of 10 microns to 30 microns, such as 10 microns, 15 microns, 20 microns, or 30 microns. The thickness of the first barrier layer 221 is selected in the sense that: if the thickness of the first blocking layer 221 is greater than 30 micrometers, process waste is caused, and secondly, if the thickness of the first blocking layer 221 is too large, the space between the subsequent adjacent conductive connection pillars 210 is too small, and a plastic encapsulation layer is difficult to fill between the adjacent conductive connection pillars 210; if the thickness of the first barrier layer 221 is less than 10 microns, this results in a reduced ability of the first barrier layer 221 to block the flow of solder pillar material up the sidewalls of the conductive connection pillar 210.
It should be noted that in other embodiments, the first barrier layer is directly formed on the sidewall of the conductive connection pillar by using a glue brushing process, in which case, the position of the glue brushing needs to be strictly controlled to avoid brushing the material of the first barrier layer on the second surface of the conductive connection pillar.
Referring to fig. 8, a carrier 300 is provided, and a surface of the carrier 300 has solder columns 320.
The number of the solder columns 320 is several. The number of the solder columns 320 is equal to the number of the conductive connection columns 210. In other embodiments, the number of solder columns is one.
After subsequent contact of the solder columns 320 with the second face 210b, one solder column 320 is connected to only one conductive connection column 210.
In this embodiment, the carrier 300 is exemplified by a substrate (substrate), for example, a PCB board or a BT board.
In other embodiments, the carrier is a lead frame (lead frame).
The solder column 320 is made of tin, tin-silver alloy, tin-silver-copper alloy or tin-lead alloy.
The method of forming the solder columns 320 includes: referring to fig. 6, a mesh plate 310 is formed on the surface of the carrier 300, the mesh plate 310 has a plurality of through holes therein, and the distance between the centers of adjacent through holes is equal to the distance between the centers of adjacent conductive connection posts 210; referring to fig. 7, solder columns 320 are respectively formed in the through-holes using a printing process; referring to fig. 8, after the printing process is performed, the screen 310 is removed.
The benefits of forming the solder columns 320 by the printing process described above include: the shape and the size of the plurality of solder columns 320 are more consistent, and the pitch of the plurality of solder columns 320 can be smaller.
During the subsequent reflow process, the solder pillar 320 melts, the height of the solder layer 321 is reduced compared to the height of the solder pillar 320, and the radial dimension of the bottom of the solder layer 321 is larger than the radial dimension of the solder pillar 320. In this embodiment, the radial dimension of the solder column 320 is designed to be smaller than the radial dimension of the conductive connection column 210, so that the radial dimension of the solder layer 321 is prevented from being too large, the risk of connection between adjacent solder layers 321 is reduced, the use of solder materials is reduced, and the process cost is reduced.
In one embodiment, the radial dimension of the solder post 320 is 2/5-3/5, such as 1/2, of the radial dimension of the conductive connection post 210.
Referring to fig. 9, after the first barrier layer 221 is formed, the solder post 320 is brought into contact with the second side 210b, and the conductive connection post 210 is positioned on the solder post 320.
The center of the conductive connection post 210 is aligned with the center of the solder post 320.
The conductive connection post 210 on the solder post 320 functions to: the molten material of the solder columns 320 is prevented from flowing toward the semiconductor chip 200 by gravity during the subsequent reflow process.
Referring to fig. 10, after the solder pillar 320 is contacted with the second surface 210b, reflow is performed, and the solder pillar 320 is formed into a solder layer 321.
In one embodiment, when the height of the solder pillar 320 is 20 micrometers to 100 micrometers, the height of the solder layer 321 is 5 micrometers to 30 micrometers.
Referring to fig. 11, after the reflow soldering is performed, a molding layer 330 is formed on the carrier 300, the semiconductor chip 200, the conductive connection post 210 and the solder layer 321, and the molding layer 330 covers the first barrier layer 221.
In this embodiment, the carrier 300 is a substrate (substrate), and balls are further required to be mounted on a surface of the carrier 300 opposite to the semiconductor chip 200, and solder balls 322 are formed on a surface of the carrier 300 opposite to the semiconductor chip 200 (refer to fig. 11).
In other embodiments, referring to fig. 12, the carrier 301 is a lead frame (lead frame), and it is not necessary to perform ball-bonding on the surface of the carrier 301 opposite to the semiconductor chip 200.
Accordingly, the present embodiment further provides a package structure formed by the above method, referring to fig. 10, including: a semiconductor chip 200; a conductive connection post 210, said conductive connection post 210 having opposing first and second faces 210a (see fig. 3) and 210b (see fig. 3), said first face 210a of said conductive connection post 210 being affixed to the surface of the semiconductor chip 200; a first blocking layer 221, the first blocking layer 221 being located on a sidewall of the conductive connection pillar 210 and not covering the second face 210 b; a carrier 300, wherein the carrier 300 is disposed opposite to the semiconductor chip 200, the conductive connection column 210 is located between the semiconductor chip 200 and the carrier 300, and the second surface 210b faces the carrier 300; a solder layer 321 located between the surface of the carrier 300 and the second surface 210 b.
The first and second faces 210a and 210b are parallel to the surface of the semiconductor chip 200, and the sidewalls of the conductive connection post 210 are perpendicular to the surface of the semiconductor chip 200.
The conductive connection post 210 is made of metal, for example, the conductive connection post 210 is a copper post.
The function of the conductive connection post 210 includes: for electrically connecting the semiconductor chip 200 and the subsequent carrier board 300.
The role of the first barrier layer 221 includes: the first barrier layer 221 protects the sidewalls of the conductive connection stud 210, and the first barrier layer 221 blocks the material of the solder layer 321 from adhering to the sidewalls of the conductive connection stud 210.
In this embodiment, the material of the first blocking layer 221 is an insulating glue, the difference between the material type of the first blocking layer 221 and the material type of the solder layer is relatively large, and the first blocking layer 221 can effectively prevent the material of the solder layer 321 from being attached to the sidewall of the conductive connection pillar 210, thereby effectively preventing the quality of the solder layer 321 from being reduced. Moreover, since the material type of the first barrier layer 221 is different from the material type of the solder layer 321, the material of the solder layer 321 is not easily attached to the sidewall of the first barrier layer 221.
In other embodiments, the material of the first barrier layer is a metal oxide.
When the conductive connection pillar 210 is a copper pillar, the material of the first barrier layer 221 is copper oxide.
In this embodiment, the thickness of the first barrier layer is 10 microns to 30 microns, such as 10 microns, 15 microns, 20 microns, or 30 microns. The thickness of the first barrier layer 221 is selected in the sense that: if the thickness of the first blocking layer 221 is greater than 30 micrometers, process waste is caused, and secondly, if the thickness of the first blocking layer 221 is too large, the space between the subsequent adjacent conductive connection pillars 210 is too small, and a plastic encapsulation layer is difficult to fill between the adjacent conductive connection pillars 210; if the thickness of the first barrier layer 221 is less than 10 μm, the first barrier layer 221 may have a weak protective effect on the sidewalls of the conductive connection pillar 210.
In this embodiment, the number of the conductive connection posts 210 is several, the number of the solder layers 321 is several, and the number of the solder layers 321 between one conductive connection post 210 and the surface of the carrier 300 is one.
In this embodiment, the height of the solder layer 321 is 5 to 30 micrometers.
In this embodiment, the solder layer 321 includes a solder top surface in contact with the second surface; the radial dimension of the solder top surface is less than or equal to the total radial dimension of the first barrier layer 221 and the conductive connection stud 210.
The total radial dimension of the first barrier layer 221 and the conductive connection stud 210 is equal to the radial dimension of the conductive connection stud 210 plus 2 times the thickness of the first barrier layer 221.
In this embodiment, the carrier 300 is exemplified by a substrate (substrate), such as a PCB or BT board.
In other embodiments, referring to fig. 12, the carrier 301 is a lead frame (lead frame).
The solder column 320 is made of tin, tin-silver alloy, tin-silver-copper alloy or tin-lead alloy.
The package structure further includes: a molding layer 330 (refer to fig. 11 and 12), wherein the molding layer 330 is located on the surface of the carrier, and the molding layer 330 covers the semiconductor chip 200, the conductive connection pillar 210, the solder layer 321 and the first barrier layer 221.
When the carrier 300 is a substrate (substrate), the package structure further includes: solder balls 322 (refer to fig. 11) on the surface of the carrier plate 300 facing away from the semiconductor chip 200.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A package structure, comprising:
a semiconductor chip;
the conductive connecting column is provided with a first surface and a second surface which are opposite, and the first surface of the conductive connecting column is fixed with the surface of the semiconductor chip;
a first barrier layer on a sidewall of the conductive connection stud and not covering the second face;
the carrier plate is arranged opposite to the semiconductor chip, the conductive connecting column is positioned between the semiconductor chip and the carrier plate, and the second surface faces the carrier plate;
and the solder layer is positioned between the surface of the carrier plate and the second surface.
2. The package structure according to claim 1, wherein the material of the first barrier layer is an insulating glue.
3. The package structure of claim 1, wherein the material of the first barrier layer is a metal oxide.
4. The package structure of claim 3, wherein the conductive connection post is a copper post;
the material of the first barrier layer is copper oxide.
5. The package structure of claim 1, wherein the first barrier layer has a thickness of 10 to 30 microns.
6. The package structure of claim 1, wherein the number of the conductive connection posts is several, the number of the solder layers is several, and the number of the solder layers between one conductive connection post and the surface of the carrier board is one.
7. The package structure of claim 1, wherein the solder layer has a height of 5-30 microns.
8. The package structure of claim 1, wherein the solder layer comprises a solder top surface in contact with the second side; the radial dimension of the solder top surface is less than or equal to the total radial dimension of the first barrier layer and the conductive connection post.
9. The package structure of claim 1, further comprising: and the plastic packaging layer is positioned on the surface of the carrier plate and covers the semiconductor chip, the conductive connecting column, the solder layer and the first barrier layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810613771.6A CN110610914A (en) | 2018-06-14 | 2018-06-14 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810613771.6A CN110610914A (en) | 2018-06-14 | 2018-06-14 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110610914A true CN110610914A (en) | 2019-12-24 |
Family
ID=68887513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810613771.6A Pending CN110610914A (en) | 2018-06-14 | 2018-06-14 | Packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110610914A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| CN103730380A (en) * | 2013-12-05 | 2014-04-16 | 南通富士通微电子股份有限公司 | Forming method of packaging structure |
| CN104037143A (en) * | 2013-03-08 | 2014-09-10 | 台湾积体电路制造股份有限公司 | Package Having Substrate With Embedded Metal Trace Overlapped By Landing Pad |
-
2018
- 2018-06-14 CN CN201810613771.6A patent/CN110610914A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| CN104037143A (en) * | 2013-03-08 | 2014-09-10 | 台湾积体电路制造股份有限公司 | Package Having Substrate With Embedded Metal Trace Overlapped By Landing Pad |
| CN103730380A (en) * | 2013-12-05 | 2014-04-16 | 南通富士通微电子股份有限公司 | Forming method of packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4660643B2 (en) | Semiconductor package substrate for forming pre-solder structure, semiconductor package substrate on which pre-solder structure is formed, and manufacturing method thereof | |
| US8093721B2 (en) | Flip chip semiconductor package and fabrication method thereof | |
| US20180114786A1 (en) | Method of forming package-on-package structure | |
| JP4423285B2 (en) | Electronic component built-in substrate and method for manufacturing electronic component built-in substrate | |
| US9437565B2 (en) | Semiconductor substrate and semiconductor package structure having the same | |
| JP2000200859A (en) | Chip size semiconductor package, aggregate thereof and manufacture thereof | |
| CN104685622A (en) | BVA interposer | |
| KR20140017295A (en) | Semiconductor devices having multi-bump structural electrical interconnections and methods for fabricating the same | |
| KR100618838B1 (en) | Stack type multi-chip package improving a connection reliability of stacked chips | |
| US20040227223A1 (en) | Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device | |
| KR101211724B1 (en) | Semiconductor package with nsmd type solder mask and method for manufacturing the same | |
| CN110610916B (en) | Packaging structure | |
| US10553558B2 (en) | Semiconductor device | |
| JP2009188275A (en) | Semiconductor chip, semiconductor device, method for manufacturing same, and liquid crystal module | |
| CN108598046B (en) | Chip packaging structure and packaging method thereof | |
| CN110610914A (en) | Packaging structure | |
| CN108847396B (en) | Flip-chip method | |
| CN103915397A (en) | Multi-die, high current wafer level package | |
| JP2009099816A (en) | Semiconductor device, method of manufacturing the same and mounting method of semiconductor device | |
| CN110610870A (en) | Flip-chip method | |
| TWI399838B (en) | Pillar-to-pillar flip-chip assembly | |
| KR102494595B1 (en) | Semiconductor package | |
| CN110610915B (en) | Flip-chip method | |
| US10770425B2 (en) | Flip-chip method | |
| CN212461680U (en) | Three-dimensional package structure that piles up of wafer level chip fan-out |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |