JP2005079379A - Terminal electrode, semiconductor device, semiconductor module, electronic equipment, method of manufacturing terminal electrode, and method of manufacturing semiconductor module - Google Patents

Terminal electrode, semiconductor device, semiconductor module, electronic equipment, method of manufacturing terminal electrode, and method of manufacturing semiconductor module Download PDF

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JP2005079379A
JP2005079379A JP2003308696A JP2003308696A JP2005079379A JP 2005079379 A JP2005079379 A JP 2005079379A JP 2003308696 A JP2003308696 A JP 2003308696A JP 2003308696 A JP2003308696 A JP 2003308696A JP 2005079379 A JP2005079379 A JP 2005079379A
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electrode
electrode pad
protective film
protruding
terminal
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Tomoko Nako
朋子 名古
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Seiko Epson Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector

Abstract

<P>PROBLEM TO BE SOLVED: To increase the joint area of a projecting electrode without increasing the number of steps. <P>SOLUTION: A protective film 4 is provided on an electrode pad 2 across the pad 2, and the recessed section 7 corresponding to the shape of the protective film 4 is formed on the surface of the projecting electrode 6 by electroless plating. Then the projecting electrode 6 is joined to a terminal electrode in a state where the terminal electrode is fitted in the recessed section 7 of the projecting electrode 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は端子電極、半導体装置、半導体モジュール、電子機器、端子電極の製造方法および半導体モジュールの製造方法の製造方法に関し、特に、端子電極の接合方法に適用して好適なものである。   The present invention relates to a terminal electrode, a semiconductor device, a semiconductor module, an electronic device, a method for manufacturing a terminal electrode, and a method for manufacturing a semiconductor module, and is particularly suitable for application to a method for bonding terminal electrodes.

従来の半導体装置では、無電解Niメッキを用いて電極パッド上に突出電極を形成する方法がある。そして、半田印刷または半田ディップを用いて半田層を突出電極上に形成し、半田層を介して突出電極をリード端子上に接合することが行われている。
また、例えば、特許文献1には、リードとバンプ電極とを接合させる際の位置ずれを防止するために、リードを嵌入させる凹陥部をバンプ電極の上面に形成する方法が開示されている。
特開平2−140935号公報
In a conventional semiconductor device, there is a method of forming a protruding electrode on an electrode pad using electroless Ni plating. Then, solder printing or solder dip is used to form a solder layer on the protruding electrode, and the protruding electrode is bonded to the lead terminal via the solder layer.
Further, for example, Patent Document 1 discloses a method of forming a concave portion into which the lead is inserted on the upper surface of the bump electrode in order to prevent a positional shift when the lead and the bump electrode are joined.
JP-A-2-140935

しかしながら、無電解Niメッキを用いて突出電極を形成すると、突出電極が硬くなる。このため、接合時の荷重を突出電極で吸収し難くなり、電極パッド下にクラックが入り易くなるという問題があった。
また、特許文献1に開示された方法では、バンプ電極の周囲を盛り上げるためのレジストパターンを形成する必要があり、工程増を招くという問題があった。
However, when the protruding electrode is formed using electroless Ni plating, the protruding electrode becomes hard. For this reason, the load at the time of joining becomes difficult to absorb with the protruding electrode, and there is a problem that cracks are easily formed under the electrode pad.
Further, the method disclosed in Patent Document 1 has a problem in that it is necessary to form a resist pattern for raising the periphery of the bump electrode, which increases the number of processes.

そこで、本発明の目的は、製造工程の煩雑化を抑制しつつ、突出電極の接合面積を増加させることが可能な端子電極、半導体装置、半導体モジュール、電子機器、端子電極の製造方法および半導体モジュールの製造方法を提供することである。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a terminal electrode, a semiconductor device, a semiconductor module, an electronic device, a method of manufacturing a terminal electrode, and a semiconductor module that can increase the bonding area of protruding electrodes while suppressing the complexity of the manufacturing process It is to provide a manufacturing method.

上述した課題を解決するために、本発明の一態様に係る端子電極によれば、電極パッドと、前記電極パッドを横切るように配置された保護膜と、前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする。
これにより、無電解メッキを用いて突出電極を形成することで、保護膜上の成長を抑制することができ、突出電極の表面を横切るように配置された凹部を設けることが可能となる。このため、突出電極をリード端子に接合する際に、リード端子を突出電極の凹部に嵌め込むことが可能となり、製造工程の煩雑化を抑制しつつ、突出電極の接合面積を増加させることが可能となる。この結果、突出電極が硬い材料で構成されている場合においても、接合時の荷重を突出電極で吸収し易くすることが可能となり、電極パッド下にクラックが入り難くすることが可能となる。
In order to solve the above-described problem, according to a terminal electrode according to an aspect of the present invention, an electrode pad, a protective film disposed so as to cross the electrode pad, and the protection formed on the electrode pad are provided. A concave electrode corresponding to the arrangement position of the film is provided with a protruding electrode provided on the surface.
Thus, by forming the protruding electrode using electroless plating, growth on the protective film can be suppressed, and a recess disposed so as to cross the surface of the protruding electrode can be provided. For this reason, when joining the projecting electrode to the lead terminal, the lead terminal can be fitted into the recess of the projecting electrode, and the joining area of the projecting electrode can be increased while suppressing the complexity of the manufacturing process. It becomes. As a result, even when the protruding electrode is made of a hard material, it is possible to easily absorb the load at the time of bonding by the protruding electrode, and it is possible to prevent cracks from entering the electrode pad.

また、本発明の一態様に係る端子電極によれば、絶縁層上に形成された電極パッドと、前記電極パッドを分断する開口部と、前記電極パッド上に形成され、前記開口部に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする。
これにより、無電解メッキを用いて突出電極を形成することで、開口部上の成長を抑制することができ、突出電極の表面を横切るように配置された凹部を設けることが可能となる。このため、突出電極をリード端子に接合する際に、リード端子を突出電極の凹部に嵌め込むことが可能となり、製造工程の煩雑化を抑制しつつ、突出電極の接合面積を増加させることが可能となる。この結果、突出電極が硬い材料で構成されている場合においても、接合時の荷重を突出電極で吸収し易くすることが可能となり、電極パッド下にクラックが入り難くすることが可能となる。
Moreover, according to the terminal electrode which concerns on 1 aspect of this invention, it formed on the electrode pad formed on the insulating layer, the opening part which divides the said electrode pad, and the said electrode pad, and respond | corresponded to the said opening part And a concave electrode provided on the surface of the concave electrode.
Thus, by forming the protruding electrode using electroless plating, growth on the opening can be suppressed, and a recess disposed so as to cross the surface of the protruding electrode can be provided. For this reason, when joining the projecting electrode to the lead terminal, the lead terminal can be fitted into the recess of the projecting electrode, and the joining area of the projecting electrode can be increased while suppressing the complexity of the manufacturing process. It becomes. As a result, even when the protruding electrode is made of a hard material, it is possible to easily absorb the load at the time of bonding by the protruding electrode, and it is possible to prevent cracks from entering the electrode pad.

また、本発明の一態様に係る半導体装置によれば、半導体チップと、前記半導体チップ上に形成された電極パッドと、前記電極パッドを横切るように配置された保護膜と、前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする。
これにより、突出電極の形成時に、突出電極の表面を横切るように配置された凹部を設けることが可能となり、製造工程の煩雑化を抑制しつつ、突出電極の接合面積を増加させることが可能となる。このため、突出電極が硬い材料で構成されている場合においても、接合時の荷重を突出電極で吸収し易くすることが可能となり、電極パッド下にクラックが入り難くすることが可能となる。
In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor chip, the electrode pad formed over the semiconductor chip, the protective film disposed across the electrode pad, and the electrode pad And a protruding electrode formed on the surface with a recess corresponding to the position of the protective film.
As a result, when forming the protruding electrode, it is possible to provide a recess disposed across the surface of the protruding electrode, and it is possible to increase the bonding area of the protruding electrode while suppressing the complexity of the manufacturing process. Become. For this reason, even when the protruding electrode is made of a hard material, it is possible to easily absorb the load at the time of bonding with the protruding electrode, and it is possible to prevent cracks from entering the electrode pad.

また、本発明の一態様に係る半導体モジュールによれば、半導体チップと、前記半導体チップ上に形成された電極パッドと、前記電極パッドを横切るように配置された保護膜と、前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極と、前記凹部に嵌め込まれた状態で、前記突出電極と接合された端子電極と、前記端子電極が設けられた配線基板とを備えることを特徴とする。   Moreover, according to the semiconductor module which concerns on 1 aspect of this invention, a semiconductor chip, the electrode pad formed on the said semiconductor chip, the protective film arrange | positioned across the said electrode pad, and on the said electrode pad A protruding electrode formed and provided with a concave portion corresponding to the position of the protective film on the surface, a terminal electrode joined to the protruding electrode in a state fitted in the concave portion, and the terminal electrode were provided And a wiring board.

これにより、突出電極を端子電極に接合する際に、端子電極を突出電極の凹部に嵌め込むことが可能となり、突出電極の接合面積を増加させることが可能となる。このため、突出電極が硬い材料で構成されている場合においても、接合時の荷重を突出電極で吸収し易くして、電極パッド下にクラックが入り難くすることが可能となる。
また、本発明の一態様に係る半導体モジュールによれば、前記配線基板に設けられた端子電極の先端は先鋭化されていることを特徴とする。
Accordingly, when the protruding electrode is bonded to the terminal electrode, the terminal electrode can be fitted into the concave portion of the protruding electrode, and the bonding area of the protruding electrode can be increased. For this reason, even when the protruding electrode is made of a hard material, it is possible to easily absorb the load at the time of bonding by the protruding electrode, and to prevent cracks from entering the electrode pad.
The semiconductor module according to one aspect of the present invention is characterized in that the tip of the terminal electrode provided on the wiring board is sharpened.

これにより、端子電極の先端の形状を突出電極の表面に設けられた凹部の形状に対応させることが可能となる。このため、端子電極の先端と突出電極の凹部との接触面積を増加させることが可能となり、接合時の荷重を突出電極で吸収し易くすることを可能として、電極パッド下にクラックが入り難くすることが可能となる。
また、本発明の一態様に係る電子機器によれば、半導体チップと、前記半導体チップ上に形成された電極パッドと、前記電極パッドを横切るように配置された保護膜と、前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極と、前記凹部に嵌め込まれた状態で、前記突出電極と接合された端子電極と、前記端子電極が設けられた配線基板と、前記配線基板を介して前記半導体チップに接続された電子部品とを備えることを特徴とする。
Thereby, the shape of the tip of the terminal electrode can be made to correspond to the shape of the recess provided on the surface of the protruding electrode. For this reason, it becomes possible to increase the contact area between the tip of the terminal electrode and the recess of the protruding electrode, making it possible to easily absorb the load at the time of bonding with the protruding electrode, and making it difficult to crack under the electrode pad. It becomes possible.
According to the electronic device of one aspect of the present invention, a semiconductor chip, an electrode pad formed over the semiconductor chip, a protective film disposed across the electrode pad, and the electrode pad A protruding electrode formed and provided with a concave portion corresponding to the position of the protective film on the surface, a terminal electrode joined to the protruding electrode in a state fitted in the concave portion, and the terminal electrode were provided A wiring board and an electronic component connected to the semiconductor chip through the wiring board are provided.

これにより、端子電極を突出電極の凹部に嵌め込みながら、突出電極を端子電極に接合させることが可能となる。このため、実装面積の増大を抑制しつつ、接合時の過重を突出電極に吸収させることが可能となり、電子機器の小型・軽量化を可能としつつ、電子機器の信頼性を向上させることができる。
また、本発明の一態様に係る端子電極の製造方法によれば、絶縁層上に電極パッドを形成する工程と、前記電極パッド上に保護膜を形成する工程と、前記保護膜をエッチング加工することにより、前記保護膜が前記電極パッドを横切るようにして、前記電極パッドの表面を露出させる工程と、無電解メッキにより、前記電極パッド上に突出電極を形成する工程とを備えることを特徴とする。
Thereby, it becomes possible to join the protruding electrode to the terminal electrode while fitting the terminal electrode into the concave portion of the protruding electrode. For this reason, it is possible to absorb the excessive weight at the time of joining to the protruding electrode while suppressing an increase in the mounting area, and it is possible to improve the reliability of the electronic device while making the electronic device smaller and lighter. .
According to the method for manufacturing the terminal electrode according to one aspect of the present invention, the step of forming the electrode pad on the insulating layer, the step of forming the protective film on the electrode pad, and etching the protective film A step of exposing the surface of the electrode pad so that the protective film crosses the electrode pad; and a step of forming a protruding electrode on the electrode pad by electroless plating. To do.

これにより、電極パッド上に形成される保護膜のパターンを変更することで、突出電極の表面を横切るように配置された凹部を形成することが可能となる。このため、工程増を伴うことなく、突出電極の接合面積を増加させることが可能となり、スループットの低下を抑制しつつ、接合時の荷重を突出電極で吸収し易くすることができる。
また、本発明の一態様に係る半導体モジュールの製造方法によれば、保護膜の配置位置に対応した凹部が突出電極の表面に形成された半導体チップと配線基板との位置合わせを行う工程と、前記突出電極の表面の凹部に前記配線基板の端子電極を嵌め合わせた状態で、前記配線基板の端子電極に前記突出電極を接合させる工程とを備えることを特徴とする。
Thus, by changing the pattern of the protective film formed on the electrode pad, it is possible to form a recess that is disposed across the surface of the protruding electrode. For this reason, it is possible to increase the bonding area of the protruding electrode without increasing the number of steps, and it is possible to easily absorb the load during bonding with the protruding electrode while suppressing a decrease in throughput.
In addition, according to the method for manufacturing a semiconductor module according to one aspect of the present invention, the step of aligning the semiconductor chip and the wiring substrate, in which the recess corresponding to the position of the protective film is formed on the surface of the protruding electrode, A step of bonding the protruding electrode to the terminal electrode of the wiring board in a state in which the terminal electrode of the wiring board is fitted in the concave portion on the surface of the protruding electrode.

これにより、工程増を伴うことなく、突出電極の接合面積を増加させることが可能となり、スループットの低下を抑制しつつ、接合時の荷重を突出電極で吸収し易くすることができる。   Accordingly, it is possible to increase the bonding area of the protruding electrode without increasing the number of processes, and it is possible to easily absorb the load during bonding with the protruding electrode while suppressing a decrease in throughput.

以下、本発明の実施形態に係る端子電極および半導体モジュールの製造方法について図面を参照しながら説明する。
図1(a)、(c)、(d)および図2は、本発明の第1実施形態に係る半導体モジュールの製造方法を示す断面図、図1(b)は、電極パッド2上の保護膜3の構成を示す平面図である。
Hereinafter, a method for manufacturing a terminal electrode and a semiconductor module according to an embodiment of the present invention will be described with reference to the drawings.
1A, 1C, 1D, and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor module according to the first embodiment of the present invention, and FIG. 3 is a plan view showing a configuration of a film 3. FIG.

図1(a)において、半導体チップ1には電極パッド2が設けられ、電極パッド2が設けられた半導体チップ1の表面は保護膜3で被覆されている。なお、半導体チップ1には、トランジスタなどの能動素子またはキャパシタなどの受動素子を形成することができる。また、保護膜3としては、例えば、シリコン酸化膜、シリコン窒化膜またはポリイミド膜などを用いることができる。ここで、保護膜3には、例えば、図1(b)に示すように、電極パッド2の表面を露出させる開口部3aが形成されるとともに、電極パッド2上に、電極パッド2を横切るように配置された保護膜4が設けられている。   In FIG. 1A, an electrode pad 2 is provided on a semiconductor chip 1, and the surface of the semiconductor chip 1 provided with the electrode pad 2 is covered with a protective film 3. Note that an active element such as a transistor or a passive element such as a capacitor can be formed on the semiconductor chip 1. As the protective film 3, for example, a silicon oxide film, a silicon nitride film, a polyimide film, or the like can be used. Here, for example, as shown in FIG. 1B, the protective film 3 has an opening 3 a that exposes the surface of the electrode pad 2, and crosses the electrode pad 2 on the electrode pad 2. A protective film 4 is provided.

なお、電極パッド2を横切るように配置された保護膜4を形成する場合、保護膜3のエッチング加工時に、電極パッド2の表面を露出させる開口部3aの形成と一括して行うことができる。
次に、図1(c)に示すように、保護膜3、4が形成された半導体チップ1上に感光性樹脂層5を塗布する。なお、感光性樹脂層5は、例えば、スピンコート、カーテンコート、スクリーン印刷、インクジェット法などを用いて形成することができる。そして、感光性樹脂層5の露光・現像を行うことにより、電極パッド2の表面を露出させる開口部5aを感光性樹脂層5に形成する。
In addition, when forming the protective film 4 arrange | positioned so that the electrode pad 2 may be crossed, it can carry out collectively with formation of the opening part 3a which exposes the surface of the electrode pad 2 at the time of the etching process of the protective film 3. FIG.
Next, as shown in FIG. 1C, a photosensitive resin layer 5 is applied on the semiconductor chip 1 on which the protective films 3 and 4 are formed. The photosensitive resin layer 5 can be formed by using, for example, spin coating, curtain coating, screen printing, an inkjet method, or the like. Then, by performing exposure / development of the photosensitive resin layer 5, an opening 5 a that exposes the surface of the electrode pad 2 is formed in the photosensitive resin layer 5.

次に、図1(d)に示すように、無電解メッキを用いることにより、電極パッド2上に配置された突出電極6を開口部5a内に形成する。なお、突出電極6の材料としては、例えば、ニッケルNi、金Au、銅Cuなどを用いることができる。また、ニッケルNiで形成された突出電極6上には、銅Cu、錫Snまたは金Auなどのキャップ層を形成してもよく、突出電極6上に形成されたキャップ層を介して半田層を形成するようにしてもよい。   Next, as shown in FIG.1 (d), the protruding electrode 6 arrange | positioned on the electrode pad 2 is formed in the opening part 5a by using electroless plating. As a material for the protruding electrode 6, for example, nickel Ni, gold Au, copper Cu, or the like can be used. Further, a cap layer such as copper Cu, tin Sn or gold Au may be formed on the protruding electrode 6 made of nickel Ni, and a solder layer is formed via the cap layer formed on the protruding electrode 6. You may make it form.

ここで、無電解メッキでは、電極パッド2上で金属の成膜が進行し、保護膜4上では金属の成膜が抑制されるため、保護膜4上で突出電極6が窪むようになる。このため、無電解メッキを用いて電極パッド2上に突出電極6を形成することにより、電極パッド2上の保護膜4の形状に対応した凹部7を突出電極6の表面に形成することができる。なお、凹部7の深さは、図2(a)の端子電極12の高さよりも小さくなるように設定することができる。   Here, in electroless plating, metal film formation proceeds on the electrode pad 2 and metal film formation is suppressed on the protective film 4, so that the protruding electrode 6 becomes depressed on the protective film 4. For this reason, by forming the protruding electrode 6 on the electrode pad 2 using electroless plating, the concave portion 7 corresponding to the shape of the protective film 4 on the electrode pad 2 can be formed on the surface of the protruding electrode 6. . In addition, the depth of the recessed part 7 can be set so that it may become smaller than the height of the terminal electrode 12 of Fig.2 (a).

次に、図2(a)に示すように、感光性樹脂層5を半導体チップ1から除去することにより、電極パッド2上に形成された突出電極6の周囲を露出させる。そして、突出電極6と端子電極12とが対向して配置されるように、半導体チップ1と配線基板11とを位置合わせする。なお、配線基板11としては、例えば、両面基板、多層配線基板、ビルドアップ基板、テープ基板またはフィルム基板などを用いることができ、配線基板11の材質としては、例えば、ポリイミド樹脂、ガラスエポキシ樹脂、BTレジン、アラミドとエポキシのコンポジットまたはセラミックなどを用いることができる。また、端子電極12としては、例えば、金Auや錫Snなどで被覆された銅Cuなどを用いることができる。また、突出電極6の凹部7の形状に対応して端子電極12の先端を先鋭化させるようにしてもよく、例えば、端子電極12の断面形状を三角形状にすることができる。   Next, as shown in FIG. 2A, the periphery of the protruding electrode 6 formed on the electrode pad 2 is exposed by removing the photosensitive resin layer 5 from the semiconductor chip 1. Then, the semiconductor chip 1 and the wiring substrate 11 are aligned so that the protruding electrode 6 and the terminal electrode 12 are arranged to face each other. In addition, as the wiring board 11, for example, a double-sided board, a multilayer wiring board, a build-up board, a tape board, or a film board can be used, and as the material of the wiring board 11, for example, polyimide resin, glass epoxy resin, BT resin, aramid and epoxy composite, ceramic, or the like can be used. Moreover, as the terminal electrode 12, copper Cu etc. which were coat | covered with gold | metal | money Au, tin Sn, etc. can be used, for example. Moreover, you may make it sharpen the front-end | tip of the terminal electrode 12 corresponding to the shape of the recessed part 7 of the protrusion electrode 6, for example, the cross-sectional shape of the terminal electrode 12 can be made into a triangular shape.

次に、図2(b)に示すように、端子電極12が突出電極6の凹部7に嵌め込まれた状態で、突出電極6を端子電極12に接合させることにより、半導体チップ1を配線基板11上にフリップチップ実装する。そして、配線基板11上に実装された半導体チップ1の表面に封止樹脂13を注入することにより、半導体チップ1を樹脂封止する。
これにより、端子電極12を突出電極6の凹部7に嵌め込むことで突出電極6の接合面積を増加させることが可能となる。このため、突出電極6がニッケルNiなどの硬い材料で構成されている場合においても、接合時の荷重を突出電極6で吸収し易くして、電極パッド2下の半導体チップ1にクラックが入り難くすることが可能となる。
Next, as shown in FIG. 2B, the semiconductor chip 1 is bonded to the wiring substrate 11 by joining the protruding electrode 6 to the terminal electrode 12 in a state where the terminal electrode 12 is fitted in the recess 7 of the protruding electrode 6. Flip chip mounting on top. Then, the semiconductor chip 1 is resin-sealed by injecting a sealing resin 13 into the surface of the semiconductor chip 1 mounted on the wiring substrate 11.
Thereby, it becomes possible to increase the bonding area of the protruding electrode 6 by fitting the terminal electrode 12 into the recess 7 of the protruding electrode 6. For this reason, even when the protruding electrode 6 is made of a hard material such as nickel Ni, the protruding electrode 6 can easily absorb the load at the time of bonding, and the semiconductor chip 1 under the electrode pad 2 is hardly cracked. It becomes possible to do.

なお、突出電極6を端子電極12に接合させる場合、ACF(Anisotropic Conductive Film)接合、NCF(Nonconductive Film)接合、ACP(Anisotropic Conductive Paste)接合、NCP(Nonconductive Paste)接合などの圧接接合を用いるようにしてもよいし、半田接合や合金接合などの金属接合を用いるようにしてもよい。   When the protruding electrode 6 is bonded to the terminal electrode 12, an ACF (Anisotropic Conductive Film) junction, an NCF (Nonconductive Film) junction, an ACP (Anisotropic Conductive Paste) junction, an NCP (Nonconductive pressure junction), or the like. Alternatively, metal bonding such as solder bonding or alloy bonding may be used.

図3(a)、(c)、(d)および図4は、本発明の第2実施形態に係る半導体モジュールの製造方法を示す断面図、図3(b)は、電極パッド22の構成を示す平面図である。
図3(a)において、半導体チップ21には電極パッド22が設けられ、電極パッド22が設けられた半導体チップ21の表面は保護膜23で被覆されている。そして、保護膜23には、電極パッド22の表面を露出させる開口部23aが設けられている。ここで、電極パッド22の中央には、例えば、図3(b)に示すように、電極パッド22を分断する開口部24が設けられている。
3 (a), 3 (c), 3 (d) and 4 are sectional views showing a method of manufacturing a semiconductor module according to the second embodiment of the present invention, and FIG. FIG.
In FIG. 3A, an electrode pad 22 is provided on the semiconductor chip 21, and the surface of the semiconductor chip 21 provided with the electrode pad 22 is covered with a protective film 23. The protective film 23 is provided with an opening 23 a that exposes the surface of the electrode pad 22. Here, in the center of the electrode pad 22, for example, as shown in FIG. 3B, an opening 24 for dividing the electrode pad 22 is provided.

なお、電極パッド22を分断する開口部24を形成する場合、電極パッド22を形成するためのエッチング加工時に一括して行うことができる。
次に、図3(c)に示すように、保護膜23が形成された半導体チップ21上に感光性樹脂層25を塗布する。そして、感光性樹脂層25の露光・現像を行うことにより、電極パッド22の表面を露出させる開口部25aを感光性樹脂層25に形成する。
In addition, when forming the opening part 24 which divides the electrode pad 22, it can carry out collectively at the time of the etching process for forming the electrode pad 22. FIG.
Next, as shown in FIG. 3C, a photosensitive resin layer 25 is applied on the semiconductor chip 21 on which the protective film 23 is formed. Then, by performing exposure / development of the photosensitive resin layer 25, an opening 25 a that exposes the surface of the electrode pad 22 is formed in the photosensitive resin layer 25.

次に、図3(d)に示すように、無電解メッキを用いることにより、電極パッド22上に配置された突出電極26を開口部25a内に形成する。なお、突出電極26の材料としては、例えば、ニッケルNi、金Au、銅Cuなどを用いることができる。ここで、無電解メッキでは、電極パッド22上で金属の成膜が進行し、電極パッド22下の絶縁層上では金属の成膜が抑制されるため、電極パッド22に設けられた開口部24上で突出電極26が窪むようになる。このため、無電解メッキを用いて電極パッド22上に突出電極26を形成することにより、開口部24の形状に対応した凹部27を突出電極26の表面に形成することができる。なお、凹部27の深さは、図4(a)の端子電極32の高さよりも小さくなるように設定することができる。   Next, as shown in FIG. 3D, the protruding electrode 26 disposed on the electrode pad 22 is formed in the opening 25a by using electroless plating. As a material of the protruding electrode 26, for example, nickel Ni, gold Au, copper Cu, or the like can be used. Here, in electroless plating, metal film formation proceeds on the electrode pad 22, and metal film formation is suppressed on the insulating layer under the electrode pad 22, so the opening 24 provided in the electrode pad 22. The protruding electrode 26 becomes recessed above. For this reason, by forming the protruding electrode 26 on the electrode pad 22 using electroless plating, the concave portion 27 corresponding to the shape of the opening 24 can be formed on the surface of the protruding electrode 26. In addition, the depth of the recessed part 27 can be set so that it may become smaller than the height of the terminal electrode 32 of Fig.4 (a).

次に、図4(a)に示すように、感光性樹脂層25を半導体チップ21から除去することにより、電極パッド22上に形成された突出電極26の周囲を露出させる。そして、突出電極26と端子電極32とが対向して配置されるように、半導体チップ21と配線基板31とを位置合わせする。
次に、図4(b)に示すように、端子電極32が突出電極26の凹部27に嵌め込まれた状態で、突出電極26を端子電極32に接合させることにより、半導体チップ21を配線基板31上にフリップチップ実装する。そして、配線基板31上に実装された半導体チップ21の表面に封止樹脂33を注入することにより、半導体チップ21を樹脂封止する。
Next, as shown in FIG. 4A, the photosensitive resin layer 25 is removed from the semiconductor chip 21 to expose the periphery of the protruding electrode 26 formed on the electrode pad 22. Then, the semiconductor chip 21 and the wiring substrate 31 are aligned so that the protruding electrode 26 and the terminal electrode 32 are arranged to face each other.
Next, as shown in FIG. 4B, the semiconductor chip 21 is connected to the wiring substrate 31 by bonding the protruding electrode 26 to the terminal electrode 32 in a state where the terminal electrode 32 is fitted in the concave portion 27 of the protruding electrode 26. Flip chip mounting on top. Then, the semiconductor chip 21 is resin-sealed by injecting a sealing resin 33 into the surface of the semiconductor chip 21 mounted on the wiring substrate 31.

これにより、端子電極32を突出電極26の凹部27に嵌め込むことで突出電極26の接合面積を増加させることが可能となる。このため、突出電極26がニッケルNiなどの硬い材料で構成されている場合においても、接合時の荷重を突出電極26で吸収し易くして、電極パッド22下の半導体チップ21にクラックが入り難くすることが可能となる。
図5は、本発明の第3実施形態に係る回路基板の製造方法を示す断面図である。
Thus, the joint area of the protruding electrode 26 can be increased by fitting the terminal electrode 32 into the recess 27 of the protruding electrode 26. For this reason, even when the protruding electrode 26 is made of a hard material such as nickel Ni, the protruding electrode 26 can easily absorb the load at the time of bonding, and the semiconductor chip 21 under the electrode pad 22 is hardly cracked. It becomes possible to do.
FIG. 5 is a sectional view showing a circuit board manufacturing method according to the third embodiment of the present invention.

図5(a)において、銅Cuなどからなる金属箔を配線基板41上に貼り付けることにより、配線基板41上に導電層42を形成する。
次に、図5(b)に示すように、導電層42上にレジストを塗布する。そして導電層42上に塗布されたレジストの露光・現像を行うことにより、所定間隔だけ隔てて配置されたレジスト層43を導電層42上に形成する。
In FIG. 5A, a conductive layer 42 is formed on the wiring board 41 by attaching a metal foil made of copper Cu or the like on the wiring board 41.
Next, as shown in FIG. 5B, a resist is applied on the conductive layer 42. Then, the resist applied on the conductive layer 42 is exposed and developed to form a resist layer 43 arranged at a predetermined interval on the conductive layer 42.

次に、図5(c)に示すように、レジスト層43をマスクとして、導電層42の等方性エッチングを行うことにより、配線基板41の表面を露出させ、接合面が先鋭化された端子電極44を配線基板41上に形成する。なお、導電層42の等方性エッチングとしては、ウエットエッチングまたはプラズマエッチングなどを用いることができる。そして、図5(d)に示すように、端子電極44上のレジスト層43を除去する。   Next, as shown in FIG. 5C, isotropic etching of the conductive layer 42 is performed using the resist layer 43 as a mask to expose the surface of the wiring board 41 and the terminals with sharpened joint surfaces. The electrode 44 is formed on the wiring substrate 41. As the isotropic etching of the conductive layer 42, wet etching or plasma etching can be used. Then, as shown in FIG. 5D, the resist layer 43 on the terminal electrode 44 is removed.

ここで、導電層42の等方性エッチングを用いて配線基板41の表面を露出させることにより、導電層42の厚み方向におけるエッチング量を変化させることが可能となり、導電層42の上面に近づくに従って横方向のエッチング量を増やすことが可能となる。このため、端子電極44の先端を先鋭化させながら、端子電極44を配線基板41上に形成することが可能となり、製造工程の煩雑化を抑制しつつ、端子電極44の接合面積を増加させて、接合時の荷重を吸収させ易くすることが可能となる。   Here, by exposing the surface of the wiring substrate 41 using isotropic etching of the conductive layer 42, it becomes possible to change the etching amount in the thickness direction of the conductive layer 42, and as the surface of the conductive layer 42 is approached. It becomes possible to increase the etching amount in the lateral direction. Therefore, it is possible to form the terminal electrode 44 on the wiring substrate 41 while sharpening the tip of the terminal electrode 44, and to increase the bonding area of the terminal electrode 44 while suppressing the complexity of the manufacturing process. It becomes possible to easily absorb the load at the time of joining.

図6は、本発明の第4実施形態に係る回路基板の製造方法を示す断面図である。
図6(a)において、端子電極55の配置位置に対応してシード電極52を配線基板51上に形成する。
そして、図6(b)に示すように、型枠53には、先端が先鋭化された凹部54が設けられている。そして、シード電極52上に凹部54が配置されるようにして、配線基板51上に型枠53を押し付ける。なお、型枠53の材質としては、例えば、ガラスまたは樹脂を用いることができる。あるいは、凹部54の表面に剥離剤が塗布された金型を用いるようにしてもよい。
FIG. 6 is a sectional view showing a circuit board manufacturing method according to the fourth embodiment of the present invention.
In FIG. 6A, the seed electrode 52 is formed on the wiring substrate 51 corresponding to the arrangement position of the terminal electrode 55.
As shown in FIG. 6B, the mold 53 is provided with a recess 54 with a sharpened tip. Then, the mold 53 is pressed onto the wiring substrate 51 so that the concave portion 54 is disposed on the seed electrode 52. In addition, as a material of the formwork 53, glass or resin can be used, for example. Alternatively, a mold in which a release agent is applied to the surface of the recess 54 may be used.

次に、図6(c)に示すように、配線基板51上に型枠53を押し付けながら、シード電極52上に電解メッキを行うことにより、凹部54の形状に対応した端子電極55を配線基板51上に形成する。そして、図6(d)に示すように、配線基板51上に端子電極55が形成されると、配線基板51上の型枠53を除去する。
これにより、型枠53に設けられた凹部54の形状を変更することで、端子電極54の先端を先鋭化させながら、端子電極54を配線基板51上に形成することが可能となる。このため、製造工程の煩雑化を抑制しつつ、端子電極54の接合面積を増加させることが可能となり、接合時の荷重を吸収させ易くすることができる。
Next, as shown in FIG. 6C, the terminal electrode 55 corresponding to the shape of the recess 54 is formed by performing electrolytic plating on the seed electrode 52 while pressing the mold 53 on the wiring substrate 51. 51 is formed. Then, as shown in FIG. 6D, when the terminal electrode 55 is formed on the wiring substrate 51, the mold 53 on the wiring substrate 51 is removed.
Accordingly, by changing the shape of the recess 54 provided in the mold 53, the terminal electrode 54 can be formed on the wiring substrate 51 while sharpening the tip of the terminal electrode 54. For this reason, it becomes possible to increase the joining area of the terminal electrode 54, suppressing complication of the manufacturing process, and to easily absorb the load at the time of joining.

図7は、本発明の第5実施形態に係る回路基板の製造方法を示す断面図である。
図7(a)において、配線基板61上にインクジェットヘッド63を配置する。そして、図7(b)に示すように、インクジェットヘッド63の位置を制御しながら、インクジェットヘッド63を介し、導電性材料からなる液滴64を配線基板61上に吐出させることで、接合面が先鋭化された端子電極62を配線基板61上に形成する。なお、液滴63としては、例えば、ニッケルNi、金Auまたは銅Cuなどの金属粉が溶媒に分散された金属スラリーあるいは金属ペーストなどを用いることができる。
FIG. 7 is a sectional view showing a circuit board manufacturing method according to the fifth embodiment of the present invention.
In FIG. 7A, the inkjet head 63 is disposed on the wiring board 61. Then, as shown in FIG. 7B, while controlling the position of the inkjet head 63, droplets 64 made of a conductive material are ejected onto the wiring substrate 61 via the inkjet head 63, so that the bonding surface is A sharpened terminal electrode 62 is formed on the wiring board 61. As the droplet 63, for example, a metal slurry or a metal paste in which a metal powder such as nickel Ni, gold Au, or copper Cu is dispersed in a solvent can be used.

これにより、液滴64の吐出位置を制御することで、端子電極62の形状を変化させることが可能となり、接合面が先鋭化された端子電極62を配線基板61上に容易に形成することが可能となる。
なお、上述した半導体モジュールは、例えば、液晶表示装置、携帯電話、携帯情報端末、ビデオカメラ、デジタルカメラ、MD(Mini Disc)プレーヤ、ICカード、ICタグなどの電子機器に適用することができ、電子機器の小型・軽量化を可能としつつ、電子機器の信頼性を向上させることができる。
Thus, by controlling the discharge position of the droplet 64, the shape of the terminal electrode 62 can be changed, and the terminal electrode 62 having a sharp joint surface can be easily formed on the wiring substrate 61. It becomes possible.
Note that the semiconductor module described above can be applied to electronic devices such as a liquid crystal display device, a mobile phone, a portable information terminal, a video camera, a digital camera, an MD (Mini Disc) player, an IC card, and an IC tag. The electronic device can be reduced in size and weight, and the reliability of the electronic device can be improved.

また、上述した実施形態では、半導体チップの実装方法を例にとって説明したが、本発明は、必ずしも半導体チップの実装方法に限定されることなく、例えば、弾性表面波(SAW)素子などのセラミック素子、光変調器や光スイッチなどの光学素子、磁気センサやバイオセンサなどの各種センサ類などの実装方法に適用してもよい。   In the above-described embodiment, the semiconductor chip mounting method has been described as an example. However, the present invention is not necessarily limited to the semiconductor chip mounting method, and for example, a ceramic element such as a surface acoustic wave (SAW) element. The present invention may also be applied to mounting methods for optical elements such as optical modulators and optical switches, and various sensors such as magnetic sensors and biosensors.

本発明の第1実施形態に係る半導体モジュールの製造方法を示す図。The figure which shows the manufacturing method of the semiconductor module which concerns on 1st Embodiment of this invention. 本発明の第1実施形態に係る半導体モジュールの製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the semiconductor module which concerns on 1st Embodiment of this invention. 本発明の第2実施形態に係る半導体モジュールの製造方法を示す図。The figure which shows the manufacturing method of the semiconductor module which concerns on 2nd Embodiment of this invention. 本発明の第2実施形態に係る半導体モジュールの製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the semiconductor module which concerns on 2nd Embodiment of this invention. 本発明の第3実施形態に係る回路基板の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the circuit board which concerns on 3rd Embodiment of this invention. 本発明の第4実施形態に係る回路基板の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the circuit board which concerns on 4th Embodiment of this invention. 本発明の第5実施形態に係る回路基板の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the circuit board which concerns on 5th Embodiment of this invention.

符号の説明Explanation of symbols

1、21 半導体チップ、2、22 電極パッド、3、4、23、 保護膜、3a、23a、24 開口部、5、25 感光性樹脂層、6、26 突出電極、7、27、54 凹部、11、31、41、51、61 配線基板、12、32、44、55、62 端子電極、13、33 封止樹脂、42 導電層、43 レジスト、52 シード電極、53 型枠、63 インクジェットヘッド、64 液滴   1, 21 Semiconductor chip, 2, 22 Electrode pad 3, 4, 23, Protective film, 3a, 23a, 24 Open part, 5, 25 Photosensitive resin layer, 6, 26 Protruding electrode, 7, 27, 54 Recessed part, 11, 31, 41, 51, 61 Wiring board, 12, 32, 44, 55, 62 Terminal electrode, 13, 33 Sealing resin, 42 Conductive layer, 43 Resist, 52 Seed electrode, 53 Mold frame, 63 Inkjet head, 64 droplets

Claims (8)

電極パッドと、
前記電極パッドを横切るように配置された保護膜と、
前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする端子電極。
An electrode pad;
A protective film disposed across the electrode pad;
A terminal electrode comprising: a protruding electrode formed on the electrode pad and provided with a concave portion on a surface thereof corresponding to an arrangement position of the protective film.
絶縁層上に形成された電極パッドと、
前記電極パッドを分断する開口部と、
前記電極パッド上に形成され、前記開口部に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする端子電極。
An electrode pad formed on the insulating layer;
An opening for dividing the electrode pad;
A terminal electrode comprising: a protruding electrode formed on the electrode pad and provided with a concave portion corresponding to the opening on a surface thereof.
半導体チップと、
前記半導体チップ上に形成された電極パッドと、
前記電極パッドを横切るように配置された保護膜と、
前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極とを備えることを特徴とする半導体装置。
A semiconductor chip;
An electrode pad formed on the semiconductor chip;
A protective film disposed across the electrode pad;
A semiconductor device comprising: a protruding electrode formed on the electrode pad and provided with a concave portion on a surface thereof corresponding to an arrangement position of the protective film.
半導体チップと、
前記半導体チップ上に形成された電極パッドと、
前記電極パッドを横切るように配置された保護膜と、
前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極と、
前記凹部に嵌め込まれた状態で、前記突出電極と接合された端子電極と、
前記端子電極が設けられた配線基板とを備えることを特徴とする半導体モジュール。
A semiconductor chip;
An electrode pad formed on the semiconductor chip;
A protective film disposed across the electrode pad;
A protruding electrode formed on the electrode pad and provided with a recess on the surface corresponding to the position of the protective film;
A terminal electrode joined to the protruding electrode in a state of being fitted in the recess;
A semiconductor module comprising: a wiring board provided with the terminal electrode.
前記配線基板に設けられた端子電極の先端は先鋭化されていることを特徴とする請求項4記載の半導体モジュール。   5. The semiconductor module according to claim 4, wherein the tip of the terminal electrode provided on the wiring board is sharpened. 半導体チップと、
前記半導体チップ上に形成された電極パッドと、
前記電極パッドを横切るように配置された保護膜と、
前記電極パッド上に形成され、前記保護膜の配置位置に対応した凹部が表面に設けられた突出電極と、
前記凹部に嵌め込まれた状態で、前記突出電極と接合された端子電極と、
前記端子電極が設けられた配線基板と、
前記配線基板を介して前記半導体チップに接続された電子部品とを備えることを特徴とする電子機器。
A semiconductor chip;
An electrode pad formed on the semiconductor chip;
A protective film disposed across the electrode pad;
A protruding electrode formed on the electrode pad and provided with a recess on the surface corresponding to the position of the protective film;
A terminal electrode joined to the protruding electrode in a state of being fitted in the recess;
A wiring board provided with the terminal electrodes;
An electronic device comprising: an electronic component connected to the semiconductor chip through the wiring board.
絶縁層上に電極パッドを形成する工程と、
前記電極パッド上に保護膜を形成する工程と、
前記保護膜をエッチング加工することにより、前記保護膜が前記電極パッドを横切るようにして、前記電極パッドの表面を露出させる工程と、
無電解メッキにより、前記電極パッド上に突出電極を形成する工程とを備えることを特徴とする端子電極の製造方法。
Forming an electrode pad on the insulating layer;
Forming a protective film on the electrode pad;
Etching the protective film to expose the surface of the electrode pad so that the protective film crosses the electrode pad;
And a step of forming a protruding electrode on the electrode pad by electroless plating.
保護膜の配置位置に対応した凹部が突出電極の表面に形成された半導体チップと配線基板との位置合わせを行う工程と、
前記突出電極の表面の凹部に前記配線基板の端子電極を嵌め合わせた状態で、前記配線基板の端子電極に前記突出電極を接合させる工程とを備えることを特徴とする半導体モジュールの製造方法。
A step of aligning the wiring substrate with the semiconductor chip in which the recess corresponding to the position of the protective film is formed on the surface of the protruding electrode;
And a step of bonding the protruding electrode to the terminal electrode of the wiring board in a state in which the terminal electrode of the wiring board is fitted in the concave portion on the surface of the protruding electrode.
JP2003308696A 2003-09-01 2003-09-01 Terminal electrode, semiconductor device, semiconductor module, electronic equipment, method of manufacturing terminal electrode, and method of manufacturing semiconductor module Withdrawn JP2005079379A (en)

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WO2012111722A1 (en) * 2011-02-18 2012-08-23 シャープ株式会社 Semiconductor chip and semiconductor device
JP2012227546A (en) * 2012-07-17 2012-11-15 Sharp Corp Semiconductor chip and semiconductor device
WO2014033977A1 (en) * 2012-08-29 2014-03-06 パナソニック株式会社 Semiconductor device
EP2738796A3 (en) * 2012-11-29 2014-11-05 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for producing a flip-chip structure for assembling microelectronic devices comprising an insulating block for guiding a connecting element and corresponding device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012111722A1 (en) * 2011-02-18 2012-08-23 シャープ株式会社 Semiconductor chip and semiconductor device
JP2012174803A (en) * 2011-02-18 2012-09-10 Sharp Corp Semiconductor chip and semiconductor device
JP2012227546A (en) * 2012-07-17 2012-11-15 Sharp Corp Semiconductor chip and semiconductor device
WO2014033977A1 (en) * 2012-08-29 2014-03-06 パナソニック株式会社 Semiconductor device
US9520381B2 (en) 2012-08-29 2016-12-13 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device for use in flip-chip bonding, which reduces lateral displacement
EP2738796A3 (en) * 2012-11-29 2014-11-05 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for producing a flip-chip structure for assembling microelectronic devices comprising an insulating block for guiding a connecting element and corresponding device
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