JP5050431B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5050431B2
JP5050431B2 JP2006198396A JP2006198396A JP5050431B2 JP 5050431 B2 JP5050431 B2 JP 5050431B2 JP 2006198396 A JP2006198396 A JP 2006198396A JP 2006198396 A JP2006198396 A JP 2006198396A JP 5050431 B2 JP5050431 B2 JP 5050431B2
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chip
electrode pad
semiconductor device
pad portion
semiconductor chip
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JP2008028108A (en
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吉弘 蒔田
哲理 青柳
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Sony Corp
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of miniaturizing a mounting substrate, while preventing the contamination of an electrode pad due to an underfill material. <P>SOLUTION: The semiconductor device 10 includes: a first semiconductor chip 11 as the mounting substrate where an electrode pad 14 is formed around a chip mounting region; a second semiconductor chip 12 mounted by flip chip on the chip mounting region; and the underfill material 15 injected between the first and second semiconductor chips 11, 12. The electrode pad 14 is formed as a dam for preventing the effluence of the underfill material 15. By the configuration, the first semiconductor chip 11 is miniaturized. Furthermore, the electrode pad 14 functions as the dam. Consequently, the effluence of the underfill material 15 is prevented on the surface of the electrode pad 14, so as to secure reliability in bonding concerning bonding wire. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、実装基板上に半導体チップがフリップチップ実装された、例えばチップオンチップ構造の半導体装置に関する。   The present invention relates to a semiconductor device having, for example, a chip-on-chip structure in which a semiconductor chip is flip-chip mounted on a mounting substrate.

近年、電子機器の高機能化や軽薄短小化の要求に伴って電子部品の高密度集積化や高密度実装化が進み、フリップチップ実装を用いたＭＣＭ（マルチチップモジュール）又はＳＩＰ（システムインパッケージ）タイプの半導体装置が主流になりつつある。この種の半導体装置の中には、インターポーザと称される実装基板に半導体チップをフリップチップ実装した、いわゆるＣＯＣ（チップオンチップ）構造の半導体装置が知られている（例えば下記特許文献１参照）。チップオンチップ構造の半導体装置は、多ピン化によるワイドバスを実現してデータ転送密度の向上を図ることができる。   In recent years, along with demands for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have progressed, and MCM (multi-chip module) or SIP (system-in-package) using flip chip mounting ) Type semiconductor devices are becoming mainstream. Among such semiconductor devices, a semiconductor device having a so-called COC (chip-on-chip) structure in which a semiconductor chip is flip-chip mounted on a mounting substrate called an interposer is known (see, for example, Patent Document 1 below). . A semiconductor device having a chip-on-chip structure can realize a wide bus by increasing the number of pins and improve data transfer density.

図８は従来のチップオンチップ構造の半導体装置の一製造工程を示す概略図であり、Ａは側断面図、Ｂは平面図である。この従来の半導体装置は、第１の半導体チップ１のチップ実装領域に、第２の半導体チップ２がはんだバンプ３を介してフリップチップ接合されて構成されている。第１の半導体チップ１は、チップ実装領域の外周側に電極パッド４が複数形成されている。電極パッド４は、図示しない配線基板に対してボンディングワイヤ等を介して電気的に接続される。   8A and 8B are schematic views showing a manufacturing process of a conventional semiconductor device having a chip-on-chip structure, in which A is a side sectional view and B is a plan view. In this conventional semiconductor device, a second semiconductor chip 2 is flip-chip bonded to a chip mounting region of a first semiconductor chip 1 via solder bumps 3. The first semiconductor chip 1 has a plurality of electrode pads 4 formed on the outer peripheral side of the chip mounting area. The electrode pad 4 is electrically connected to a wiring board (not shown) via a bonding wire or the like.

チップオンチップ実装技術は、多ピン、微細ピッチに対応した高精度実装技術であり、また、回路面への実装であることから層間絶縁膜に適用されている脆弱な低誘電率膜（Ｌｏｗ−ｋ）に対応した低ダメージフリップ実装技術である。そのため、第１，第２の半導体チップ１，２のフリップチップ接合には、はんだバンプ３を用いた溶融接合などが低ダメージ実装技術として採用されている。しかし、フリップチップ接合のみでは微小なバンプ３に応力が集中し、クラックなどによって接続不良を起こしてしまう。これを防止するため、図８に示すように、アンダーフィル材５と呼ばれる液状封止樹脂材をニードル６を用いて滴下し、上下チップ１，２間の狭い空隙内に毛細管現象を利用して浸透させた後、加熱硬化させることにより接続信頼性を向上させると同時に、チップ表面を湿度などの外部ストレスから保護している。   The chip-on-chip mounting technology is a high-precision mounting technology that supports multi-pin, fine pitch, and since it is mounted on a circuit surface, it is a fragile low dielectric constant film (Low−) applied to an interlayer insulating film. This is a low damage flip mounting technology corresponding to k). Therefore, for the flip chip bonding of the first and second semiconductor chips 1 and 2, fusion bonding using the solder bumps 3 is employed as a low damage mounting technique. However, with flip-chip bonding alone, stress concentrates on the minute bumps 3 and causes connection failure due to cracks or the like. In order to prevent this, as shown in FIG. 8, a liquid sealing resin material called an underfill material 5 is dropped using a needle 6, and a capillary phenomenon is used in a narrow gap between the upper and lower chips 1 and 2. After being infiltrated, the connection reliability is improved by heating and curing, and at the same time, the chip surface is protected from external stress such as humidity.

アンダーフィル材５の注入工程において、アンダーフィル材５による電極パッド４の汚染を防止するためにダム７が設けられている。ダム７は、第１の半導体チップ１のチップ実装領域と電極パッド４との間に環状に形成されており、チップ１，２間に注入されたアンダーフィル材５の電極パッド４側への流出を堰き止める機能を有している。   A dam 7 is provided in order to prevent contamination of the electrode pad 4 by the underfill material 5 in the injection process of the underfill material 5. The dam 7 is formed in an annular shape between the chip mounting region of the first semiconductor chip 1 and the electrode pad 4, and the underfill material 5 injected between the chips 1 and 2 flows out to the electrode pad 4 side. It has a function of blocking dams.

特開２００５−２７６８７９号公報JP 2005-276879 A

近年における半導体装置の小型化の要求を受けて、図８に示した構成の半導体装置においては、実装基板としての第１の半導体チップ１の更なる小型化が検討されている。この場合、第１の半導体チップ１の小型化によりアンダーフィル材５の滴下領域が狭くなるため、第１の半導体チップ１上に供給したアンダーフィル材５がダム７を乗り越えて電極パッド４を汚染するおそれが生じる。電極パッド４がアンダーフィル材５で汚染されてしまうと、電極パッド４に対するボンディングワイヤの接続信頼性が低下する。   In response to the recent demand for miniaturization of semiconductor devices, further miniaturization of the first semiconductor chip 1 as a mounting substrate has been studied in the semiconductor device having the configuration shown in FIG. In this case, since the dripping region of the underfill material 5 is narrowed by downsizing the first semiconductor chip 1, the underfill material 5 supplied onto the first semiconductor chip 1 gets over the dam 7 and contaminates the electrode pad 4. May occur. When the electrode pad 4 is contaminated with the underfill material 5, the connection reliability of the bonding wire to the electrode pad 4 is lowered.

また、アンダーフィル材５の注入に際しては、第２の半導体チップ２の周縁部とダム７との間の少なくとも一箇所にニードル６の先端径よりも大きな樹脂滴下領域を確保する必要があり、これに更にダム７の形成領域を確保するとなると、半導体装置の小型化が図れなくなる。   In addition, when the underfill material 5 is injected, it is necessary to secure a resin dripping region larger than the tip diameter of the needle 6 at least at one location between the peripheral edge of the second semiconductor chip 2 and the dam 7. In addition, if the formation area of the dam 7 is further secured, the semiconductor device cannot be reduced in size.

本発明は上述の問題に鑑みてなされ、アンダーフィル材による電極パッドの汚染を防止しつつ実装基板の小型化を図ることができる半導体装置を提供することを課題とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing the size of a mounting substrate while preventing contamination of an electrode pad by an underfill material.

以上の課題を解決するに当たり、本発明の半導体装置は、チップ実装領域の周囲に電極パッドが形成された実装基板と、チップ実装領域にフリップチップ実装された半導体チップと、実装基板と半導体チップとの間に注入されたアンダーフィル材とを備え、上記電極パッドは、アンダーフィル材の流出防止用のダムとして形成されている。   In solving the above problems, a semiconductor device of the present invention includes a mounting substrate in which an electrode pad is formed around a chip mounting region, a semiconductor chip flip-chip mounted in the chip mounting region, a mounting substrate and a semiconductor chip. The electrode pad is formed as a dam for preventing the underfill material from flowing out.

電極パッドをアンダーフィル材の流出防止用のダムとして形成することにより、チップ実装領域と電極パッドとの間に別途ダムを形成する必要がなくなるので、実装基板の小型化を図れるようになる。また、電極パッドがダムとして機能するので、電極パッドの表面をアンダーフィル材の汚染から防止して、ボンディングワイヤの接合信頼性を確保することができる。なお、ボンディングワイヤの代わりに、はんだ等の金属バンプを形成してもよい。   By forming the electrode pad as a dam for preventing the underfill material from flowing out, it is not necessary to separately form a dam between the chip mounting region and the electrode pad, so that the mounting substrate can be reduced in size. Further, since the electrode pad functions as a dam, the surface of the electrode pad can be prevented from being contaminated with the underfill material, and the bonding reliability of the bonding wire can be ensured. Note that metal bumps such as solder may be formed instead of the bonding wires.

本発明において、電極パッドをダムとして機能させるためには、電極パッドを実装基板のアンダーフィル材の塗布面よりも高く形成すればよい。具体的には、電極パッド４を構成するパッド部の上に端子部を形成したり、当該パッド部を厚く形成したり、当該パッド部に下地層を形成する等の方法を採用することができる。   In the present invention, in order for the electrode pad to function as a dam, the electrode pad may be formed higher than the application surface of the underfill material of the mounting substrate. Specifically, a method of forming a terminal part on the pad part constituting the electrode pad 4, forming the pad part thickly, or forming a base layer on the pad part can be employed. .

電極パッドは、上記半導体チップの接合温度で溶融しない、例えば金（Ａｕ）等の金属材料で形成することにより、アンダーフィル工程前の形状変化を防ぐことができる。また、電極パッドの内周側縁部にコーナー等のエッジ部が形成されていると、アンダーフィル材の流出を効果的に規制することができる。   By forming the electrode pad with a metal material such as gold (Au) that does not melt at the bonding temperature of the semiconductor chip, it is possible to prevent a shape change before the underfill process. Moreover, when edge parts, such as a corner, are formed in the inner peripheral side edge part of an electrode pad, the outflow of an underfill material can be controlled effectively.

本発明の半導体装置によれば、電極パッドをアンダーフィル材の流出防止用のダムとしても機能させるようにしているので、アンダーフィル材による電極パッドの汚染を防止しながら、半導体装置の小型化を実現することができる。   According to the semiconductor device of the present invention, since the electrode pad functions as a dam for preventing the underfill material from flowing out, the semiconductor device can be reduced in size while preventing the electrode pad from being contaminated by the underfill material. Can be realized.

以下、本発明の各実施形態について図面を参照して説明する。なお、本発明は以下の各実施形態に限定されることはなく、本発明の技術的思想に基づいて種々の変形が可能である。   Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the following embodiments, and various modifications can be made based on the technical idea of the present invention.

（第１の実施形態）
図１Ａ，Ｂは、本発明の第１の実施形態を示しており、Ａは、半導体装置１０の一製造工程であるアンダーフィル注入工程を示す概略断面図、Ｂは、配線基板に対する半導体装置１０の一実装形態を示す概略断面図である。 (First embodiment)
1A and 1B show a first embodiment of the present invention, in which A is a schematic cross-sectional view showing an underfill injection process which is one manufacturing process of the semiconductor device 10, and B is a semiconductor device 10 for a wiring board. It is a schematic sectional drawing which shows one mounting form.

本実施形態の半導体装置１０は、実装基板としての第１の半導体チップ１１と、この第１の半導体チップ１１の上に実装された第２の半導体チップ１２とで構成されている。第１の半導体チップ１１は、第２の半導体チップ１２よりも大型の半導体チップで構成されている。なお、第１の半導体チップ１１は、シリコンインターポーザ等の回路基板で構成されていてもよい。   The semiconductor device 10 according to the present embodiment includes a first semiconductor chip 11 as a mounting substrate, and a second semiconductor chip 12 mounted on the first semiconductor chip 11. The first semiconductor chip 11 is composed of a semiconductor chip larger than the second semiconductor chip 12. The first semiconductor chip 11 may be composed of a circuit board such as a silicon interposer.

第２の半導体チップ１２は、第１の半導体チップ１１の主面のほぼ中央部のチップ実装領域上に複数のはんだバンプ１３を介してフリップチップ実装されている。第１の半導体チップ１１のチップ実装領域の外周位置には、複数の電極パッド１４が形成されている。本実施形態において、電極パッド１４は、第１の半導体チップ１１の表面に形成されたパッド部２２と、パッド部２２の上に積層された端子部１７とを備えている。   The second semiconductor chip 12 is flip-chip mounted via a plurality of solder bumps 13 on a chip mounting region at a substantially central portion of the main surface of the first semiconductor chip 11. A plurality of electrode pads 14 are formed at the outer peripheral position of the chip mounting region of the first semiconductor chip 11. In the present embodiment, the electrode pad 14 includes a pad portion 22 formed on the surface of the first semiconductor chip 11 and a terminal portion 17 stacked on the pad portion 22.

第１の半導体チップ１１と第２の半導体チップ１２との間は、アンダーフィル材１５が充填されている。アンダーフィル材１５は、はんだバンプ１３による接合部を外気湿度や外部ストレスから保護するための補強層であり、エポキシ系等の合成樹脂材料で形成されている。アンダーフィル材１５は、図１Ａに示すように、第２の半導体チップ１２の一周縁部と電極パッド１４との間の領域に配置されたニードル１６の先端から第１の半導体チップ１１上に滴下され、毛細管現象により第１，第２の半導体チップ１１，１２間に浸透し、その後、加熱硬化される。なお、アンダーフィル材１５としては、表面張力が硬化温度以下で例えば２５ｍＮ／ｍ以上がよい。   An underfill material 15 is filled between the first semiconductor chip 11 and the second semiconductor chip 12. The underfill material 15 is a reinforcing layer for protecting the joint portion by the solder bump 13 from outside air humidity and external stress, and is formed of a synthetic resin material such as epoxy. As shown in FIG. 1A, the underfill material 15 is dropped onto the first semiconductor chip 11 from the tip of the needle 16 disposed in the region between the one peripheral edge portion of the second semiconductor chip 12 and the electrode pad 14. Then, it penetrates between the first and second semiconductor chips 11 and 12 by capillary action, and is then heat-cured. The underfill material 15 preferably has a surface tension of not more than the curing temperature and, for example, 25 mN / m or more.

本実施形態では、電極パッド１４は、パッド部２２と端子部１７の積層構造で構成されることにより、第１の半導体チップ１１のアンダーフィル塗布面１１Ｓよりも高く形成されている。このような構成により、第１の半導体チップ１１上の各電極パッド１４は、アンダーフィル材１５の流出防止用のダムとして形成される。なお、アンダーフィル塗布面１１Ｓに対する電極パッド１４の高さは特に制限されないが、例えば１７μｍとされる。   In the present embodiment, the electrode pad 14 is formed to be higher than the underfill application surface 11 </ b> S of the first semiconductor chip 11 by being configured by a laminated structure of the pad portion 22 and the terminal portion 17. With such a configuration, each electrode pad 14 on the first semiconductor chip 11 is formed as a dam for preventing the underfill material 15 from flowing out. The height of the electrode pad 14 with respect to the underfill application surface 11S is not particularly limited, but is set to 17 μm, for example.

半導体装置１０は、接着材料層１９を介して配線基板１８に接合される。そして、半導体装置１０の電極パッド１４（端子部１７）と配線基板１８のランド部２０との間にボンディングワイヤ２１が接続されることによって、半導体装置１０と配線基板１８との間の電気的接続が行われている。なお、ボンディングワイヤ２１の代わりに、はんだ等の金属バンプを電極パッド１４上に形成し、当該金属バンプを介して配線基板上に実装するようにしてもよい。   The semiconductor device 10 is bonded to the wiring substrate 18 via the adhesive material layer 19. Then, the bonding wire 21 is connected between the electrode pad 14 (terminal portion 17) of the semiconductor device 10 and the land portion 20 of the wiring substrate 18, so that electrical connection between the semiconductor device 10 and the wiring substrate 18 is achieved. Has been done. Instead of the bonding wires 21, metal bumps such as solder may be formed on the electrode pads 14 and mounted on the wiring board via the metal bumps.

本実施形態によれば、電極パッド１４をアンダーフィル材１５の流出防止用のダムとして形成しているので、チップ実装領域と電極パッドとの間に従来設置されていたダムの形成が不要となり、これにより第１の半導体チップ１１の小型化を図ることが可能となり、設計自由度を増すことができる。また、電極パッド１４がダムとして機能するので、電極パッド１４の表面をアンダーフィル材１５の汚染から防止して、ボンディングワイヤ２１の接合信頼性を確保することができる。   According to this embodiment, since the electrode pad 14 is formed as a dam for preventing the underfill material 15 from flowing out, it is not necessary to form a dam that has been conventionally installed between the chip mounting region and the electrode pad. This makes it possible to reduce the size of the first semiconductor chip 11 and increase the degree of design freedom. Moreover, since the electrode pad 14 functions as a dam, the surface of the electrode pad 14 can be prevented from being contaminated by the underfill material 15 and the bonding reliability of the bonding wire 21 can be ensured.

ここで、電極パッド１４を構成する端子部１７は、その内周側縁部に屈曲したコーナー状のエッジ部１７ｅを形成することで、アンダーフィル材１５の流出を効果的に規制することができる。このような端子部１７の形状加工は、めっきレジストを用いた選択めっき法によって得ることができる。   Here, the terminal part 17 which comprises the electrode pad 14 can control the outflow of the underfill material 15 by forming the curved edge part 17e in the inner peripheral side edge part. . Such shape processing of the terminal portion 17 can be obtained by a selective plating method using a plating resist.

また、電極パッド１４を構成する端子部１７及びパッド部２２は、チップ実装領域に対する第２の半導体チップ１２の接合温度で溶融しない金属材料で形成される。本実施形態では、はんだバンプ１３はＳｎ（すず）−Ａｇ（銀）系はんだであり、その接合温度（リフロー温度）は例えば２２０℃〜２３０℃である。そして、端子部１７は金（Ａｕ）めっき、パッド部２２はアルミニウム（Ａｌ）系材料で構成される。これにより、半導体チップ１２の接合時における電極パッド１４の形状変化を防止でき、ダム機能の確保を図ることができる。   Further, the terminal portion 17 and the pad portion 22 constituting the electrode pad 14 are formed of a metal material that does not melt at the bonding temperature of the second semiconductor chip 12 with respect to the chip mounting region. In the present embodiment, the solder bump 13 is Sn (tin) -Ag (silver) solder, and the bonding temperature (reflow temperature) is, for example, 220 ° C. to 230 ° C. The terminal portion 17 is made of gold (Au) plating, and the pad portion 22 is made of an aluminum (Al) -based material. Thereby, the shape change of the electrode pad 14 at the time of joining of the semiconductor chip 12 can be prevented, and a dam function can be ensured.

次に、上述した本発明の第１の実施形態の半導体装置１０を構成する第１の半導体チップ１１の製造方法について説明する。図２〜図５はその製造方法を説明する要部の工程断面図である。   Next, a method for manufacturing the first semiconductor chip 11 constituting the semiconductor device 10 according to the first embodiment of the present invention described above will be described. 2 to 5 are process cross-sectional views of the main part for explaining the manufacturing method.

まず、図２（Ａ）に示すように、第１の半導体チップ１１を構成する基板３１の能動面（チップ実装面）に、バンプ形成用のパッド部３２と、ワイヤボンディング用のパッド部２２を形成するとともに、これらパッド部を被覆する保護層３３を形成する。各パッド部２２，３２は、基板３１の表面に引き回し形成されたアルミニウム配線パターンの末端部に形成され、保護層３３の各パッド部に対応する領域には開口が形成されている。   First, as shown in FIG. 2A, bump forming pad portions 32 and wire bonding pad portions 22 are formed on the active surface (chip mounting surface) of the substrate 31 constituting the first semiconductor chip 11. While forming, the protective layer 33 which coat | covers these pad parts is formed. Each of the pad portions 22 and 32 is formed at an end portion of an aluminum wiring pattern formed around the surface of the substrate 31, and an opening is formed in a region corresponding to each pad portion of the protective layer 33.

次に、図２（Ｂ）及び図２（Ｃ）に示すように、基板３１の表面全域にバリアメタルとしてＴｉ（チタン）層３４とＣｕ（銅）層３５をスパッタ法によって順に積層形成する。そして、図２（Ｄ）に示すように、基板３１の表面に感光性レジスト膜３６をコーティングする。そして、図２（Ｅ）及び図３（Ｆ）に示すように、レジスト膜３６に対し、マスク３７を介しての露光と現像処理を施すことにより、バンプ形成用パッド部３２の形成領域のみ開口したレジストパターン３６Ｐを形成する。なお、感光性レジスト膜３６はポジ型を用いたが、ネガ型を用いても構わない。   Next, as shown in FIGS. 2B and 2C, a Ti (titanium) layer 34 and a Cu (copper) layer 35 are sequentially stacked over the entire surface of the substrate 31 as a barrier metal by a sputtering method. Then, as shown in FIG. 2D, a photosensitive resist film 36 is coated on the surface of the substrate 31. Then, as shown in FIGS. 2E and 3F, the resist film 36 is exposed and developed through a mask 37 so that only the formation region of the bump forming pad portion 32 is opened. The resist pattern 36P thus formed is formed. In addition, although the positive type was used for the photosensitive resist film 36, a negative type may be used.

続いて、図３（Ｇ）に示すように、レジストパターン３６Ｐの開口部から露出するバンプ形成用パッド部３２の直上に、バリアメタル層３４，３５をシード層（給電層）としてＮｉ（ニッケル）層３８を電気めっき法により形成する。Ｎｉ層３８の形成後、このＮｉ層３８の上に、図３（Ｈ）に示すように、はんだめっき層１３Ａを電気めっき法により形成する。   Subsequently, as shown in FIG. 3G, Ni (nickel) is formed with barrier metal layers 34 and 35 as seed layers (feeding layers) immediately above the bump forming pad portions 32 exposed from the openings of the resist pattern 36P. Layer 38 is formed by electroplating. After the formation of the Ni layer 38, a solder plating layer 13A is formed on the Ni layer 38 by electroplating as shown in FIG.

次に、図３（Ｉ）及び図３（Ｊ）に示すように、レジストパターン３６Ｐを除去した後、基板３１上に電極パッド形成用の感光性レジスト膜３９を形成する。そして、図４（Ｋ）及び図４（Ｌ）に示すように、レジスト膜３９に対し、マスク４０を介しての露光と現像処理を施すことにより、ワイヤボンディング用パッド部２２の形成領域のみ開口したレジストパターン３９Ｐを形成する。なお、この例においても感光性レジスト膜３６にポジ型を用いたが、ネガ型を用いても構わない。   Next, as shown in FIGS. 3I and 3J, after removing the resist pattern 36P, a photosensitive resist film 39 for forming an electrode pad is formed on the substrate 31. Next, as shown in FIG. Then, as shown in FIGS. 4K and 4L, the resist film 39 is exposed and developed through the mask 40 so that only the formation region of the wire bonding pad portion 22 is opened. The resist pattern 39P thus formed is formed. In this example, the positive type is used for the photosensitive resist film 36, but a negative type may be used.

続いて、図４（Ｍ）に示すように、レジストパターン３９Ｐの開口部から露出するワイヤボンディング用パッド部２２の直上に、バリアメタル層３４，３５をシード層として、Ｎｉ層４１を電気めっき法により形成する。Ｎｉ層４１の形成後、このＮｉ層４１の上に、図４（Ｎ）に示すように、Ａｕ（金）めっき層からなる端子部１７を電気めっき法により形成する。   Subsequently, as shown in FIG. 4M, the Ni layer 41 is electroplated using the barrier metal layers 34 and 35 as a seed layer directly on the wire bonding pad portion 22 exposed from the opening of the resist pattern 39P. To form. After the Ni layer 41 is formed, a terminal portion 17 made of an Au (gold) plating layer is formed on the Ni layer 41 by electroplating as shown in FIG.

次に、図４（Ｏ）に示すように、レジストパターン３９Ｐを除去する。そして、図５（Ｐ）及び図５（Ｑ）に示すように、バリアメタル層としてのＣｕ層３５及びＴｉ層３４を順にエッチング除去する。これらＣｕ層３５及びＴｉ層３４の除去工程では、Ｎｉ層３８，４１をマスクとしたウェットエッチング法によって行われる。   Next, as shown in FIG. 4O, the resist pattern 39P is removed. Then, as shown in FIGS. 5 (P) and 5 (Q), the Cu layer 35 and the Ti layer 34 as the barrier metal layer are removed by etching in order. The removal process of the Cu layer 35 and the Ti layer 34 is performed by a wet etching method using the Ni layers 38 and 41 as a mask.

次に、図５（Ｒ）に示すように、基板３１の表面にフラックス４２を塗布形成する。そして、図５（Ｓ）に示すように、基板３１をはんだめっき層１３Ａのリフロー温度に加熱して、バンプ形成用パッド部３２上にはんだバンプ１３を形成する。このとき、ワイヤボンディング用パッド部２２上の端子部１４は、はんだめっき層１３Ａのリフロー温度より高い融点をもつＡｕめっきで形成されているので、端子部１４の形状変化は生じない。その後、図５（Ｔ）に示すように、フラックス４２を洗浄除去する。   Next, as shown in FIG. 5 (R), a flux 42 is applied and formed on the surface of the substrate 31. Then, as shown in FIG. 5 (S), the substrate 31 is heated to the reflow temperature of the solder plating layer 13 </ b> A to form the solder bumps 13 on the bump forming pad portions 32. At this time, since the terminal portion 14 on the wire bonding pad portion 22 is formed by Au plating having a melting point higher than the reflow temperature of the solder plating layer 13A, the shape of the terminal portion 14 does not change. Thereafter, as shown in FIG. 5 (T), the flux 42 is washed away.

以上のようにして、アンダーフィル材の流出防止用のダムを兼ねた、ワイヤボンディング用の電極パッド１４を備えた第１の半導体チップ１１が作製される。   As described above, the first semiconductor chip 11 including the electrode pads 14 for wire bonding, which also serves as a dam for preventing the underfill material from flowing out, is manufactured.

（第２の実施形態）
次に、本発明の第２の実施形態について説明する。上述の第１の実施形態においては、ワイヤボンディング用のパッド部２２上に端子部１７を突出形成することで、ダムを兼ねた電極パッド１４を構成したが、本実施形態では、上記パッド部を当初より厚手に形成してダムを兼ねる電極パッドを構成するようにしている。図６は、本実施形態における電極パッド４４の製造方法を説明する要部の工程断面図である。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the electrode pad 14 that also serves as a dam is configured by protrudingly forming the terminal portion 17 on the wire bonding pad portion 22. The electrode pad is formed thicker than the beginning and also serves as a dam. FIG. 6 is a process cross-sectional view of the main part for explaining the method of manufacturing the electrode pad 44 in the present embodiment.

まず、図６（Ａ）に示すように、第１の半導体チップ１１を構成する基板３１の表面にＡｌ配線層４５Ａを形成した後、図６（Ｂ）に示すように、Ａｌ配線層をパターンエッチングして電極パッド４４の形成領域にパッド部４４Ａを形成する。次に、図６（Ｃ）及び図６（Ｄ）に示すように、基板３１の表面にＡｌ配線層４５Ａと同種のＡｌ配線層４５Ｂを形成した後、パターンエッチングすることで、ワイヤボンディング用のパッド部４４Ｂとともに、バンプ形成用パッド部３２を形成する。これにより、ワイヤボンディング用パッド部４４Ｂは、バンプ形成用パッド部３２よりも厚く形成されることになる。最後に、図６（Ｅ）に示すように、基板３１の表面に保護膜３３を形成し、パッド部４４（３２）の形成領域を開口させることで、本発明に係る電極パッド４４が形成される。   First, as shown in FIG. 6A, after an Al wiring layer 45A is formed on the surface of the substrate 31 constituting the first semiconductor chip 11, the Al wiring layer is patterned as shown in FIG. 6B. Etching forms a pad portion 44 </ b> A in the formation region of the electrode pad 44. Next, as shown in FIGS. 6C and 6D, an Al wiring layer 45B of the same type as the Al wiring layer 45A is formed on the surface of the substrate 31, and then pattern etching is performed, thereby performing wire bonding. A bump forming pad portion 32 is formed together with the pad portion 44B. Thus, the wire bonding pad portion 44B is formed to be thicker than the bump forming pad portion 32. Finally, as shown in FIG. 6E, the protective film 33 is formed on the surface of the substrate 31, and the formation region of the pad portion 44 (32) is opened, whereby the electrode pad 44 according to the present invention is formed. The

本実施形態によれば、電極パッド４４を構成するパッド部４４Ｂがバンプ形成用パッド部３２よりも厚く形成されることにより、電極パッド４４のアンダーフィル塗布面１１Ｓからの形成高さを大きくすることができるので、電極パッド４４に対してアンダーフィル材の流出を防止させるダム機能を付与することができる。また、パッド部４４Ｂを被覆する保護層３３の内周縁部にエッジ部３３ｅを設けることで、当該電極パッド４４によるアンダーフィル材の流出防止機能を更に高めることができるようになる。   According to the present embodiment, the pad portion 44B constituting the electrode pad 44 is formed thicker than the bump forming pad portion 32, thereby increasing the formation height of the electrode pad 44 from the underfill coating surface 11S. Therefore, a dam function for preventing the underfill material from flowing out to the electrode pad 44 can be provided. Further, by providing the edge portion 33e on the inner peripheral edge portion of the protective layer 33 covering the pad portion 44B, the function of preventing the underfill material from flowing out by the electrode pad 44 can be further enhanced.

（第３の実施形態）
次に、本発明の第３の実施形態について説明する。本実施形態では、ワイヤボンディング用のパッド部を下地層を介して形成することにより、アンダーフィル材の流出防止用ダムを兼ねる電極パッド５４を構成するようにしている。図７は、本実施形態における電極パッド５４の製造方法を説明する要部の工程断面図である。 (Third embodiment)
Next, a third embodiment of the present invention will be described. In the present embodiment, an electrode pad 54 that also serves as an underfill material outflow prevention dam is formed by forming a wire bonding pad portion through an underlayer. FIG. 7 is a process cross-sectional view of the main part for explaining the method for manufacturing the electrode pad 54 in the present embodiment.

まず、図７（Ａ）に示すように、第１の半導体チップ１１を構成する基板３１上に絶縁膜５１を形成した後、図７（Ｂ）に示すように、絶縁層５１をパターンエッチングして電極パッド５４の形成領域に下地層５１Ａを形成する。下地層５１Ａを形成する絶縁材料は特に限定されず、例えばＳｉＯ2 膜が用いられる。次に、図７（Ｃ）及び図７（Ｄ）に示すように、基板３１の表面にＡｌ配線層４５を形成した後、パターンエッチングすることで、ワイヤボンディング用のパッド部２２とともに、バンプ形成用パッド部３２を形成する。これにより、ワイヤボンディング用パッド部２２は、バンプ形成用パッド部３２よりも厚く形成されることになる。最後に、図７（Ｅ）に示すように、基板３１の表面に保護膜３３を形成し、パッド部４４（３２）の形成領域を開口させることで、本発明に係る電極パッド５４が形成される。 First, as shown in FIG. 7A, an insulating film 51 is formed on a substrate 31 constituting the first semiconductor chip 11, and then the insulating layer 51 is subjected to pattern etching as shown in FIG. 7B. Then, a base layer 51A is formed in the formation region of the electrode pad 54. The insulating material for forming the base layer 51A is not particularly limited, and for example, a SiO 2 film is used. Next, as shown in FIGS. 7C and 7D, after forming an Al wiring layer 45 on the surface of the substrate 31, pattern etching is performed to form bumps together with the pad portion 22 for wire bonding. The pad portion 32 is formed. As a result, the wire bonding pad portion 22 is formed to be thicker than the bump forming pad portion 32. Finally, as shown in FIG. 7E, the protective film 33 is formed on the surface of the substrate 31, and the formation region of the pad portion 44 (32) is opened, whereby the electrode pad 54 according to the present invention is formed. The

本発明の第１の実施形態による半導体装置の構成を示す概略断面図であり、Ａはアンダーフィル注入工程を示し、Ｂは配線基板への一実装形態を示している。It is a schematic sectional drawing which shows the structure of the semiconductor device by the 1st Embodiment of this invention, A shows the underfill injection | pouring process, B shows the one mounting form to a wiring board. 図１に示した半導体装置における第１の半導体チップの一製造方法を説明する要部の工程断面図である。FIG. 6 is a process cross-sectional view of the main part for explaining a method of manufacturing the first semiconductor chip in the semiconductor device shown in FIG. 1. 図１に示した半導体装置における第１の半導体チップの一製造方法を説明する要部の工程断面図である。FIG. 6 is a process cross-sectional view of the main part for explaining a method of manufacturing the first semiconductor chip in the semiconductor device shown in FIG. 1. 図１に示した半導体装置における第１の半導体チップの一製造方法を説明する要部の工程断面図である。FIG. 6 is a process cross-sectional view of the main part for explaining a method of manufacturing the first semiconductor chip in the semiconductor device shown in FIG. 1. 図１に示した半導体装置における第１の半導体チップの一製造方法を説明する要部の工程断面図である。FIG. 6 is a process cross-sectional view of the main part for explaining a method of manufacturing the first semiconductor chip in the semiconductor device shown in FIG. 1. 本発明の第２の実施形態による半導体装置の電極パッドの製造方法を説明する要部の工程断面図である。It is process sectional drawing of the principal part explaining the manufacturing method of the electrode pad of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第３の実施形態による半導体装置の電極パッドの製造方法を説明する要部の工程断面図である。It is process sectional drawing of the principal part explaining the manufacturing method of the electrode pad of the semiconductor device by the 3rd Embodiment of this invention. 従来の半導体装置のアンダーフィル注入工程を示す概略断面図であり、Ａは側断面図、Ｂは平面図である。It is a schematic sectional drawing which shows the underfill injection | pouring process of the conventional semiconductor device, A is a sectional side view, B is a top view.

符号の説明Explanation of symbols

１０…半導体装置、１１…第１の半導体チップ（実装基板）、１２…第２の半導体チップ、１３…はんだバンプ、１４、４４，５４…電極パッド、１５…アンダーフィル材、１６…ニードル、１７…端子部、１８…配線基板、２１…ボンディングワイヤ、２２…パッド部、３１…基板、３２…バンプ形成用パッド部、３３…保護膜   DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... 1st semiconductor chip (mounting substrate), 12 ... 2nd semiconductor chip, 13 ... Solder bump, 14, 44, 54 ... Electrode pad, 15 ... Underfill material, 16 ... Needle, 17 ... Terminal part, 18 ... Wiring substrate, 21 ... Bonding wire, 22 ... Pad part, 31 ... Substrate, 32 ... Pad part for bump formation, 33 ... Protective film

Claims (5)

表面と、前記表面上のチップ実装領域に第１の高さで形成されたアルミニウム製の第１のパッド部と、前記チップ実装領域の周囲に前記第１の高さよりも高い第２の高さで形成されたアルミニウム製の第２のパッド部と、を有する実装基板と、
前記第１のパッド部を介して前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に注入されたアンダーフィル材と、
前記表面と前記第１のパッド部および前記第２のパッド部の周縁とを被覆し、前記第２のパッド部の前記チップ実装領域側の縁部に前記アンダーフィル材の流出防止用のエッジ部を有する保護膜と、
を具備する半導体装置。 A surface, a first pad portion made of aluminum formed at a first height in a chip mounting region on the surface, and a second height higher than the first height around the chip mounting region A mounting board having a second pad portion made of aluminum formed by :
A semiconductor chip flip-chip mounted on the chip mounting region via the first pad portion ;
An underfill material injected between the mounting substrate and the semiconductor chip ;
An edge portion for covering the surface and the peripheral edges of the first pad portion and the second pad portion, and for preventing the underfill material from flowing out to an edge portion of the second pad portion on the chip mounting region side A protective film having
A semiconductor device comprising: 請求項１に記載の半導体装置であって、
前記実装基板は、半導体チップである
半導体装置。 The semiconductor device according to claim 1,
The mounting substrate is a semiconductor chip. 請求項１に記載の半導体装置であって、
前記第２のパッド部には、ボンディングワイヤが接続されている
半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein a bonding wire is connected to the second pad portion . 請求項１に記載の半導体装置であって、
前記第２のパッド部には、はんだバンプが形成されている
半導体装置。 The semiconductor device according to claim 1,
Solder bumps are formed on the second pad portion . Semiconductor device. 実装基板上のチップ実装領域に第１の高さを有するアルミニウム製の第１のパッド部を形成し、前記チップ実装領域の周囲に前記第１の高さよりも高い第２の高さを有するアルミニウム製の第２のパッド部を形成し、An aluminum first pad portion having a first height is formed in a chip mounting area on the mounting substrate, and an aluminum having a second height higher than the first height is formed around the chip mounting area. Forming a second pad portion made of
前記実装基板上に、前記第１のパッド部および前記第２のパッド部の周縁を被覆する保護膜を形成し、  Forming a protective film covering the periphery of the first pad portion and the second pad portion on the mounting substrate;
前記第１のパッド部を介して前記チップ実装領域に半導体チップをフリップチップ実装し、  A semiconductor chip is flip-chip mounted on the chip mounting region via the first pad portion,
前記実装基板と前記半導体チップとの間にアンダーフィル材を注入する  An underfill material is injected between the mounting substrate and the semiconductor chip.
半導体装置の製造方法。  A method for manufacturing a semiconductor device.
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