CN110596439A - Digital trigger detection method - Google Patents
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
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- G01R13/0254—Circuits therefor for triggering, synchronisation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/029—Software therefor
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Abstract
The invention discloses a digital trigger detection method, which adopts a high-speed gigabit transceiver in FPGA to sample and deserialize a trigger comparator output signal (trigger signal) and output parallel trigger data; and carrying out state judgment on the parallel trigger signals in the FPGA, and identifying the position of state jump so as to determine the position of the trigger point in the parallel data acquisition. The gigabit transceiver is set to have the same multiplying power as the ADC frequency dividing ratio for serial-to-parallel conversion, and the speed is reduced to the speed at which FGAP can stably work, so that parallel trigger data and parallel sampling data of a signal to be tested have one-to-one correspondence, and a trigger jumping point identified in the parallel trigger data is the accurate position of signal triggering, thereby solving the problems that a high-speed trigger signal of the digital storage oscilloscope cannot be input into the FPGA, the trigger signal cannot be accurately positioned in the data collected by the parallel ADC, and the like, and realizing the triggering synchronization of the high-speed parallel sampling digital storage oscilloscope.
Description
Technical Field
The invention belongs to the technical field of trigger identification of digital storage oscilloscopes, and particularly relates to a digital trigger detection method, namely a method capable of accurately detecting the rising edge and the falling edge of a trigger signal in high-speed parallel sampling data, which is used for trigger identification of a digital storage oscilloscope with a trigger function.
Background
Trigger recognition is an important means for displaying a stable waveform and acquiring a signal of interest in a digital storage oscilloscope. The acquisition triggering principle of the traditional digital storage oscilloscope is shown in fig. 1, a measured signal is acquired by an analog-to-digital converter, and acquired data is output and flows to a field programmable logic device (FPGA). The trigger signal is usually generated by comparing a detected signal or an external trigger signal through a trigger comparator, and enters the FPGA for trigger identification: and converting into logic '0' or '1', if the trigger is a rising edge trigger and the pre-trigger condition is met, when the logic '0' is changed into logic '1', the trigger is regarded as a trigger, and the storage of the acquired data stream is controlled.
Because the ADC of the high-speed digital storage oscilloscope is high in data flow rate, in order to enable the FPGA to work stably, the acquired data generally needs to be processed in a de-serializing and speed-reducing mode, namely one sampling clock corresponds to a plurality of sampling data points, and specific points in the plurality of sampling data points in parallel cannot be detected to be trigger points. In addition, for the high-speed digital storage oscilloscope, because the frequency of the trigger signal is also very high, the comparison output signal cannot enter the FPGA, and if the trigger signal frequency division processing is adopted, the accidental trigger event cannot be captured.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a digital trigger detection method for accurately detecting (identifying) a trigger position.
In order to achieve the above object, the digital trigger detection method of the present invention is characterized by comprising the following steps:
(1) sampling and serial-parallel conversion (deserializing) are carried out on an output signal (trigger signal) of a trigger comparator by adopting a high-speed gigabit transceiver in the FPGA, and parallel trigger data are output, wherein the sampling rate of the gigabit transceiver is the same as that of the ADC, and the deserializing proportion of the gigabit transceiver is the same as the output frequency dividing ratio N of the ADC (deserializing proportion of the FPGA to the collected data);
the parallel trigger data output by the gigabit transceiver is in a group of N, one group corresponds to one output clock cycle and is synchronous with the parallel acquisition data output by the ADC (the ADC outputs a group of acquisition parallel data, and the gigabit transceiver also outputs a group of trigger parallel data);
(2) designing a trigger data state detection circuit, wherein the trigger data state detection circuit comprises a rising edge trigger detection module and a falling edge trigger detection module, and parallel trigger data are simultaneously input into the rising edge trigger detection module and the falling edge trigger detection module;
in the rising edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '0' to '1', the parallel trigger data is regarded as rising edge trigger, a trigger mark trigr is set from 0 to '1', the position posr of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
in a falling edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has the first change from '1' to '0', the parallel trigger data is regarded as falling edge trigger, a trigger mark trigf is set to '1' from 0, the position posf of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
(3) selecting a trigger mark trigr and a position posr output by a rising edge trigger detection module or a trigger mark trigf and a position posf output by a falling edge trigger detection module as a system trigger state Trig and a trigger position flag through an edge selection signal Trig _ sel according to the trigger edge setting condition of the digital storage oscilloscope;
the digital storage oscilloscope trigger storage control circuit latches the storage address of the parallel acquisition data by using the change of the system trigger state trig from '0' to '1', and then determines the corresponding trigger point of the trigger position in the address by the trigger position flag to realize the position of the trigger point in the parallel acquisition data.
The invention aims to realize the following steps:
the invention discloses a digital trigger detection method, which adopts a high-speed gigabit transceiver in an FPGA to sample and deserialize a trigger comparator output signal (trigger signal) and output parallel trigger data; and carrying out state judgment on the parallel trigger signals in the FPGA, and identifying the position of state jump so as to determine the position of the trigger point in the parallel data acquisition. The method comprises the steps of setting the same multiplying power as the ADC frequency dividing ratio for serial-to-parallel conversion on a gigabit transceiver, and reducing the speed to the speed at which FGAP can stably work, so that parallel trigger data and parallel sampling data of a signal to be tested have one-to-one correspondence, and a trigger jumping point identified in the parallel trigger data is the accurate position of signal triggering, thereby solving the problems that a high-speed trigger signal of a digital storage oscilloscope cannot be input into an FPGA (field programmable gate array), the trigger signal cannot be accurately positioned in the data collected by the parallel ADC, and the like.
Has the advantages that: the invention solves the problems that a high-speed trigger comparison output FPGA in a digital storage oscilloscope cannot receive and parallel sampling data are difficult to accurately position, and the digital trigger detection method based on sampling deserialization of the FPGA high-speed gigabit transceiver provided by the invention has the characteristics of simple circuit and high trigger positioning precision, and can be effectively applied to trigger synchronization in the digital storage oscilloscope.
Drawings
FIG. 1 is a schematic block diagram of a conventional oscilloscope trigger circuit;
FIG. 2 is a flow chart of one embodiment of a digital trigger detection method of the present invention;
FIG. 3 is a functional block diagram of trigger signal acquisition and serial-to-parallel conversion (deserialization);
FIG. 4 is a diagram of the correspondence between ADC sample values and trigger signal deserialization outputs;
FIG. 5 is a functional block diagram of trigger state detection;
FIG. 6 is a simulation of the digital trigger detection method of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
The invention provides a trigger identification method of a high-speed gigabit transceiver in an FPGA (field programmable gate array) in order to solve the problem of high-speed trigger signal identification in a digital storage oscilloscope. The method is suitable for trigger identification in parallel sampling data of a high-speed and high-sampling-rate digital storage oscilloscope. The invention adopts the gigabit transceiver of the FPGA to receive and sample the trigger comparison output signal (trigger signal), and the speed of the high-speed transceiver can reach more than 20 GHz. The sampling rate of the gigabit transceiver is set to be consistent with that of the ADC, the deserializing multiplying power of the gigabit transceiver is consistent with that of the ADC sampling data, and accurate triggering, positioning and detection of one sampling point can be realized through logical judgment of the state of triggering deserializing output.
Specifically, the digital trigger detection method of the present invention is shown in fig. 1, and includes the following steps:
step S1: sampling and deserializing a trigger signal
Sampling and serial-parallel conversion (deserializing) are carried out on an output signal (trigger signal) of a trigger comparator by adopting a high-speed gigabit transceiver in the FPGA, and parallel trigger data are output, wherein the sampling rate of the gigabit transceiver is the same as that of the ADC, and the deserializing proportion of the gigabit transceiver is the same as the output frequency dividing ratio N of the ADC (deserializing proportion of the FPGA to the acquired data);
the output parallel trigger data of the gigabit transceiver is a group of N, one group corresponds to one output clock cycle, and is synchronous with the parallel acquisition data output by the ADC (the ADC outputs a group of acquisition parallel data, and the gigabit transceiver also outputs a group of trigger parallel data).
In this embodiment, the sampling and serial-to-parallel conversion of the trigger signal by the high-speed gigabit transceiver is shown in fig. 3. The input of the gigabit transceiver is a trigger comparator output of a trigger channel, namely a trigger signal, and the trigger signal is input to the high speed in the FPGA through a high speed transceiver pin of the FPGAA gigabit transceiver. Setting the sampling rate f of a high-speed gigabit transceivers. In order to ensure that the parallel trigger data corresponds to the parallel sampling data output by the ADC one by one, the sampling rate fsThe same sampling rate as the ADC is set. According to the frequency dividing ratio output by the ADC and the deserializing ratio of the interior of the FPGA to the sampling data, the deserializing ratio of the gigabit transceiver is set, so that the deserializing ratio of the trigger signal is the same as the total frequency dividing ratio from the ADC sampling data to the deserializing output by the FPGAoThen there is fo＝fs/8. The output parallel trigger data of the gigabit transceiver is a group of 8, and one group corresponds to one output clock period.
Step S2: triggering and trigger position detection of parallel trigger data
Designing a trigger data state detection circuit, wherein the trigger data state detection circuit comprises a rising edge trigger detection module and a falling edge trigger detection module, and parallel trigger data are simultaneously input into the rising edge trigger detection module and the falling edge trigger detection module;
in the rising edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '0' to '1', the parallel trigger data is regarded as rising edge trigger, a trigger mark trigr is set from 0 to '1', the position posr of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
in the falling edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '1' to '0', the parallel trigger data is regarded as falling edge trigger, a trigger flag trigf is set from 0 to '1', the position posf of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed.
Fig. 4 is a diagram illustrating the deserialization relationship between the ADC sampling data and the trigger signal. And if the total frequency dividing ratio of the acquired data of the ADC is 8, combining 8 sampling points into a group to form parallel acquired data, wherein the parallel acquired data is consistent with the triggering deserializing ratio. The acquired data of the output signal (trigger signal) of the trigger comparator is subjected to serial-parallel conversion according to a deserializing proportion of 8, and 8 sampling points are combined into a group to form parallel trigger data.
If the pre-triggering is completed when the data sampled in parallel reaches the As point, the trigger detection is started at the Bs point, and if the data sampled in parallel is triggered by a rising edge, the data Bt triggered in parallel includes a state change from '0' to '1', that is, a rising edge, in this embodiment, As shown in fig. 4, according to the corresponding relationship, a trigger event occurs at the position of the "N + 9" point sampled by the ADC, where the point is a trigger point; if the trigger is a rising edge trigger, the deserialized trigger data Bt also includes state changes from '1' to '0', that is, includes a rising edge, and in this embodiment, the trigger event occurs at the position of the "N + 12" th point of the ADC sampling according to the corresponding relationship, where the point is the trigger point.
After the pre-triggering is completed, the rising edge or the falling edge needs to be judged in real time in the parallel trigger data, and the trigger data state detection circuit is designed to realize the function, as shown in fig. 5. The deserialized trigger data (parallel trigger data) enters the rising edge detection module and the falling edge detection module at the same time.
In the rising edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '0' to '1', the parallel trigger data is regarded as rising edge trigger, a trigger mark trigr is set from 0 to '1', the position posr of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
in the falling edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '1' to '0', the parallel trigger data is regarded as falling edge trigger, a trigger flag trigf is set from 0 to '1', the position posf of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed.
Step S3: determining the location of trigger points in parallel acquisition data
In this embodiment, as shown in fig. 5, according to the trigger edge setting condition of the digital storage oscilloscope, the trigger flag trigr and the position posr output by the rising edge trigger detection module or the trigger flag trigf and the position posf output by the falling edge trigger detection module are selected as the system trigger state Trig and the trigger position flag via the edge selection signal Trig _ sel;
the digital storage oscilloscope trigger storage control circuit latches the storage address of the parallel acquisition data by using the change of the system trigger state trig from '0' to '1', and then determines the corresponding trigger point of the trigger position in the address by the trigger position flag to realize the position of the trigger point in the parallel acquisition data.
Fig. 6 is a simulation schematic diagram of the digital trigger detection method of the present invention, the deserialization ratio of the trigger signal is the same as the frequency dividing ratio of the ADC sampling data, both are 8 times, and the trigger edge selects the rising edge for triggering. The trigger comparison threshold is set as the central point of the full scale of the sampled data, i.e. if the sampled data is greater than or equal to 128, the trigger comparator outputs trig _ in as logic '1', otherwise, it is logic '0'. Dt is the deserialized trigger data, ADC _ data 0-ADC _ data7 are the frequency divided sample data, and the lowest bit of Dt corresponds to ADC _ data 0. After the pre-trigger is completed, the trigger data state detection circuit in the FPGA starts to detect the trigger data, and the detection logic is performed as shown in fig. 5. As can be seen from fig. 6, in the ADC deserializing data after triggering, that is, the parallel acquisition data, the 2 nd sampling point data 41 and the 3 rd sampling point data 143 generate a jump crossing the trigger threshold 128, and therefore are identified as rising edge triggering, at this time, the corresponding trigger deserializing data Dt is "00111100", the trigger position flag should be "2", and the trigger state trig becomes logic '1', as can be seen from the simulation diagram, the rising edge is accurately detected.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (1)
1. A digital trigger detection method, comprising the steps of:
(1) sampling and serial-parallel conversion (deserializing) are carried out on an output signal (trigger signal) of a trigger comparator by adopting a high-speed gigabit transceiver in the FPGA, and parallel trigger data are output, wherein the sampling rate of the gigabit transceiver is the same as that of the ADC, and the deserializing proportion of the gigabit transceiver is the same as the output frequency dividing ratio N of the ADC (deserializing proportion of the FPGA to the collected data);
the parallel trigger data output by the gigabit transceiver is in a group of N, one group corresponds to one output clock cycle and is synchronous with the parallel acquisition data output by the ADC (the ADC outputs a group of acquisition parallel data, and the gigabit transceiver also outputs a group of trigger parallel data);
(2) designing a trigger data state detection circuit, wherein the trigger data state detection circuit comprises a rising edge trigger detection module and a falling edge trigger detection module, and parallel trigger data are simultaneously input into the rising edge trigger detection module and the falling edge trigger detection module;
in the rising edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has a first change from '0' to '1', the parallel trigger data is regarded as rising edge trigger, a trigger mark trigr is set from 0 to '1', the position posr of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
in a falling edge trigger detection module, after pre-triggering is completed, when a group of parallel trigger data has the first change from '1' to '0', the parallel trigger data is regarded as falling edge trigger, a trigger mark trigf is set to '1' from 0, the position posf of the trigger in the triggered parallel data is recorded, and edge detection is not performed in subsequent data after triggering is completed;
(3) selecting a trigger mark trigr and a position posr output by a rising edge trigger detection module or a trigger mark trigf and a position posf output by a falling edge trigger detection module as a system trigger state Trig and a trigger position flag through an edge selection signal Trig _ sel according to the trigger edge setting condition of the digital storage oscilloscope;
the digital storage oscilloscope trigger storage control circuit latches the storage address of the parallel acquisition data by using the change of the system trigger state trig from '0' to '1', and then determines the corresponding trigger point of the trigger position in the address by the trigger position flag to realize the position of the trigger point in the parallel acquisition data.
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| CN112084731A (en) * | 2020-08-04 | 2020-12-15 | 中电科仪器仪表有限公司 | FPGA digital circuit and method for improving peak power measurement trigger dynamic range |
| CN112798857A (en) * | 2020-12-22 | 2021-05-14 | 中电科仪器仪表有限公司 | Peak power multi-pulse parameter measuring method |
| CN113740345A (en) * | 2021-08-27 | 2021-12-03 | 电子科技大学(深圳)高等研究院 | Burr detection method and system at high sampling rate |
| WO2022105059A1 (en) * | 2020-11-17 | 2022-05-27 | 北京普源精电科技有限公司 | Trigger system and method for oscilloscope, oscilloscope, and storage medium |
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