CN110571773B

CN110571773B - Protective circuit

Info

Publication number: CN110571773B
Application number: CN201910885912.4A
Authority: CN
Inventors: 王越; 凌涛; 晏成
Original assignee: Shandong Paimeng Network Technology Co ltd
Current assignee: Shandong paimeng Network Technology Co.,Ltd.
Priority date: 2019-09-19
Filing date: 2019-09-19
Publication date: 2021-11-09
Anticipated expiration: 2039-09-19
Also published as: CN110571773A

Abstract

The application discloses a protection circuit. The protection circuit comprises a first input end, a second input end, an output end, a current guide circuit, a hierarchical current limiting circuit, a power-off voltage stabilizing circuit and an energy storage circuit; one end of the current guide circuit is connected with the first input end, and the other end of the current guide circuit is connected with one end of the hierarchical current limiting circuit; the other end of the hierarchical current limiting circuit is connected with one end of the energy storage circuit; the other end of the energy storage circuit is grounded; one end of the power-off voltage stabilizing circuit is connected with one end of the energy storage circuit, and the other end of the power-off voltage stabilizing circuit is connected with the output end; the power-off voltage stabilizing circuit is also connected with the second input end. The protection circuit that this application provided has hierarchical current-limiting circuit and outage voltage stabilizing circuit, has reduced the influence of surge current and unstable voltage to circuit and equipment, has played certain guard action to circuit and equipment.

Description

Protective circuit

Technical Field

The present application relates to the field of electronic circuits and semiconductor technologies, and in particular, to a protection circuit.

Background

Circuits often produce high operating overvoltages when turning on and off inductive loads or large loads, and such transient overvoltages (or overcurrents), referred to as surge voltages (or surge currents), are a type of transient disturbance.

For example, to meet the requirement of the power receiving device for large current, a capacitor (such as a farad capacitor) with a large capacitance value is added to a circuit of most power receiving devices, when the power receiving device has the large current requirement, a short large current is provided by the farad capacitor or the capacitor with the large capacitance value, and when the large current is not needed, the circuit charges the farad capacitor.

However, at the moment of supplying power to a power receiving device including a capacitor (such as a farad capacitor) with a large capacitance value, a large surge current may be generated due to the large capacitance value of the capacitor (such as the farad capacitor), which may seriously damage the power supply device and also cause unrecoverable damage to the capacitor or circuit of the power receiving device.

Therefore, the surge current phenomenon seriously jeopardizes the safe operation of the equipment, and the reduction of the surge noise interference and the surge damage are always the core problems related to the safe and reliable operation of the equipment.

Disclosure of Invention

In view of the above, embodiments of the present application provide a protection circuit for mitigating surge interference in a circuit.

In order to solve the above technical problem, the embodiments of the present specification are implemented as follows:

the protection circuit provided by the embodiment of the specification comprises a first input end, a second input end, an output end, a current guide circuit, a hierarchical current limiting circuit, a power-off voltage stabilizing circuit and an energy storage circuit;

one end of the current guide circuit is connected with the first input end, and the other end of the current guide circuit is connected with one end of the hierarchical current limiting circuit and is used for limiting the current direction at the first input end;

the other end of the hierarchical current limiting circuit is connected with one end of the energy storage circuit and is used for limiting the current of the energy storage circuit during power-on and delaying the energy storage speed of the energy storage circuit; the other end of the energy storage circuit is grounded and used for storing electric energy;

one end of the power-off voltage stabilizing circuit is connected with one end of the energy storage circuit, and the other end of the power-off voltage stabilizing circuit is connected with the output end and used for stabilizing the voltage of the output end during power-off;

the power-off voltage stabilizing circuit is further connected with the second input end, the second input end is connected with a first power supply end of a peripheral device, the first input end is connected with a second power supply end of the peripheral device, and the second power supply end is obtained by converting the first power supply end through an internal circuit of the peripheral device.

Optionally, the current steering circuit includes a diode, an anode of the diode is connected to the first input terminal, and a cathode of the diode is connected to one end of the hierarchical current limiting circuit.

Optionally, the energy storage circuit includes a farad capacitor, one end of the farad capacitor is connected to the other end of the level current limiting circuit, and the other end of the farad capacitor is grounded.

Optionally, the hierarchical current limiting circuit includes a capacitor, a first resistor, a second resistor, a third resistor, and a first field effect transistor;

one end of the capacitor is connected with the source electrode of the first field effect transistor, and the other end of the capacitor, the grid electrode of the first field effect transistor and one end of the first resistor are intersected; the other end of the first resistor is grounded;

one end of the second resistor is connected with the source electrode of the first field effect transistor, and the other end of the second resistor is connected with the drain electrode of the first field effect transistor;

one end of the third resistor is connected with the drain electrode of the first field effect transistor, and the other end of the third resistor is connected with one end of the energy storage circuit;

and the source electrode of the first field effect transistor is connected with the other end of the current guide circuit.

Optionally, the first field effect transistor includes a P-channel field effect transistor.

Optionally, the power-off voltage stabilizing circuit comprises a second field effect transistor, a fourth resistor and an amplifying circuit;

the source electrode of the second field effect transistor, one end of the fourth resistor and one end of the energy storage circuit are intersected, the drain electrode of the second field effect transistor is connected with the output end, and the grid electrode of the second field effect transistor, the other end of the fourth resistor and one end of the amplifying circuit are intersected;

the other end of the amplifying circuit is connected with the second input end.

Optionally, the second field effect transistor includes a P-channel field effect transistor.

Optionally, the amplifying circuit includes a triode, a fifth resistor and a sixth resistor;

the base electrode of the triode is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with the second input end;

a collector of the triode is connected with one end of the sixth resistor, and the other end of the sixth resistor is connected with a grid electrode of the second field effect transistor;

and the emitter of the triode is grounded.

Optionally, the amplifying circuit further includes a seventh resistor and an eighth resistor;

one end of the seventh resistor is connected with the second input end, and the other end of the seventh resistor is connected with the other end of the fifth resistor;

one end of the eighth resistor is connected with the other end of the seventh resistor, and the other end of the eighth resistor is grounded.

Optionally, the transistor includes an NPN transistor.

The embodiment of the specification adopts at least one technical scheme which can achieve the following beneficial effects: the protection circuit provided by the embodiment of the specification comprises the hierarchical current limiting circuit, when the first input end is powered on, the hierarchical current limiting circuit limits the energy storage speed of the energy storage circuit and limits the current flowing in the circuit, so that the surge current is effectively reduced, and the damage of the surge current to peripheral power supply equipment and powered equipment is further effectively reduced.

Meanwhile, the hierarchical current limiting circuit limits the energy storage speed of the energy storage circuit, and effectively solves the problem that the peripheral power supply equipment and the powered equipment are unstable due to the energy storage circuit at the moment of power-on.

On the other hand, in the embodiment of the present specification, when the circuit is powered off, the energy storage circuit discharges, and the power-off voltage stabilizing circuit connected between the energy storage circuit and the output terminal can cut off the energy storage circuit to supply power to the output terminal, so that the problem that the energy storage circuit provides unstable voltage to the output terminal is avoided, the stability of the voltage of the output terminal is improved, the current direction is limited by the current guiding circuit, and the influence of the discharge of the energy storage circuit on peripheral equipment is avoided.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.

In the drawings:

fig. 1 is a schematic diagram of a protection circuit provided in an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a protection circuit provided in an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a protection circuit provided in an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an apparatus to which the protection circuit provided by the embodiments of the present specification is applied;

fig. 5 is a schematic diagram of an application of a protection circuit provided in an embodiment of the present disclosure;

fig. 6 is a schematic diagram of another application of the protection circuit provided in the embodiments of the present disclosure;

fig. 7 is a schematic diagram of another application of the protection circuit provided in the embodiments of the present disclosure;

fig. 8 is a schematic diagram of another application of the protection circuit provided in the embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The common electronic product equipment is directly powered by a USB (Universal Serial Bus) interface of a PC (personal computer) or by a USB interface of other equipment. It is standard to use a USB interface to power a device, for example, USB 2.0 specification can transmit 2.5 watts of power (500 mA current is provided through 5V voltage); the USB 3.0 standard is capable of transmitting 4.5 watts of power (900 mA current supplied through 5V voltage).

If the power supply requirement of the power receiving equipment is larger than the power supply capacity of the power supply equipment USB specification, the power supply equipment is damaged, and the power receiving equipment cannot work stably due to the insufficient power supply capacity.

In order to solve the above problems, most of the circuits of the power receiving devices are added with a capacitor (such as a farad capacitor) with a large capacitance value, when the power receiving devices require a large current, the farad capacitor or the capacitor with the large capacitance value provides a short large current, and when the large current is not required, the circuits charge the farad capacitor.

A capacitor, generally referred to as a capacitor for short, is a device for holding electric charge; farad capacitance is called double electric layer capacitor, gold capacitance and super capacitor, and the difference from common capacitor is firstly the difference in capacity, the maximum capacity of common capacitor is 1 ten thousand-4 ten thousand microfarads, the maximum capacity of super capacitor can reach thousands farads, 1 farad is 100 ten thousand microfarads.

The addition of the pull-out capacitor or the capacitor with large capacitance value in the circuit can meet the condition of large current temporarily required by the power receiving equipment without exceeding the range of the power supply capacity of the power supply equipment. However, a series of problems are caused by adding a pull-out capacitor or a large-capacitance capacitor to the powered device.

Firstly, at the moment of electrifying the power receiving equipment, because the capacitance value of the faradaic capacitor or the capacitor with a large capacitance value is large, a large surge current can be generated, and most PC terminals or other equipment terminals can prompt the word of surge of a concentrator port. The power supply equipment can be seriously damaged, and unrecoverable damage can be caused to the capacitance or the circuit of the power receiving equipment.

Secondly, due to the existence of the farad capacitor or the capacitor with a large capacitance value, the power supply voltage of the system is also pulled down at the moment of electrifying the power receiving equipment, so that the power supply equipment and the power receiving equipment are in unstable states.

Moreover, after the power receiving equipment is disconnected from the power supply, the capacitor with the large capacitance value or the pull-down capacitor is still connected in the circuit. The capacitor discharge process is curved, and the shape of the curve is related to the time constant. The voltage of the capacitor changes in the discharging process of the capacitor, so that the powered device has one and unstable power supply, and the powered device has an abnormal phenomenon (for example, the indicator light is turned off after the power supply is turned off for a long time, the horn occasionally makes an abnormal sound, and abnormal data information is sent, and the like, which is unpredictable and strange).

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Example 1

The embodiment 1 of the present specification provides a protection circuit, fig. 1 is a schematic diagram of the protection circuit provided by the embodiment of the present specification, and as shown IN fig. 1, the protection circuit provided by the embodiment of the present specification includes a first input terminal V-IN, a second input terminal VBUS, an output terminal V-OUT, a current steering circuit 1, a hierarchical current limiting circuit 2, a power-off voltage stabilizing circuit 4, and an energy storage circuit 3.

One end of the current guide circuit 1 is connected with the first input end V-IN, and the other end is connected with one end of the hierarchical current limiting circuit 2 and used for limiting the current direction at the first input end V-IN; the other end of the hierarchical current limiting circuit 2 is connected with one end of the energy storage circuit 3 and is used for limiting the current of the energy storage circuit 3 during power-on and delaying the energy storage speed of the energy storage circuit 3; the other end of the energy storage circuit 3 is grounded and used for storing electric energy.

One end of the power-off voltage stabilizing circuit 4 is connected with one end of the energy storage circuit 3, and the other end of the power-off voltage stabilizing circuit is connected with the output end V-OUT for stabilizing the voltage of the output end V-OUT when the power is off.

The power-off voltage stabilizing circuit 4 is further connected with a second input end VBUS, the second input end VBUS is connected with a first power supply end of the peripheral device, the first input end V-IN is connected with a second power supply end of the peripheral device, and the second power supply end is obtained by converting the first power supply end through an internal circuit of the peripheral device. The peripheral devices are not shown in fig. 1 and may include electronic devices such as PC terminals.

Fig. 2 is a schematic structural diagram of the protection circuit provided IN the embodiment of the present disclosure, and as shown IN fig. 2, the current steering circuit 1 may include a diode D1, an anode of the diode D1 is connected to the first input terminal V-IN, and a cathode of the diode D1 is connected to one end of the hierarchical current limiting circuit 2. Due to the unidirectional conductivity of the diode D1, current can only flow from the first input end V-IN to the diode D1, but cannot flow from the diode D1 to the first input end V-IN, namely, the current cannot enter peripheral equipment connected with the first input end V-IN from the first input end V-IN, and therefore a certain protection effect is achieved on the peripheral equipment.

The energy storage circuit 3 can comprise a farad capacitor C1, one end of the farad capacitor C1 is connected with the other end of the hierarchical current limiting circuit 2, and the other end of the farad capacitor C1 is grounded. When the load connected with the output end V-OUT needs large current, the short-time large current can be provided by the farad capacitor C1, and when the load does not need the large current, the circuit charges the farad capacitor C1, so that the farad capacitor C1 stores energy to ensure the subsequent requirement of the load.

Farad capacitance is also called double-layer capacitor, gold capacitance, super capacitor, which is a chemical element. The super capacitor stores energy through polarized electrolyte, but does not generate chemical reaction, and the energy storage process is reversible and can be repeatedly charged and discharged for tens of thousands of times.

The difference between the farad capacitor and the common capacitor is firstly the difference in capacity, the maximum capacity of the common capacitor is 1 ten thousand to 4 ten thousand microfarads, the maximum capacity of the farad capacitor can reach thousands of farads, and 1 farad is 100 ten thousand microfarads.

The farad capacitor C1 provided in the embodiments of the present disclosure may also be a large-capacitance capacitor, as long as it can satisfy a large current requirement of a load, and a specific capacitance value may be set according to a load condition, and the capacitance value of the farad capacitor C1 provided in the embodiments of the present disclosure is 0.5F.

As shown in fig. 2, the hierarchical current limiting circuit 2 includes a capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, and a first fet T1.

One end of the capacitor C2 is connected with the source electrode of the first field effect transistor T1, and the other end of the capacitor C2, the grid electrode of the first field effect transistor T1 and one end of the first resistor R1 are intersected; the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected to the source of the first fet T1, and the other end is connected to the drain of the first fet T1. One end of the third resistor R3 is connected with the drain electrode of the first field effect transistor T1, and the other end is connected with one end of the energy storage circuit; the source of the first fet T1 is connected to the other end of the current steering circuit. Specifically, as shown in fig. 1, the other end of the third resistor R3 is connected to one end of the faraday capacitor C1. The first fet T1 may comprise a P-channel fet, which may be referred to as a PMOS transistor. For convenience of description, the first fet T1 will be hereinafter referred to as a PMOS transistor T1.

When the circuit is powered on, namely the first input end V-IN is powered on, due to the characteristics of the capacitor, the voltage at two ends of the capacitor cannot suddenly change at the moment of powering on, namely the voltage at two ends of the capacitor C2 cannot suddenly change and is 0, at the moment, the gate voltage of the PMOS tube T1 is 0 at one end of the capacitor C2, the source voltage is V-IN at one end of the second resistor R2, namely the gate source voltage value of the PMOS tube T1 is greater than the threshold voltage Vgs (the value is a negative value), the PMOS tube T1 is IN an off state, the current IN the circuit slowly charges the farad capacitor C1 through the second resistor R2 and the third resistor R3, and the second resistor R2 and the third resistor R3 play a role IN limiting current.

Meanwhile, the capacitor C2 and the first resistor R1 form the simplest RC delay circuit, electrons at two ends of the capacitor C2 are continuously gathered along with the prolonging of the power-on time, the grid source voltage of the PMOS transistor T1 is continuously reduced, the grid G of the PMOS transistor T1 is at a low level, when the gate-source voltage value of the PMOS transistor T1 is less than or equal to the threshold voltage Vgs of T1 (which is negative), the PMOS transistor T1 is conducted to short-circuit the second resistor R2, the current in the circuit rapidly charges the farad capacitor C1 through the third resistor, since the farad capacitor C1 is in a slow charging state during the process from the off state to the on state of the PMOS transistor T1, when the PMOS transistor T1 is conducted, a certain amount of electricity is stored in the Faraday capacitor C1, and a certain voltage is applied, on the basis, the farad capacitor C1 is charged again, so that the excessive surge current and the voltage fluctuation in the circuit can not be caused, therefore, the problem that power supply equipment and powered equipment are unstable due to the fact that a large-capacitance-value capacitor or a farad capacitor is charged at the moment is solved.

It should be noted that, the RC delay circuit used in the embodiments of the present disclosure may also be a delay circuit in other forms, as long as a hierarchical charging process of slowly and quickly charging the farad capacitor C1 can be implemented.

Moreover, the values of the second resistor R2 and the third resistor R3 may be determined according to specific circuits and use cases, and the resistance values of the second resistor R2 and the third resistor R3 provided in the embodiments of the present specification are 5.1 ohms.

The power-off voltage stabilizing circuit 4 provided by the embodiment of the present specification may include a second field effect transistor T2, a fourth resistor R4, and an amplifying circuit, where a source of the second field effect transistor T2, one end of the fourth resistor R4, and one end of the energy storage circuit intersect with each other, a drain of the second field effect transistor T2 is connected to the output terminal V-OUT, and a gate of the second field effect transistor T2, the other end of the fourth resistor R4, and one end of the amplifying circuit intersect with each other; the other end of the amplifying circuit is connected with a second input end VBUS.

The second fet T2 may comprise a P-channel fet, which may be referred to as a PMOS transistor. For convenience of description, the second fet T2 will be hereinafter referred to as a PMOS transistor T2.

Specifically, when the first input terminal V-IN is powered on, because the amplifying circuit is connected to the second input terminal VBUS, at this time, the amplifying circuit is started simultaneously, the amplifying circuit is connected to the fourth resistor R4, the current flowing through the fourth resistor R4 is controlled, because the gate and the source of the second fet T2 are connected to the two ends of the fourth resistor R4, respectively, the voltage difference between the gate and the source of the second fet T2 is the voltage difference between the two ends of the fourth resistor R4, the current IN the amplifying circuit is controlled, and further the voltage value of the gate and the source of the second fet T2 is controlled to be less than or equal to the threshold voltage Vgs of T1 (the voltage is a negative value), so that the PMOS transistor T2 is IN a conducting state, and thus the load connected to the output terminal V-OUT can be powered by the first input terminal V-IN, and the load is IN a working state.

As shown in fig. 2, the amplifying circuit may further include a transistor Q3, a fifth resistor R5, and a sixth resistor R6, specifically, a base of the transistor Q3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the second input terminal VBUS; a collector of the triode Q3 is connected with one end of a sixth resistor R6, and the other end of the sixth resistor R6 is connected with the gate of the second field-effect transistor T2; the emitter of transistor Q3 is connected to ground. The transistor Q3 includes an NPN transistor as an electronic switch, and the fifth resistor R5 and the sixth resistor R6 function as current limiting protection.

Specifically, when the protection circuit is powered on, that is, when the first input terminal V-IN and the second input terminal VBUS are powered on, the base of the transistor Q3 is at a high level, the base radio voltage of the transistor Q3 is greater than the threshold voltage Vbe (the silicon transistor is 0.7V, and the germanium transistor is 0.5V), the collector and the emitter of the transistor Q3 are conducted to form an amplifying circuit, and further, the current IN the fourth resistor R4 is controlled, so that the voltage value of the pole and the source of the second field-effect transistor T2 is less than or equal to the threshold voltage Vgs of the T1 (the value is a negative value), and the PMOS transistor T2 is IN a conducting state, so that the load connected to the output terminal V-OUT can be powered by the first input terminal V-IN, and the load is IN a working state.

When the protection circuit is powered off, namely the first input end V-IN and the second input end VBUS are powered off, the base of the triode Q3 is at a low level, the base radio voltage of the triode Q3 is smaller than the threshold voltage Vbe (the silicon tube is 0.7V, and the germanium tube is 0.5V), so that the triode Q3 is turned off, because the fourth resistor R4 is connected between the gate G of the PMOS tube T2 and the source collector S, at this time, the gate source voltage value of the PMOS tube T2 is greater than the threshold Vgs (the value is a negative value), so that the PMOS tube T2 is IN an off state, and because the farad capacitor C1 stores electric energy, after the power is powered off, the farad capacitor C1 continues to supply power to the circuit, and at this time, the PMOS tube T2 is IN an off state, the electric energy discharged by the farad capacitor C1 cannot be transmitted to a load connected to the output end V-OUT, thereby solving the problem that the load or the power receiving device is extremely unstable IN power supply.

As shown IN fig. 2, the protection circuit further includes a diode D1, when the protection circuit is powered off and the farad capacitor C1 discharges, the farad capacitor C1 cannot supply current to the peripheral device connected to the first input terminal V-IN due to the unidirectional conduction characteristic of the diode D1, thereby avoiding damage to the peripheral device.

On the basis of the structural schematic diagram of the protection circuit, fig. 3 is another structural schematic diagram of the protection circuit provided in the embodiment of the present specification. Wherein the amplifying circuit may further include a seventh resistor R7 and an eighth resistor R8; one end of the seventh resistor R7 is connected to the second input end VBUS, and the other end is connected to the other end of the fifth resistor R5; one end of the eighth resistor R8 is connected to the other end of the seventh resistor R7, and the other end is grounded. The seventh resistor R7 and the eighth resistor R8 constitute a voltage dividing circuit, and perform a voltage dividing protection function on the amplifying circuit.

The protection circuit provided by the embodiment 1 of the present specification can achieve, but is not limited to, the following beneficial effects: the protection circuit provided in embodiment 1 of the present description includes a hierarchical current limiting circuit, and when the first input terminal is powered on, the hierarchical current limiting circuit limits the energy storage speed of the energy storage circuit, and limits the current flowing through the circuit, thereby effectively reducing the inrush current, and effectively reducing the damage of the inrush current to the peripheral power supply device and the powered device.

Example 2

On the basis of the above embodiment 1, the protection circuit provided in this specification can be applied to a power receiving device, and in order to more clearly describe the case of the protection circuit provided in this specification, embodiment 2 of this specification applies the above protection circuit to a code scanning payment device.

Along with the progress of science and technology, more and more people use the cell-phone to carry out the payment of consumption, thereby various sweep a yard payment equipment and also generally be applied to people's life, like the cash desk department of market, supermarket etc., for further convenience of customers uses, it can provide the voice broadcast function in the yard payment equipment to sweep at most, adopt the speaker to carry out voice broadcast, and in the twinkling of an eye that the speaker carries out work, need great electric quantity to make the speaker start, for the normal start of guaranteeing the speaker and not exceeding power supply's operational capability, can select the condenser of setting for a large capacitance value in sweeping yard payment equipment, provide transient heavy current for the speaker and make the normal start of speaker. Meanwhile, due to the existence of the capacitor with the large capacitance value in the circuit, at the moment of electrifying the code scanning payment equipment, due to the large capacitance value of the capacitor with the large capacitance value, if no current limiting measure is taken, a large surge current can be generated, if the code scanning payment equipment is connected with the PC end, most of the PC ends can prompt 'surge of a concentrator port', power supply equipment can be seriously damaged, and the capacitor or the circuit in the code scanning payment equipment can be damaged unrecoverably. In order to protect the code scanning payment device and the power supply device, embodiment 2 of the present specification applies a protection circuit to the code scanning payment device.

Fig. 4 is a schematic diagram of a device to which the protection circuit provided in the embodiment of the present specification is applied, and as shown in fig. 4, the protection circuit 2-2 is connected to the speaker 2-3 in the code scanning payment device 2-11 and connected to the PC terminal 2-4. Specifically, fig. 5 is an application schematic diagram of the protection circuit provided in the embodiment of the present disclosure. As shown in fig. 5, the output terminal V-OUT in the protection circuit 2-2 may be connected to the speaker 2-3.

The protection circuit 2-2 further comprises a first input end V-IN, a second input end VBUS, a diode D1, a hierarchical current limiting circuit 2, a power-off voltage stabilizing circuit 4 and a farad capacitor C1, wherein specifically, the anode of the diode D1 is connected with the first input end V-IN, and the cathode of the diode D1 is connected with one end of the hierarchical current limiting circuit 2 and used for limiting the current direction at the first input end V-IN; one end of the hierarchical current limiting circuit 2 is connected with the first input end V-IN, and the other end of the hierarchical current limiting circuit is connected with one end of the farad capacitor C1, so that the current of the farad capacitor C1 during electrification is limited, and the energy storage speed of the farad capacitor C1 is slowed; the other end of the farad capacitor C1 is grounded and used for storing electric energy; one end of the power-off voltage stabilizing circuit 4 is connected with one end of a farad capacitor C1, and the other end of the power-off voltage stabilizing circuit is connected with the output end V-OUT for stabilizing the voltage of the output end V-OUT when the power is off.

The power-off voltage stabilizing circuit 2 is further connected with a second input end VBUS, wherein the second input end VBUS is connected with a first power supply end of the peripheral device, the first input end V-IN is connected with a second power supply end of the peripheral device, and the second power supply end is obtained by converting the first power supply end through an internal circuit of the peripheral device. In this embodiment, the first power end of the peripheral device may be a power end of the PC terminal 4, and the second power end may be a USB interface of the PC terminal 4 connected to the code-scanning payment device 1.

The farad C1 may also provide a brief high current to the load connected to the output V-OUT when there is a high current demand on it to meet the load's demand. For example, when carrying out voice broadcast, loudspeaker 3 just begins to broadcast and reports and needs the heavy current in the twinkling of an eye, just can provide brief heavy current by farad capacitor C1, when loudspeaker 3 is in steady operating condition, perhaps after voice broadcast ends, loudspeaker 3 no longer needs the heavy current, and farad capacitor C1 can no longer provide the heavy current this moment, and the circuit charges for farad capacitor C1, makes farad capacitor C1 energy storage in order to guarantee the follow-up demand of load.

As shown in fig. 5, the hierarchical current limiting circuit 2 may include a capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, and a first fet T1. One end of the capacitor C2 is connected with the source electrode of the first field effect transistor T1, and the other end of the capacitor C2, the grid electrode of the first field effect transistor T1 and one end of the first resistor R1 are intersected; the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected with the source electrode of the first field effect transistor T1, and the other end is connected with the drain electrode of the first field effect transistor T1; one end of the third resistor R3 is connected with the drain electrode of the first field effect transistor T1, and the other end is connected with one end of the farad capacitor C1; the source of the first fet T1 is connected to the cathode of the diode D1.

The first fet T1 may comprise a P-channel fet, which may be referred to as a PMOS transistor. For convenience of description, the first fet T1 will be hereinafter referred to as a PMOS transistor T1.

IN practical application, the code scanning payment device 1 including the protection circuit provided IN the embodiment of the present disclosure is connected to a PC terminal through a USB interface, the code scanning payment device 1 may be directly connected to a USB interface of an already-powered PC terminal, or the code scanning payment device may be connected to the PC terminal, and then the PC terminal is powered on, so that the code scanning payment device is also powered on, at this time, the protection circuit is also powered on, when the circuit is powered on, that is, when the first input terminal V-IN is powered on, due to the characteristics of the capacitor itself, the voltage at two ends of the capacitor C2 cannot suddenly change at the moment of powering on, the gate voltage value of the PMOS transistor T1 is greater than the threshold voltage Vgs (the value is a negative value), so that the PMOS transistor T1 is IN an off state, the current IN the circuit slowly charges the farad C1 through the second resistor R2 and the third resistor R3, and the second resistor R2 and the third resistor R3 play a role of limiting current.

Meanwhile, the capacitor C2 and the first resistor R1 form the simplest RC delay circuit, electrons at two ends of the capacitor C2 are gathered continuously along with the prolonging of the power-on time, the grid source voltage of the PMOS tube T1 is reduced continuously, the grid G of the PMOS tube T1 is at a low level, when the grid source voltage value of the PMOS tube T1 is smaller than or equal to the threshold voltage Vgs of T1 (the value is a negative value), the PMOS tube T1 is conducted, the second resistor R2 is short-circuited, the current in the circuit charges the farad capacitor C1 quickly through the third resistor R3, because the farad capacitor C1 is in a slow charging state in the process from the disconnection to the conduction of the PMOS tube T1, a certain amount of electricity is stored in the farad capacitor C1 when the PMOS tube T1 is conducted, and has a certain voltage, and on the basis, the influence of the surge current of the loudspeaker on the output end caused by the surge current of the farad capacitor C1 charged through the third resistor R3 is effectively reduced, in addition, due to the current limiting effect of the second resistor R2 and the third resistor R3, the farad capacitor C1 cannot absorb excessive electric energy at the power-on moment, and the stability of the electric energy of the output end is improved.

The third resistor R3 may be further connected between the cathode of the diode D1 and the first fet T1, and specifically may include: one end of a third resistor R3 is connected with the cathode of the diode D1, and the other end of the third resistor R3, the source of the first field-effect transistor T1 and one end of the capacitor C2 are intersected; secondly, one end of the third resistor R3, the cathode of the diode D1 and one end of the capacitor C2 intersect, and the other end of the third resistor R3 is connected with the source electrode of the first field effect transistor T1. Thus, the third resistor R3 can also serve as a current limiter.

The power-off voltage stabilizing circuit 4 provided by the embodiment of the specification can comprise a second field effect transistor T2, a fourth resistor R4 and an amplifying circuit, wherein the amplifying circuit comprises a triode Q3, a fifth resistor R5 and a sixth resistor R6. As shown in fig. 5, the base of the transistor Q3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the second input terminal VBUS; a collector of the triode Q3 is connected with one end of a sixth resistor R6, and the other end of the sixth resistor R6 is connected with the gate of the second field-effect transistor T2; the emitter of transistor Q3 is connected to ground. The transistor Q3 includes an NPN transistor as an electronic switch, and the fifth resistor R5 and the sixth resistor R6 function as current limiting protection.

The source electrode of the second field effect transistor T2, one end of the fourth resistor R4 and one end of the farad capacitor C1 are intersected, the drain electrode of the second field effect transistor T2 is connected with the output end V-OUT, and the grid electrode of the second field effect transistor T2, the other end of the fourth resistor R4 and the other end of the sixth resistor R6 are intersected. When the circuit is powered off, the power-off voltage stabilizing circuit can prevent the output end V-OUT from outputting unstable voltage provided by the farad capacitor C1.

Specifically, the second fet T2 may include a P-channel fet, which may be referred to as a PMOS transistor. For convenience of description, the second fet T2 will be hereinafter referred to as a PMOS transistor T2.

When the protection circuit is powered on, that is, when the first input terminal V-IN and the second input terminal VBUS are powered on, the base of the triode Q3 is at a high level, the base radio voltage of the triode Q3 is greater than the threshold voltage Vbe (the silicon tube is 0.7V, and the germanium tube is 0.5V), the collector and the emitter of the triode Q3 are conducted to form an amplifying circuit, so that the voltage value of the pole and the source of the second field-effect tube T2 is less than or equal to the threshold voltage Vgs of T1 (the value is a negative value), and the PMOS tube T2 is IN a conducting state, so that the speaker 3 connected to the output terminal V-OUT can be powered by the first input terminal V-IN, and the speaker 3 is IN a working state. And because farad capacitor C1 is limited by the hierarchical current limiting circuit and third resistor R3, excessive voltage is not distributed, so that loudspeaker 3 can obtain more stable voltage, and certain voltage stabilizing effect is achieved.

When the protection circuit is powered off, that is, when the first input terminal V-IN and the second input terminal VBUS are powered off, the base of the triode Q3 is at a low level, the base radio voltage of the triode Q3 is less than the threshold voltage Vbe (the silicon tube is 0.7V, and the germanium tube is 0.5V), so that the triode Q3 is turned off, at this time, the gate source voltage value of the PMOS tube T2 is greater than the threshold Vgs (the value is negative), so that the PMOS tube T2 is IN the off state, because the farad capacitor C1 stores electric energy, after the power off, the farad capacitor C1 continues to supply power to the circuit, and as the discharging time of the farad capacitor C1 is prolonged, the voltage provided by the farad capacitor C1 is reduced, while the PMOS tube T2 is IN the off state, the electric energy discharged by the farad capacitor C1 cannot be transmitted to the loudspeaker 3 connected to the output terminal V-OUT, thereby solving the problem that the loudspeaker 3 is extremely unstable IN power off, that the loudspeaker 3 IN the present embodiment does not generate abnormal sound after the power off, plays a certain role in protecting the loudspeaker 3.

And because of the unidirectional conduction characteristic of the diode D1, the farad capacitor C1 cannot provide current for the circuit connected with the first input end V-IN, and the damage to the PC end is avoided.

The protection circuit that this description embodiment 2 provided has the advantage with the protection circuit that this description embodiment 1 provided, and it is no longer repeated here to, the protection circuit that this embodiment 2 provided is connected with the speaker of sweeping yard payment equipment, when having restricted the surge phenomenon, has avoided because of the unstable damage to the speaker of voltage, has protected to a certain extent and has swept yard payment equipment.

Example 3

On the basis of the above embodiment 2, embodiment 3 of the present specification provides another application schematic diagram of a protection circuit, and is also applicable to the code scanning payment device in the above embodiment 2. The protection circuit provided in embodiment 3 of this specification includes the protection circuit provided in embodiment 2, and in order to further protect the amplification circuit and the entire protection circuit, a voltage dividing resistor is added to the protection circuit provided in embodiment 2 in the protection circuit provided in embodiment 3 of this specification

As shown in fig. 6, the protection circuit may further include a seventh resistor R7 and an eighth resistor R8, which are located in the amplifying circuit. One end of the seventh resistor R7 is connected to the second input end VBUS, and the other end is connected to the other end of the fifth resistor R5; one end of the eighth resistor R8 is connected to the other end of the seventh resistor R7, and the other end is grounded.

The seventh resistor R7 and the eighth resistor R8 form a voltage divider circuit, which performs a voltage division protection function on the amplifier circuit and also performs a certain protection function on the protection circuit.

Other parts of the protection circuit provided in embodiment 3 of this specification are the same as those of the protection circuit in embodiment 2 described above, and are not described again here.

In addition, the protection circuit provided in embodiment 3 has a voltage dividing resistor, so as to avoid the damage of the transistor Q3 caused by the excessive voltage input at the second input terminal VBUS, and further protect the voltage dividing circuit and the protection circuit.

Example 4

Based on any one of the protection circuits IN embodiments 1 to 3, the protection circuit provided IN this specification may also be applied to protection of an indicator light, fig. 7 is an application schematic diagram of another protection circuit provided IN this specification, and the protection circuit provided IN embodiment 4 IN this specification includes a first input terminal V-IN, a second input terminal VBUS, an output terminal V-OUT, a current steering circuit 1, a hierarchical current limiting circuit 2, a power-off voltage stabilizing circuit 4, and an energy storage circuit 3; the output end V-OUT is connected with the indicating lamp circuit board 3-1, the indicating lamp circuit board 3-1 comprises at least one indicating lamp, the indicating lamp can adopt a light emitting diode, and the output end V-OUT can provide electric energy required by the indicating lamp circuit board 3-1.

One end of the current guide circuit 1 is connected with the first input end V-IN, and the other end is connected with one end of the hierarchical current limiting circuit 2, so as to limit the current direction at the first input end V-IN; the other end of the hierarchical current limiting circuit 2 is connected with one end of the energy storage circuit 3 and is used for limiting the current of the energy storage circuit 3 at the moment of power-on and delaying the energy storage speed of the energy storage circuit 3; the other end of the energy storage circuit 3 is grounded and used for storing electric energy; one end of the power-off voltage stabilizing circuit 4 is connected with one end of the energy storage circuit 3, and the other end of the power-off voltage stabilizing circuit is connected with the output end V-OUT and is used for stabilizing the voltage of the output end during power-off; the power-off voltage stabilizing circuit 4 is further connected with the second input end VBUS, the second input end VBUS is connected with a first power supply end of a peripheral device, the first input end V-IN is connected with a second power supply end of the peripheral device, and the second power supply end is obtained by converting the first power supply end through an internal circuit of the peripheral device.

The current steering circuit 1 comprises a diode D1; the energy storage circuit 3 comprises a farad capacitor C1, and the hierarchical current limiting circuit 2 comprises a capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3 and a first field-effect transistor T1; the power-off voltage stabilizing circuit 4 comprises a second field effect transistor T2, a fourth resistor R4 and an amplifying circuit, wherein the amplifying circuit comprises a triode Q3, a fifth resistor R5 and a sixth resistor R6.

Specifically, as shown IN fig. 7, the anode of the diode D1 is connected to the first input terminal V-IN, and the cathode of the diode D1 is connected to the source of the first fet T1; one end of the capacitor C2 is connected with the source electrode of the first field effect transistor T1, the other end of the capacitor C2, the grid electrode of the first field effect transistor T1 and one end of the first resistor R1 are intersected, and the other end of the first resistor R1 is grounded; one end of the second resistor R2 is connected with the source electrode of the first field effect transistor T1, and the other end is connected with the drain electrode of the first field effect transistor T1; one end of the third resistor R3 is connected to the drain of the first fet T1, and the other end is connected to one end of the farad capacitor C1.

The source electrode of the second field-effect tube T2, one end of the fourth resistor R4 and one end of the farad capacitor C1 are intersected, the drain electrode of the second field-effect tube T2 is connected with the output end V-OUT, and the grid electrode of the second field-effect tube T2, the other end of the fourth resistor R4 and the other end of the sixth resistor R6 are intersected; one end of the sixth resistor R6 is connected with the collector of the triode Q3, the base of the triode Q3 is connected with one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the second input end VBUS; the emitter of transistor Q3 is connected to ground.

When the load connected with the output end V-OUT has a large current demand, the short-time large current can be provided by the farad capacitor C1, and when the load does not need the large current, the circuit charges the farad capacitor C1, so that the farad capacitor C1 stores energy to ensure the subsequent demand of the load. For example, in embodiment 3 of this specification, when the indicator lamp in the indicator lamp circuit board 3-1 is turned on at an instant, an instantaneous large current is needed to drive the indicator lamp to be turned on, the output terminal V-OUT is an input power supply network of a large current power supply circuit that needs a short time, and is connected to the indicator lamp, at this time, the farad capacitor C1 may provide a short-lived large current, when the indicator lamp is in a stable turned-on state or a turned-off state, the indicator lamp does not need a large current at this time, and the circuit may charge the farad capacitor C1, so that the farad capacitor C1 stores energy to ensure the subsequent requirement of the indicator lamp. Therefore, when the indicating lamp needs large current, the indicating lamp does not need to be provided by peripheral power supply equipment at the first input end V-IN, the working limit of the peripheral power supply equipment is avoided being exceeded, and a certain protection effect is achieved on the peripheral power supply equipment. For example, the first input end V-IN is connected to the USB interface of the PC end, and when the indicator lamp needs a large current, the farad capacitor C1 can provide a short large current, thereby effectively avoiding the problem that the first input end V-IN exceeds the power supply capability of the USB interface.

It should be noted that the farad capacitor C1 provided in the embodiments of the present disclosure may also be a large-capacitance capacitor, as long as the large-current requirement of the load can be satisfied, and the specific capacitance value may be set according to the load condition.

When the circuit is powered on, namely the first input end V-IN is powered on, due to the characteristics of the capacitor, the voltage at two ends of the capacitor cannot change suddenly at the moment of power on, the grid source voltage value of the PMOS tube T1 is larger than the threshold voltage Vgs (the value is a negative value), so that the PMOS tube T1 is IN an off state, the current IN the circuit slowly charges the farad capacitor C1 through the second resistor R2 and the third resistor R3, and the second resistor R2 and the third resistor R3 play a role IN limiting the current.

Moreover, the capacitor C2 and the first resistor R1 form the simplest RC delay circuit, electrons at two ends of the capacitor C2 are continuously gathered along with the prolonging of the power-on time, the grid source voltage of the PMOS tube T1 is continuously reduced, the grid G of the PMOS tube T1 is at a low level, when the grid source voltage value of the PMOS tube T1 is smaller than or equal to the threshold voltage Vgs of T1 (the value is a negative value), the PMOS tube T1 is conducted, the second resistor R2 is short-circuited, the farad capacitor C1 is rapidly charged by the current in the circuit through the PMOS tube T1 and the third resistor R3, because the farad capacitor C1 is in a slow charging state in the process from the disconnection to the conduction of the PMOS tube T1, a certain amount of electricity is stored in the farad capacitor C1 when the PMOS tube T1 is conducted, and has a certain voltage, on the basis, the charge of the farad capacitor C1 through the third resistor R3 can not cause the overlarge current and the voltage fluctuation of the surge current of the output end of the effective surge indicating lamp-1-3 surge current-surge-circuit board, in addition, due to the current limiting effect of the second resistor R2 and the third resistor R3, the farad capacitor C1 does not absorb excessive electric energy at the power-on moment, the stability of the electric energy of the output end is improved, and the electric energy of the output end can meet the normal use of the circuit board 3-1 of the indicator lamp.

It should be noted that the values of the second resistor R2 and the third resistor R3 may be determined according to specific circuits and use cases, and the resistance values of the second resistor R2 and the third resistor R3 provided in the embodiments of the present disclosure are 5.1 ohms.

The transistor Q3 provided in embodiment 4 of this specification may include an NPN-type transistor, which serves as an electronic switch, and the fifth resistor R5 and the sixth resistor R6 perform a current limiting protection function.

When the protection circuit is powered on, namely the first input end V-IN and the second input end VBUS are powered on, the base of the triode Q3 is at a high level, the base radio voltage of the triode Q3 is greater than the threshold voltage Vbe (the silicon tube is 0.7V, and the germanium tube is 0.5V), the collector and the emitter of the triode Q3 are conducted to form an amplifying circuit, and further the current IN the fourth resistor R4 is controlled, so that the voltage value of the gate and the source of the second field effect tube T2 is less than or equal to the threshold voltage Vgs of the T1 (the value is a negative value), and the PMOS tube T2 is IN a conducting state, so that the indicator lamp circuit board 3-1 and the indicator lamp connected at the output end V-OUT can be powered by the first input end V-IN, and the indicator lamp can be IN a working state. And because farad capacitor C1 is limited by the hierarchical current limiting circuit and third resistor R3, excessive voltage can not be divided, thus indicator light circuit board 3-1 and indicator light can obtain more stable voltage, and certain voltage stabilizing function is also played.

When the protection circuit is powered off, that is, when the first input terminal V-IN and the second input terminal VBUS are powered off, the base of the transistor Q3 is at a low level, and the base radio voltage of the transistor Q3 is less than the threshold voltage Vbe (the silicon transistor is 0.7V, and the germanium transistor is 0.5V), so that the transistor Q3 is turned off, because the fourth resistor R4 is connected between the gate G of the PMOS transistor T2 and the source collector S, at this time, the gate voltage value of the PMOS transistor T2 is greater than the threshold Vgs (the value is a negative value), so that the PMOS transistor T2 is IN an off state, because the faraday capacitor C1 stores electric energy, after the power is off, the faraday capacitor C1 will continue to supply power to the circuit, and when the PMOS transistor T2 is IN the off state, the electric energy discharged from the faraday capacitor C1 will not be transmitted to the load connected to the output terminal V-OUT, thereby solving the problem that the load or the power receiving device can supply power very unstably, that is not turned off again after the indicator lamp IN this specification is continuously turned on and turned off for a while power is turned off, but the power-off state is immediately extinguished along with the power-off state, so that the condition that the indicator lamp bears unstable voltage provided by the farad capacitor C1 is avoided, and a certain protection effect is achieved on the indicator lamp.

And because of the unidirectional conduction characteristic of the diode D1, the farad capacitor C1 cannot provide electric energy for the circuit connected to the first input end V-IN, and damage to peripheral power supply equipment is avoided.

The second input end VBUS is an interface power network, and voltage is generated only when power is supplied to the powered device; the first input terminal V-IN is an output power network of the second input terminal VBUS after passing through some circuits. Specifically, the second input terminal VBUS may be connected to a first power terminal of the peripheral device, and the first input terminal V-IN may be connected to a second power terminal of the peripheral device, where the second power terminal is converted by the first power terminal through an internal circuit of the peripheral device.

For example, the protection circuit provided IN embodiment 4 of this specification can be applied to a code scanning payment device including an indicator light circuit board, the code scanning payment device can be connected to a PC terminal, where the first input terminal V-IN can be connected to a USB interface of the PC terminal, and the second input terminal VBUS can be connected to a power interface of the PC terminal, that is, the USB interface of the PC terminal is equivalent to a second power terminal of a peripheral device, the power interface of the PC terminal is equivalent to a first power terminal of the peripheral device, the second power terminal is obtained by converting the first power terminal through an internal circuit of the PC terminal, and the first input terminal V-IN and the second input terminal VBUS are powered on or powered off simultaneously.

The protection circuit provided by embodiment 4 of this specification has at least one of the advantages of the protection circuit provided by embodiments 1 to 3 of this specification, and it is not described herein any more, and the protection circuit provided by embodiment 4 is connected with the indicator lamp circuit board, so that the damage to the indicator lamp circuit board due to voltage instability is avoided while the surge phenomenon is limited, and the current direction of the current guide circuit is limited, so that the influence of the energy storage circuit on the peripheral device is avoided, and the peripheral device is protected to a certain extent.

Example 5

In addition, in the protection circuit provided in embodiment 5 of the present specification, in order to further protect the amplification circuit and the entire protection circuit, a voltage dividing resistor is added on the basis of the protection circuit provided in embodiment 4.

As shown in fig. 8, the protection circuit may further include a seventh resistor R7 and an eighth resistor R8, which are located in the amplifying circuit. One end of the seventh resistor R7 is connected to the second input end VBUS, and the other end is connected to the other end of the fifth resistor R5; one end of the eighth resistor R8 is connected to the other end of the seventh resistor R7, and the other end is grounded.

Other parts of the protection circuit provided in embodiment 5 of this specification are the same as those of the protection circuit in embodiment 4 described above, and are not described again here.

In addition, the protection circuit provided in embodiment 5 has a voltage dividing resistor, so as to avoid the damage of the transistor Q3 caused by the excessive voltage input at the second input terminal VBUS, and further protect the voltage dividing circuit and the protection circuit.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A protection circuit is characterized by comprising a first input end, a second input end, an output end, a current guide circuit, a hierarchical current limiting circuit, a power-off voltage stabilizing circuit and an energy storage circuit;

one end of the power-off voltage stabilizing circuit is connected with one end of the energy storage circuit, and the other end of the power-off voltage stabilizing circuit is connected with the output end and is used for cutting off the energy storage circuit to supply power to the output end so as to stabilize the voltage of the output end during power-off;

2. A protection circuit according to claim 1, wherein the current steering circuit comprises a diode, an anode of the diode being connected to the first input terminal, and a cathode of the diode being connected to one end of the hierarchical current limiting circuit.

3. The protection circuit of claim 1, wherein the tank circuit comprises a farad capacitor, one end of the farad capacitor is connected to the other end of the hierarchical current limiting circuit, and the other end of the farad capacitor is grounded.

4. The protection circuit of claim 1, wherein the hierarchical current limiting circuit comprises a capacitor, a first resistor, a second resistor, a third resistor and a first field effect transistor;

5. The protection circuit of claim 4, wherein the first FET comprises a P-channel FET.

6. The protection circuit of claim 1, wherein the power-down voltage stabilizing circuit comprises a second field effect transistor, a fourth resistor and an amplifying circuit;

the other end of the amplifying circuit is connected with the second input end.

7. The protection circuit of claim 6, wherein said second fet comprises a P-channel fet.

8. The protection circuit according to claim 6, wherein the amplifying circuit comprises a transistor, a fifth resistor and a sixth resistor;

and the emitter of the triode is grounded.

9. The protection circuit according to claim 8, wherein the amplifying circuit further comprises a seventh resistor and an eighth resistor;

10. The protection circuit of claim 8, wherein the transistor comprises an NPN transistor.