CN110571201A - high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof - Google Patents

high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof Download PDF

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Publication number
CN110571201A
CN110571201A CN201910932010.1A CN201910932010A CN110571201A CN 110571201 A CN110571201 A CN 110571201A CN 201910932010 A CN201910932010 A CN 201910932010A CN 110571201 A CN110571201 A CN 110571201A
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China
Prior art keywords
layer
plastic package
heat dissipation
heat
carrier plate
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CN201910932010.1A
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Inventor
雷珍南
崔成强
林挺宇
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co Ltd
Guangdong Fozhixin Microelectronics Technology Research Co Ltd
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Priority to CN201910932010.1A priority Critical patent/CN110571201A/en
Publication of CN110571201A publication Critical patent/CN110571201A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

Abstract

The invention discloses a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and a preparation method thereof, wherein the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure comprises the following components: the chip plastic package body comprises a support plate, a wafer with copper columns and a plastic package layer, wherein the wafer with the copper columns is attached to two sides of the support plate through a heat dissipation layer; the seed layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and extends into the through hole to cover the inner wall of the through hole; the conductive copper column is positioned in the through hole and electrically connected with the heavy wiring layer on the seed layer, and the heavy wiring layer is provided with a bonding pad area and a non-bonding pad area; the solder mask layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and covers the non-soldering disc area of the rewiring layer; and the metal bump is welded with the bonding pad area of the redistribution layer. The invention has small overall dimension, large three-dimensional stacking density and good heat dissipation effect, and can effectively reduce warpage.

Description

high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof
Technical Field
the invention relates to the technical field of electronic packaging, in particular to a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and a preparation method thereof.
background
In recent years, high density, multiple functions, low power consumption and miniaturization become the trend of semiconductor package development, and three-dimensional fan-out type wafer level package can better meet the development requirement and the requirements of terminal market on product efficiency and volume. However, most of the existing three-dimensional fan-out packages are packaged in a stacking mode, the fan-out packages adopting the plastic package process are very difficult to control the warpage, and the solutions in the prior art also reduce the warpage from the aspects of material characteristics and plastic package final forming.
in the existing chip heat dissipation technology, multiple heat dissipation functions are set in a traditional packaging mode, meanwhile, the heat dissipation mode is usually based on a heat dissipation structure added on a chip after the chip is subjected to plastic packaging, and due to the fact that a layer of plastic packaging material (usually epoxy resin and other materials) is arranged in the middle of the chip, the heat conductivity is poor, and the heat dissipation efficiency of the chip is low.
in summary, the conventional fan-out package has the problems of high warpage and insufficient heat dissipation capability, and the quality and performance of the semiconductor chip are seriously affected.
disclosure of Invention
The invention aims to provide a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and a preparation method thereof, which can effectively reduce the warping degree of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and can quickly derive heat dissipated by a wafer.
In order to achieve the purpose, the invention adopts the following technical scheme:
On the one hand, provide a high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic envelope structure, include:
The chip plastic package body comprises a carrier plate, wafers with copper columns and plastic package layers, wherein the wafers with the copper columns are attached to two sides of the carrier plate through heat dissipation layers, the wafers are packaged in the plastic package layers, a plurality of through holes are formed in the chip plastic package body along the thickness direction of the chip plastic package body, and the copper columns of the wafers face to one side away from the carrier plate and are exposed out of the plastic package layers;
The seed layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and extends into the through hole to cover the inner wall of the through hole;
The conductive copper column is positioned in the through hole and electrically connected with the redistribution layer on the seed layer, and the redistribution layer is provided with a bonding pad area and a non-bonding pad area;
the solder mask layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and covers the non-soldering disc area of the rewiring layer;
And the metal bump is welded with the bonding pad area of the redistribution layer.
As a preferred scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the heat dissipation layer comprises a heat dissipation adhesive pasted on the support plate and a heat dissipation metal layer pasted on the heat dissipation adhesive, the heat dissipation metal layer is of a hollow structure, and the wafer is pasted on the heat dissipation adhesive and packaged in the plastic package layer.
As a preferred scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the heat-dissipation metal layer is any one of a copper foil, an aluminum foil, a silver foil and a gold foil.
As a preferred scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the seed layer comprises a titanium metal layer located on the plastic package layer and the inner wall of the through hole and a copper metal layer located on the titanium metal layer.
As an optimal scheme of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the solder mask is a photosensitive ink layer.
on the other hand, the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure comprises the following steps:
S10, providing a carrier plate, a heat dissipation layer and a plurality of wafers with copper columns, enabling the front faces of the wafers to face away from the carrier plate, respectively attaching the wafers to two sides of the carrier plate through the heat dissipation layer, and packaging and fixing the wafers by adopting a plastic package material to obtain a chip plastic package body;
S20, opening the chip plastic package body to form a through hole penetrating through the chip plastic package body;
s30, seed layers are manufactured on the two sides of the chip plastic package body and on the inner wall of the through hole;
S40, manufacturing a conductive copper pillar in the through hole and manufacturing a redistribution layer electrically connected with the conductive copper pillar on the seed layer;
and S50, providing a metal bump, manufacturing a solder mask layer on the redistribution layer, and exposing the pad area of the redistribution layer and electrically connecting the pad area with the metal bump.
as a preferable scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S10 specifically includes the following steps:
s11, providing a carrier plate and a first heat dissipation adhesive, and attaching the first heat dissipation adhesive to a first side of the carrier plate along the thickness direction of the carrier plate;
s12, providing a first heat dissipation metal layer with a hollow structure, and attaching the first heat dissipation metal layer to the first heat dissipation adhesive;
s13, providing a plurality of first wafers with copper columns, and attaching the front surfaces of the first wafers, facing away from one side of the carrier plate, to the first heat-dissipation glue;
s14, packaging the first wafer by adopting a plastic package material, and forming a first plastic package layer after the plastic package material is solidified;
s15, providing a second heat dissipation adhesive, and attaching the second heat dissipation adhesive to a second side of the carrier plate, which is opposite to the first side;
S16, providing a second heat dissipation metal layer with a hollow structure, and attaching the second heat dissipation metal layer to the second heat dissipation adhesive;
S17, providing a plurality of second wafers with copper columns, and attaching the front surfaces of the second wafers facing away from the carrier plate to the second heat-dissipation glue;
S18, packaging the second wafer by adopting a plastic package material, and forming a second plastic package layer after the plastic package material is solidified;
and S19, grinding the first plastic package layer and the second plastic package layer to enable the copper column of the wafer to be flush with the ground surface of the first plastic package layer, and the copper column of the second wafer 12 to be flush with the ground surface of the second plastic package layer.
As a preferable scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S40 specifically includes the following steps:
S41, manufacturing a conductive copper pillar in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer;
s42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
s43, forming a pattern which enables part of the copper plating layer to be exposed out of the photosensitive dry film on the photosensitive dry film through exposure and development processing;
s44, etching the copper plating layer and the seed layer exposed out of the photosensitive dry film to form the rewiring layer electrically connected with the conductive copper pillar;
And S45, removing the residual photosensitive dry film.
As a preferable scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the step S50 specifically includes the following steps:
S51, coating photosensitive ink on the surfaces of the chip plastic package body and the rewiring layer;
S52, forming a solder mask layer exposing the pad area of the rewiring layer through exposure, development and curing;
And S53, providing a metal bump, and implanting the metal bump into the pad area to be electrically connected with the redistribution layer.
As a preferable scheme of the preparation method of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, the first heat-dissipation glue and the second heat-dissipation glue have the same components and respectively comprise graphene, silica gel, silicone grease, a methyl vinyl polysiloxane mixture, a methyl hydrogen polysiloxane mixture and aluminum oxide.
The invention has the beneficial effects that: the invention respectively pastes a heat dissipation layer on two side surfaces of a carrier plate along the thickness direction of the carrier plate, pastes a wafer with copper columns on the heat dissipation layer and encapsulates the wafer in a plastic packaging layer to form a chip plastic packaging body; the chip plastic package is internally provided with the through holes for electroplating the conductive copper columns, the circuit communication of the wafers on the two sides of the carrier plate is realized through the conductive copper columns, the heat of the wafers is quickly led out of the plastic package layer through the heat dissipation layer, the wafers are respectively packaged on the two sides of the carrier plate, and the carrier plate does not need to be detached after the packaging is completed, so that the warping can be effectively reduced. Compared with the prior art, the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure has the advantages of small overall dimension, large three-dimensional stacking density and good heat dissipation effect, can keep the operation smoothness of the functional chip, further improves the quality and performance of the semiconductor chip, and can effectively reduce warpage.
drawings
in order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic cross-sectional view of an intermediate product with a heat dissipation adhesive attached to one side of a carrier according to an embodiment of the invention.
fig. 2 is a first schematic cross-sectional view of an intermediate product of a heat dissipation metal layer attached to a heat dissipation adhesive according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of an intermediate product of a heat dissipation metal layer attached to a heat dissipation adhesive according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of an intermediate product of a copper pillar-containing wafer bonded to a heat-dissipating adhesive according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of an intermediate product in which a wafer with copper pillars is packaged in a plastic package layer according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product with another heat dissipation layer attached to another side of a carrier according to an embodiment of the invention.
FIG. 7 is a cross-sectional view of another intermediate product of a copper pillar-containing die attached to another heat sink layer according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of an intermediate product in which a wafer with copper pillars is packaged in another plastic package layer according to an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of an intermediate product after polishing the plastic sealing layers on two sides of the carrier according to an embodiment of the invention.
Fig. 10 is a schematic cross-sectional view of an intermediate product after drilling a chip molding package and manufacturing a seed layer according to an embodiment of the invention.
fig. 11 is a schematic cross-sectional view of an intermediate product after the EDL layer is fabricated according to an embodiment of the present invention.
fig. 12 is a schematic cross-sectional view of a product after a solder mask layer and a metal bump are fabricated according to an embodiment of the invention.
in the figure:
1. a chip plastic package body; 11. a carrier plate; 12. a wafer; 13. a plastic packaging layer; 14. heat dissipation glue; 15. a heat dissipation metal layer;
2. a seed layer;
3. a conductive copper pillar;
4. a rewiring layer;
5. A solder resist layer;
6. and a metal bump.
Detailed Description
the technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
in the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
unless specifically stated otherwise, various raw materials used in the preparation method of the high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure of the present invention are commercially available or prepared according to conventional methods in the art.
As shown in fig. 12, an embodiment of the present invention provides a high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, including:
The chip plastic package body 1 comprises a carrier plate 11, a wafer 12 with copper columns and a plastic package layer 13, wherein the wafer 12 is attached to two sides of the carrier plate 11 through a heat dissipation layer, the wafer 12 is packaged in the plastic package layer 13, a plurality of through holes are formed in the chip plastic package body 1 along the thickness direction of the chip plastic package body, and the copper columns of the wafer 12 face to one side away from the carrier plate 11 and are exposed out of the plastic package layer 13;
the seed layer 2 is positioned on one side of the plastic packaging layer 13, which is far away from the carrier plate 11, and extends into the through hole to cover the inner wall of the through hole;
the conductive copper columns 3 are positioned in the through holes and are electrically connected with the redistribution layer 4 on the seed layer 2, and the redistribution layer 4 is provided with a bonding pad area and a non-bonding pad area;
the solder mask layer 5 is positioned on one side of the plastic package layer 13, which is far away from the carrier plate 11, and covers the non-soldering-pad area of the rewiring layer 4;
And the metal bump 6 is welded with the pad area of the heavy wiring layer 4.
in the present embodiment, unless otherwise specified, the term "cover" refers to an outer surface that surrounds a component without contacting other components. For example, the solder resist layer 5 covers the non-pad area of the redistribution layer 4, which means that the solder resist layer 5 covers the non-pad area of the redistribution layer 4 and the surface of the seed layer 2 which is not in contact with each other.
alternatively, the metal bump 6 is a solder, a silver solder, or a gold-tin alloy solder, and the specific shape of the metal bump 6 is not limited.
in this embodiment, heat dissipation layers are respectively attached to two side surfaces of the carrier plate 11 along the thickness direction thereof, and the wafer 12 with copper pillars is attached to the heat dissipation layers and packaged in the plastic package layer 13 to form the chip plastic package body 1; the chip plastic package body 1 is internally provided with a through hole for electroplating the conductive copper column 3, the circuit communication of the wafers 12 at two sides of the carrier plate 11 is realized through the conductive copper column 3, and the heat of the wafers 12 is quickly led out to the outside of the plastic package layer 13 through the heat dissipation layer. Compared with the prior art, the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is small in overall dimension, large in three-dimensional stacking density and good in heat dissipation effect, can keep the running smoothness of the wafer 12, further improves the quality and performance of a semiconductor chip, and can effectively reduce warping.
further, the heat dissipation layer includes a heat dissipation adhesive 14 attached to the carrier plate 11 and a heat dissipation metal layer 15 attached to the heat dissipation adhesive 14, the heat dissipation metal layer 15 is a hollow structure, and the wafer 12 is attached to the heat dissipation adhesive 14 and is packaged in the plastic package layer 13. Because the heat dissipation metal layer 15 is a hollow structure, the heat dissipation metal layer 15 can be directly embedded into the heat dissipation adhesive 14, so that the heat dissipation metal layer 15 does not protrude from the surface of the heat dissipation adhesive 14, and the wafer 12 can be attached to the heat dissipation adhesive 14, thereby facilitating the subsequent packaging treatment.
alternatively, the heat dissipation metal layer 15 is any one of a copper foil, an aluminum foil, a silver foil, or a gold foil, but is not limited thereto, and any metal layer having high thermal conductivity is suitable for the present invention.
the seed layer 2 comprises a titanium metal layer located on the plastic package layer 13 and on the inner wall of the through hole, and a copper metal layer located on the titanium metal layer. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the plastic package layer 13 through the titanium metal layer.
Of course, the seed layer 2 of the present embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure or a structure having two or more layers. The material of the seed layer 2 is not limited to a laminated combination of two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer 4 can be stably attached to the chip plastic package body 1, which is not described in detail.
in this embodiment, the solder resist layer 5 is a photosensitive ink layer. Photosensitive ink is used as the solder mask layer 5, so that the function of protecting the rewiring layer 4 can be achieved, and part of the seed layer 2 and the copper plating layer can be removed through exposure, development and etching.
the redistribution layer 4 has at least one layer structure, that is, can be designed into one layer, two layers, three layers or even more than three layers according to actual requirements.
The copper column of the wafer 12 is flush with the surface of the plastic package layer 13, so that the subsequent heat dissipation glue 14 can be stably attached to the surface of the plastic package layer 13 and covers the copper column of the wafer 12.
optionally, the carrier 11 is made of BT, FR4, FR5, PP, EMC, ABF or PI.
Optionally, the material of the Molding layer 13 includes polyimide, silicone, and EMC (Epoxy Molding Compound), which is preferable in this embodiment, that is, the Molding layer 13 is an Epoxy resin encapsulation layer, and can make the wafer 12 stably adhere to the carrier 11, so as to protect the wafer 12.
as shown in fig. 1 to 12, an embodiment of the present invention further provides a method for manufacturing a high heat dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure, including the following steps:
S10, providing a carrier 11, a heat dissipation layer and a plurality of wafers 12 with copper pillars, making the front surfaces of the wafers 12 face a direction away from the carrier 11, respectively attaching the wafers 12 to two sides of the carrier 11 through the heat dissipation layer, and packaging and fixing the wafers 12 by using a molding compound to obtain a chip molding compound 1, referring to fig. 1-9;
s20, opening the chip plastic package body 1 to form a through hole penetrating through the chip plastic package body 1; specifically, the chip plastic package body 1 is subjected to hole opening processing through laser, and Plasma cleaning is needed after the hole opening processing, so that residues generated in the laser hole opening process are removed;
S30, manufacturing seed layers 2 on two sides of the chip plastic package body 1 and the inner wall of the through hole, and referring to FIG. 10;
S40, forming a conductive copper pillar 3 in the via hole, and forming a redistribution layer 4 on the seed layer 2 and electrically connected to the conductive copper pillar 3, referring to fig. 11;
S50, providing a metal bump 6, and fabricating a solder mask layer 5 on the redistribution layer 4, so that the pad region of the redistribution layer 4 is exposed and electrically connected to the metal bump 6, as shown in fig. 12.
The chip 12 is attached to the two sides of the carrier 11 through the heat dissipation layers respectively, and the chip 12 is packaged on the two sides of the carrier 11 respectively by adopting a plastic package material, so that the heat dissipation rate of the chip 12 is improved; and then, hole opening treatment is carried out in the prepared chip packaging body 1, and a seed layer 2 and a conductive copper column 3 are prepared in the formed through hole so as to realize circuit conduction of the rewiring layers 4 corresponding to the wafers 12 on the two sides of the carrier plate 11, the carrier plate does not need to be detached after the prepared high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is divided, and the warping problem of the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is effectively solved.
in this embodiment, the molding compound used for encapsulating the chip 12 on both sides of the carrier 11 is completely the same, so as to further reduce warpage.
Further, step S10 specifically includes the following steps:
S11, providing a carrier plate 11 and a heat dissipation glue 14 (first heat dissipation glue), and attaching the heat dissipation glue 14 to a first side of the carrier plate 11 along the thickness direction thereof, referring to fig. 1; the material of the carrier 11 may be one of BT (bimoleimide triazineserin), FR4, FR5, PP, EMC, ABF or PI material, but is not limited thereto.
s12, providing a heat dissipation metal layer 15 (a first heat dissipation metal layer) with a hollow structure, and attaching the heat dissipation metal layer 15 to the heat dissipation adhesive 14, referring to fig. 2 and 3; a in fig. 3 refers to the mounting position of the wafer 12.
s13, providing a plurality of wafers 12 with copper pillars, and attaching the front side of the wafer 12 facing away from the carrier 11 to the heat dissipation adhesive 14, referring to fig. 4;
S14, performing a packaging process on the wafer 12 by using a molding compound, and forming a molding layer 13 (a first molding layer) after the molding compound is cured, referring to fig. 5;
s15, providing another heat dissipation glue 14 (second heat dissipation glue), and attaching the heat dissipation glue 14 to a second side of the carrier 11 opposite to the first side;
S16, providing another heat dissipation metal layer 15 (second heat dissipation metal layer) with a hollow structure, and attaching the heat dissipation metal layer 15 to the heat dissipation adhesive 14, referring to fig. 6;
s17, providing a plurality of wafers 12 (second wafers) with copper pillars, and attaching the front side of the wafer 12 facing away from the carrier 11 to the heat dissipation adhesive 14, referring to fig. 7;
S18, performing a packaging process on the wafer 15 by using a molding compound, and forming a molding layer 13 (a second molding layer) after the molding compound is cured, referring to fig. 8.
s19, the two plastic-sealed layers 13 (the first plastic-sealed layer and the second plastic-sealed layer) are polished to make the copper pillars of the wafers 12 (the first wafer and the second wafer) on the two sides of the carrier 11 flush with the surfaces of the polished plastic-sealed layers 13, respectively, as shown in fig. 9.
Further, in step S40 in this embodiment, the method for manufacturing the redistribution layer 4 by a subtractive method specifically includes the following steps:
S41, manufacturing a conductive copper pillar 3 in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer 2;
s42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
S43, forming a pattern which enables part of the copper plating layer to be exposed out of the photosensitive dry film on the photosensitive dry film through exposure and development processing;
s44, etching the copper plating layer exposed out of the photosensitive dry film and the seed layer 2 to form the redistribution layer 4 electrically connected to the conductive copper pillar 3;
and S45, removing the residual photosensitive dry film.
The method for preparing the conductive copper pillar 3 and the copper plating layer by electroplating, the method for etching the seed layer 2 and the copper plating layer, and the like are all the prior art, and detailed description is omitted.
Further, step S50 specifically includes the following steps:
s51, coating photosensitive ink on the surfaces of the chip plastic package body 1 and the rewiring layer 4;
S52, forming a solder mask layer 5 exposing the pad area of the rewiring layer 4 through exposure, development and curing;
and S53, providing a metal bump 6, and implanting the metal bump 6 into the pad region to be electrically connected with the redistribution layer 4.
In this embodiment, the first heat dissipation adhesive and the second heat dissipation adhesive are permanent heat dissipation adhesives, and both include graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, and aluminum oxide.
In another embodiment of the present invention, it is basically the same as the above embodiment, except that the redistribution layer 4 is fabricated by a semi-additive method, which is not described in detail.
the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure manufactured based on the fan-out type packaging technology not only can realize larger stacking density in the three-dimensional direction and smaller overall dimension, but also can simultaneously arrange heat dissipation glue and cover heat dissipation metal layers on the back surfaces of a plurality of wafers within the size range of hundreds of millimeters, greatly improve the heat dissipation performance of the wafers, further improve the quality and performance of semiconductor chips, and also can effectively reduce warpage.
the above examples are only intended to illustrate the detailed process of the present invention, and the present invention is not limited to the above detailed process, i.e., it is not intended that the present invention necessarily depends on the above detailed process for its implementation. It is understood by those skilled in the art that any modification of the present invention, equivalent substitutions of the raw materials of the product of the present invention and the addition of auxiliary components, selection of specific modes, etc., are within the scope and disclosure of the present invention.

Claims (10)

1. the utility model provides a high heat dissipation fan-out type three-dimensional isomerism double-sided plastic envelope structure which characterized in that includes:
the chip plastic package body comprises a carrier plate, wafers with copper columns and plastic package layers, wherein the wafers with the copper columns are attached to two sides of the carrier plate through heat dissipation layers, the wafers are packaged in the plastic package layers, a plurality of through holes are formed in the chip plastic package body along the thickness direction of the chip plastic package body, and the copper columns of the wafers face to one side away from the carrier plate and are exposed out of the plastic package layers;
the seed layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and extends into the through hole to cover the inner wall of the through hole;
The conductive copper column is positioned in the through hole and electrically connected with the redistribution layer on the seed layer, and the redistribution layer is provided with a bonding pad area and a non-bonding pad area;
the solder mask layer is positioned on one side of the plastic packaging layer, which is far away from the carrier plate, and covers the non-soldering disc area of the rewiring layer;
and the metal bump is welded with the bonding pad area of the redistribution layer.
2. The high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 1, wherein the heat dissipation layer comprises a heat dissipation adhesive pasted on the carrier board and a heat dissipation metal layer pasted on the heat dissipation adhesive, the heat dissipation metal layer is a hollow structure, and the wafer is pasted on the heat dissipation adhesive and packaged in the plastic package layer.
3. the fan-out type three-dimensional heterogeneous double-sided plastic package structure with high heat dissipation according to claim 2, wherein the heat dissipation metal layer is any one of a copper foil, an aluminum foil, a silver foil or a gold foil.
4. the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 1, wherein the seed layer comprises a titanium metal layer located on the plastic package layer and the inner wall of the through hole and a copper metal layer located on the titanium metal layer.
5. The high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 1, wherein the solder resist layer is a photosensitive ink layer.
6. A preparation method of a high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure is characterized by comprising the following steps:
s10, providing a carrier plate, a heat dissipation layer and a plurality of wafers with copper columns, enabling the front faces of the wafers to face away from the carrier plate, respectively attaching the wafers to two sides of the carrier plate through the heat dissipation layer, and packaging and fixing the wafers by adopting a plastic package material to obtain a chip plastic package body;
s20, opening the chip plastic package body to form a through hole penetrating through the chip plastic package body;
S30, seed layers are manufactured on the two sides of the chip plastic package body and on the inner wall of the through hole;
s40, manufacturing a conductive copper pillar in the through hole and manufacturing a redistribution layer electrically connected with the conductive copper pillar on the seed layer;
and S50, providing a metal bump, manufacturing a solder mask layer on the redistribution layer, and exposing the pad area of the redistribution layer and electrically connecting the pad area with the metal bump.
7. The method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 6, wherein the step S10 specifically comprises the following steps:
S11, providing a carrier plate and a first heat dissipation adhesive, and attaching the first heat dissipation adhesive to a first side of the carrier plate along the thickness direction of the carrier plate;
s12, providing a first heat dissipation metal layer with a hollow structure, and attaching the first heat dissipation metal layer to the first heat dissipation adhesive;
s13, providing a plurality of first wafers with copper columns, and attaching the front surfaces of the first wafers, facing away from one side of the carrier plate, to the first heat-dissipation glue;
S14, packaging the first wafer by adopting a plastic package material, and forming a first plastic package layer after the plastic package material is solidified;
S15, providing a second heat dissipation adhesive, and attaching the second heat dissipation adhesive to a second side of the carrier plate, which is opposite to the first side;
s16, providing a second heat dissipation metal layer with a hollow structure, and attaching the second heat dissipation metal layer to the second heat dissipation adhesive;
s17, providing a plurality of second wafers with copper columns, and attaching the front surfaces of the second wafers facing away from the carrier plate to the second heat-dissipation glue;
S18, packaging the second wafer by adopting a plastic package material, and forming a second plastic package layer after the plastic package material is solidified;
s19, grinding the first plastic package layer and the second plastic package layer to enable the copper column of the wafer to be flush with the surface of the first plastic package layer after grinding, and the copper column of the second wafer to be flush with the surface of the second plastic package layer after grinding.
8. the method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 7, wherein the step S40 specifically comprises the following steps:
S41, manufacturing a conductive copper pillar in the through hole through electroplating treatment, and manufacturing a copper plating layer on the seed layer;
S42, providing a photosensitive dry film, and attaching the photosensitive dry film to the copper plating layer;
s43, forming a pattern which enables part of the copper plating layer to be exposed out of the photosensitive dry film on the photosensitive dry film through exposure and development processing;
s44, etching the copper plating layer and the seed layer exposed out of the photosensitive dry film to form the rewiring layer electrically connected with the conductive copper pillar;
And S45, removing the residual photosensitive dry film.
9. The method for preparing the high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure according to claim 7, wherein the step S50 specifically comprises the following steps:
S51, coating photosensitive ink on the surfaces of the chip plastic package body and the rewiring layer;
S52, forming a solder mask layer exposing the pad area of the rewiring layer through exposure, development and curing;
And S53, providing a metal bump, and implanting the metal bump into the pad area to be electrically connected with the redistribution layer.
10. The method for preparing the fan-out type three-dimensional heterogeneous double-sided plastic package structure with high heat dissipation according to claim 7, wherein the first heat dissipation glue and the second heat dissipation glue have the same components and both comprise graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture and aluminum oxide.
CN201910932010.1A 2019-09-29 2019-09-29 high-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure and preparation method thereof Pending CN110571201A (en)

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CN113675093A (en) * 2021-07-14 2021-11-19 复旦大学 Packaging design and preparation method of double-sided plastic-packaged heat dissipation structure
CN113675174A (en) * 2021-08-17 2021-11-19 青岛佳恩半导体科技有限公司 Preparation method for improving Mark point morphology of power device
WO2023060496A1 (en) * 2021-10-14 2023-04-20 华为技术有限公司 Chip and manufacturing method therefor, and electronic device
CN116818063A (en) * 2023-08-30 2023-09-29 江铃汽车股份有限公司 Method and device for detecting coating quality of automobile chip heat dissipation glue and readable storage medium

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CN107611114A (en) * 2017-07-31 2018-01-19 华为技术有限公司 A kind of embedded substrate
CN108650788A (en) * 2018-05-16 2018-10-12 维沃移动通信有限公司 A kind of circuit module and terminal device
CN210575902U (en) * 2019-09-29 2020-05-19 广东佛智芯微电子技术研究有限公司 High-heat-dissipation fan-out type three-dimensional heterogeneous double-sided plastic package structure

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CN113675093A (en) * 2021-07-14 2021-11-19 复旦大学 Packaging design and preparation method of double-sided plastic-packaged heat dissipation structure
CN113675174A (en) * 2021-08-17 2021-11-19 青岛佳恩半导体科技有限公司 Preparation method for improving Mark point morphology of power device
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