CN110557278B - Multi-unit communication test system realized based on FPGA - Google Patents

Abstract

The invention discloses a multi-unit communication test system realized based on an FPGA (field programmable gate array), which comprises a resource board, a PLC (programmable logic controller) module and an upper computer. The resource board comprises an FPGA circuit, a driving circuit, an Ethernet module, an alternating current bus analog circuit, a direct current power supply circuit, a clock circuit and a reset circuit; the PLC module comprises 20 customer terminal units PLC1-PLC20, each equipped with a work light LED1-LED20 and a switch S1-S20, and 1 server subunit PLC 21; the client terminal unit, the working display lamp and the server subunit of the PLC module are connected with a driving circuit of the resource board, the driving circuit, the clock circuit and the reset circuit are connected with the FPGA circuit, and the FPGA circuit is connected with the Ethernet module. The invention has the advantages of large serial port number, high communication speed, high test efficiency and instant programming control through the upper computer, realizes the communication among all PLC units and between the upper computer and the PLC units based on the FPGA chip, and realizes the purpose of simulating the communication environment required by the test to the maximum extent.

Description

Multi-unit communication test system realized based on FPGA

Technical Field

The invention belongs to the technical field of network communication, and particularly relates to a structure and a method for performing data communication among PLC units and between an upper computer and the PLC units through an FPGA chip.

Background

The high-speed rail technology is a new industry which is rapidly developed at present, and the safe and reliable operation of the high-speed rail technology is required to be ensured, so that good data exchange communication cannot be achieved. Generally speaking, communication and test on a high-speed rail directly are not practical, the cost is high, and a certain technical means is needed to simulate the communication environment of the high-speed rail and test the communication condition and the reliability. With the development of scientific technology, particularly communication technology and network transmission technology, communication simulation of the high-speed rail multi-section car is possible.

The traditional communication simulation test technology is mainly characterized in that a microcomputer with a CPU structure such as a singlechip controls and detects communication, and has the advantages that programming can be performed through computer languages such as assembly language, C language and the like, and convenience is brought to the operation. However, in the field of high-speed rail communication simulation test, the defects of the method are that the number of serial ports is not enough, the communication requirements of a plurality of carriages and trains of the high-speed rail cannot be met, and meanwhile, the single chip adopts a single-thread sequential execution structure, so that the operation speed is slow, and the requirement of instant communication cannot be met.

Disclosure of Invention

In view of the above, the present invention provides a multi-unit communication test system based on FPGA, which adopts FPGA capable of executing in parallel to replace a single chip as a main control chip of a communication circuit, so as to solve the problems of insufficient serial number and insufficient communication speed, and meanwhile, FPGA can be controlled by an upper computer program, so that flexibility and adaptability of the system are improved, and human-computer interaction is also enhanced.

In addition, the invention also reduces the specific environment of the high-speed rail communication by technical means of simulating the line parameters of the communication among the units of the high-speed rail by using the resistor, the inductor and the capacitor, and the like, thereby achieving the purpose of maximally simulating the communication environment required by the test.

The purpose of the invention is realized by at least one of the following technical solutions.

A multi-unit communication test system based on FPGA comprises a resource board, a PLC module and an upper computer.

The resource board mainly comprises an FPGA circuit, a driving circuit, an Ethernet module, an alternating current bus analog circuit, a direct current power supply circuit, a clock circuit and a reset circuit;

the PLC module comprises 20 client terminal units PLC1-PLC20, 20 work display lamps LED1-LED20, 20 switches S1-S20 and 1 server subunit PLC21, wherein one client terminal unit corresponds to one work display lamp, and the client terminal units and the server subunits belong to the PLC units;

furthermore, the upper computer has the functions of selecting a working mode, testing messages, controlling subordinate test boards, displaying the running state and counting the packet loss rate.

Further, the client terminal unit PLC1-PLC20, the work display lamp LED1-LED20 and the server subunit PLC21 of the PLC module are connected with a driving circuit of the resource board;

furthermore, the driving circuit, the clock circuit and the reset circuit are connected to the FPGA circuit;

further, the FPGA circuit is connected to the Ethernet module;

furthermore, the alternating current bus analog circuit comprises a resistor, a capacitor and an inductance element, the power supply of the alternating current bus analog circuit is introduced by the commercial power of an external AC220V, and each client terminal unit and each server subunit are hung on the alternating current bus analog circuit;

further, the direct current power supply circuit is connected to a direct current part in the circuit and supplies power to the direct current part; the direct current part comprises the PLC module, an FPGA circuit, a driving circuit, an Ethernet module, a clock circuit and a reset circuit.

Furthermore, the alternating current bus circuit is provided with a live wire bus and a zero line bus, and each client terminal unit and each server subunit in the PLC module are sequentially hung on the buses. A resistor, an inductor and a capacitor are respectively connected in series on the live wire and the zero line between two adjacent PLC units, and the capacitor is connected in parallel to simulate an actual model when a rail transmits signals.

Further, the direct current power supply is composed of a switch power supply module (DCDC) and a linear regulator (LDO), and converts direct current power supply of the resource board into power supply required by the PLC module, the FPGA circuit, the driving circuit, the Ethernet module, the clock circuit and the reset circuit.

Furthermore, the upper computer can control the data communication test process of the PLC module by controlling the FPGA chip in the FPGA circuit through the FPGA circuit and the Ethernet module. The TX and RX ports of each PLC unit are connected with a serial port of a driving circuit through a signal wire, and the serial port of the driving circuit is connected with a serial port of an FPGA circuit to realize the communication between the PLC unit and the FPGA circuit; and the PLC units complete communication through an alternating current bus analog circuit.

At least the following two communication modes are required to realize the complete test process:

firstly, communication between FPGA circuit and server subunit: the upper computer transmits the data packet to the FPGA circuit through the Ethernet module; next, the FPGA circuit unpacks the data packet and transmits the data to a corresponding PLC client terminal unit through the serial port of the FPGA circuit; the client terminal unit gathers the received data to the server subunit through an alternating current power supply circuit; the server subunit sends all the received data to the FPGA circuit through the serial port of the FPGA circuit; and finally, packaging the received data by the FPGA circuit, counting the sent data and the received data, and transmitting the data packets and the counting result to the upper computer through the Ethernet module, so that the upper computer can calculate the packet loss rate.

Another communication mode is the communication between the FPGA circuit and the client terminal unit: the upper computer transmits the data packet to the FPGA circuit through the Ethernet module; next, the FPGA circuit unpacks the data packet and transmits the data to the PLC server subunit through a serial port; the server subunit broadcasts data to all the client terminal units through the alternating current power supply line, and the client terminal units transmit the received data to the FPGA circuit through the serial ports; and finally, the FPGA circuit also packs data, counts the data receiving and sending conditions, and sends the result to the upper computer to calculate the packet loss rate.

A calculation formula of the packet loss rate X:

through the test results of the two communication modes and the calculation of the corresponding packet loss rate, the function of the PLC receiving and sending data, the quality of data communication and the specific problems can be analyzed.

The invention has the following beneficial effects:

compared with the traditional communication simulation test technology which utilizes microcomputers with CPU structures such as a single chip microcomputer, the scheme makes full use of the characteristics of flexible FPGA design, strong expandability, large serial port quantity, high communication speed, high test efficiency, programmable control through an upper computer and the like, improves the communication test speed, shortens the test time, can simulate various test conditions, and fulfills the aim of simulating the communication environment required by the test to the maximum extent.

The PLC units can be expanded, a resource board with 20 PLC units is newly added and is connected with the original resource board through a serial port, and therefore the number of the client terminal units can reach 40 at most; if the FPGA chip with more serial ports is adopted, the number of the client terminal units can be further increased, and the expansion of the client terminal units meets various testing requirements.

According to the scheme, the resistors, the capacitors and the inductors are configured on each PLC subunit, an external AC220V power supply supplies power to each PLC unit through the resistors, the capacitors and the inductors, and meanwhile, data can be transmitted among the PLC units through a line, which is a rough estimation on electrical parameters of a section of 3 kilometer high-speed rail power supply line, so that a communication system is closer to a real scene, and the reliability of simulation test is enhanced.

Description of the drawings:

FIG. 1 is a flow chart of the design of the present communication test system;

FIG. 2 is a schematic diagram of an Ethernet module;

FIG. 3 is a schematic diagram of a driving circuit;

FIG. 4 is a schematic diagram of a DC power supply circuit;

FIG. 5 is a schematic diagram of a PLC module;

fig. 6 is a schematic diagram of a reset circuit and a clock circuit.

Detailed Description

In order to better explain the content of the invention, the concrete implementation method of the invention is described with reference to the attached drawings.

Example (b):

as shown in fig. 1, a multi-unit communication test system implemented based on an FPGA includes a resource board, a PLC module, and an upper computer. The resource board mainly comprises an FPGA circuit, a driving circuit, an Ethernet module, an alternating current bus analog circuit, a direct current power supply circuit, a clock circuit and a reset circuit; the PLC module comprises 20 client terminal units PLC1-PLC20, 20 work display lamps LED1-LED20, 20 switches S1-S20 and 1 server subunit PLC21, wherein one client terminal unit corresponds to one work display lamp, and the client terminal units and the server subunits belong to the PLC units.

In the resource board, the driving circuit, the clock circuit and the reset circuit are connected to the FPGA circuit; the FPGA circuit is connected to an Ethernet module.

The client terminal unit PLC1-PLC20, the work display lamp LED1-LED20 and the server subunit PLC21 of the PLC module are connected with a driving circuit in the resource board; the TX and RX ports of each PLC unit are connected with a serial port of a driving circuit through a signal wire, and the serial port of the driving circuit is connected with a serial port of an FPGA circuit to realize the communication between the PLC unit and the FPGA circuit; and the PLC units complete communication through an alternating current bus analog circuit.

The PLC module is a tested piece participating in testing. Wherein customer terminal unit and server subunit all can be dismantled and change, and the TX and RX mouth of every PLC unit pass through the signal line and link to each other with the drive circuit serial ports, prevents the influence of a PLC unit trouble to other circuits, and simultaneously, the use of dismantling the change unit also makes the test to PLC unit data communication more changeable, can simulate multiple different communication condition. The PLC units are arranged on the resource board according to the label sequence and the trend of the alternating current power supply circuit.

Fig. 2 is a schematic diagram of an ethernet module, which implements communication between an upper computer and an FPGA circuit. The ethernet module in this embodiment adopts an MO series-based embedded serial port-to-ethernet module, the model of which is USR-TCP232-T2, and an optimized TCP/IP protocol stack is integrated inside the module, so that the network function of the embedded device can be easily completed. According to the specific situation, the communication between the FPGA circuit and the upper computer can also be realized in other forms, such as a wifi module replacing the USR-TCP232-T2 module. The VCC pin of the USR-TCP232-T2 module is connected with a +3.3V power supply; the GND pin is connected with the ground; RST, TXD and RXD pins are connected with user I/O pins of the FPGA chip, wherein RST is a reset port, TXD is a sending data port, and RXD is a receiving data port.

The FPGA circuit in the embodiment adopts an FPGA chip with the model of M2S010-FG484, and compared with a traditional single chip microcomputer, the FPGA has a parallel execution structure, can execute a plurality of tasks simultaneously, improves the running speed and has the advantage of good real-time performance. The FPGA chip of the FPGA circuit in this embodiment adopts DDR2 memory technology standard, and has a stronger memory pre-reading capability compared with the conventional DDR standard. Meanwhile, the DDR2 memory adopts an FBGA packaging form, which is different from a widely-used TSOP/TSOP-II packaging form, and the FBGA packaging can provide better electrical performance and heat dissipation, so that the DDR2 has higher and more stable operating frequency.

User I/O pins in the FPGA chip are connected with RST, TXD and RXD pins of the USR-TCP232-T2 module, 1B-7B pins of ULN2003A and A1-A8 pins of TXS 0108; the power supply pin is connected with a +5V power supply; the power-on reset pin is connected with the MR/pin of the MAX 811; the clock pin is connected to the ClkOut pin of Y2.

Fig. 3 is a schematic diagram of a driving circuit, which is used for amplifying signals transmitted to the PLC module by the FPGA chip to ensure signal transmission quality. In this embodiment, the model of the driving circuit chip connected to the operation indicator light is ULN2003A, and the model of the driving circuit chip connected to the read/write end of the PLC module is TXS 0108. The E pin of ULN2003A is connected to ground; pins 1B-7B are connected with user I/O pins of the FPGA chip; the pins 1C-7C are connected with the pins L1 and L3 of the LED pins of the work indicator lamp. Where 1B-7B are input ports, 1C-7C are output ports, and E is a ground port.

The VCCA, VCCB and OE pins of the TXS0108 are connected with a +3.3V power supply; the GND pin is connected with the ground; the A1-A8 pin is connected with the user I/O pin of the FPGA chip; pins B1-B8 are connected to the TX and RX pins of each PLC unit. The VCCA is an A-port power supply voltage port, the VCCB is a B-port power supply voltage port, the OE is a tri-state output mode enable port referring to the VCCA, the GND is a ground port, the A1-A8 are input/output ports referring to the VCCA, and the B1-B8 are input/output ports referring to the VCCB.

The alternating current bus simulation circuit is used for simulating a 220V power supply line of a high-speed rail train. The alternating current bus circuit is provided with a live wire bus and a zero line bus, and each client terminal unit and each server subunit in the PLC module are sequentially hung on the buses. A resistor, an inductor and a capacitor are respectively connected in series on a live wire and a zero line between two adjacent tested units, and the capacitor is connected in parallel to simulate an actual model when a rail transmits signals. The alternating current bus simulation circuit in the embodiment simulates a section of high-speed rail power supply line, and parameters can be adjusted according to actual conditions, so that a communication system is closer to a real scene, the reliability of simulation test is enhanced, and a 220V alternating current power supply is provided by commercial power.

As shown in fig. 4, the dc power circuit provides stable dc power for each dc component of the system, including +3.3V, +5V, + 12V. The +12V power supply is directly accessed from the outside through a plug P10 and is stabilized through a filter inductor, a filter capacitor and a transient diode, and the +5V power supply and the +3.3V power supply are converted from the +12V power supply through a DCDC 5V3A switching power supply module and an LM1084-3.3 low-dropout linear regulator. Before the +3.3V power supply is connected to the power supply end of the driving circuit chip, capacitance filtering is added to ensure the stability of voltage.

The P1 pin of the P10 plug is connected to ground; the P2 pin is connected to a +12V power supply. P1 is a ground port; p2 is a power port.

The IN + pin of the DCDC 5V3A switching power supply module is connected with a +12V power supply; the OUT + pin is connected with a +5V power supply; the IN-pin and the OUT-pin are connected to ground. IN + is the voltage input positive polarity port; IN-is the voltage input negative polarity port; OUT + is the voltage output positive polarity port; OUT-is the voltage output negative polarity port.

The Vin pin of the LM1084-3.3 low dropout linear regulator is connected with a +5V power supply; the Vout pin is connected with a +3.3V power supply; the GND pin is connected to ground. Vin is a voltage input port; vout is the voltage output port; GND is a ground port.

Fig. 5 is a schematic diagram of a PLC module, in which a work indicator lamp is used to indicate whether each PLC unit is working normally. In the embodiment, a +3.3V common anode LED double-color lamp is adopted, two cathodes, namely a qualified cathode and an unqualified cathode, are connected to an FPGA chip, when a corresponding PLC unit is tested to be qualified, the FPGA sends a low-level signal to the qualified cathode and a high-level signal to the unqualified cathode, at the moment, the anode and the qualified cathode are conducted, the LED lamp is green, and the qualified test state is indicated; on the contrary, when the PLC unit fails in testing, the two cathodes can obtain opposite signals, at the moment, the anode and the failed cathode are conducted, the LED lamp is red, and the testing failure state is indicated.

And a switch in the PLC module is used for controlling whether the working display lamp and the PLC unit work or not. The switch in this embodiment adopts a self-locking key switch with the model number of C194402, and when the switch is pressed down, the working display lamp and the PLC unit switch states simultaneously, so that the switching between a power-on state and a power-off state is realized.

The +12 pin of the PLC unit is connected with the S5 pin of the C194402; GND and NC pins are connected with the ground; the TX and RX pins are connected with two pins of B1-B8 of a TXS0108 chip of the driving circuit; the N pin and the L pin are respectively connected with the inductors on the live wire and the zero line of the alternating current bus analog circuit. Where, +12 is a power port, GND and NC are ground ports, TX is a transmit data port, RX is a receive data port, N is a fire line port, and L is a zero line port.

The L1 and L3 pins of the working indicator light LED are connected with two pins in the 1C-7C pins of the ULN2003A chip; the L2 pin is connected to the S2 pin of the boat switch C194402 through a resistor. Where L1 and L3 are the two cathode ports of the LED and L2 is the common port of the common anode.

The S1 pin of C194402 is connected with +3.3V power supply; the S2 pin is connected with the L2 pin of the work indicator light LED through a resistor; the S4 pin is connected with a +12V power supply; the pin S5 is connected to the +12 pin of the PLC unit. Wherein, S2 and S5 are two central heads of the self-locking key switch, and S1 and S4 are respectively static contacts of the switch on one side of C194402.

The upper computer in the embodiment is used for controlling the resource board, receiving and sending data, and analyzing and displaying the received data. The function requirement of the system is to give instructions to the resource board, receive the data of the resource board, perform statistical analysis on the data and display the data. The display information mainly comprises a function selection button, statistics of data receiving and sending quantity of each channel of the resource board and a test message, wherein the content of the test message comprises a packet loss time point and a packet loss rate.

As shown in fig. 6, the reset circuit is composed of an MCU monitoring chip, a resistor, a capacitor, and a key switch. The model of the monitoring chip is MAX811S, and the low level is effective. Once the switch connected to the pin 3 of the monitoring chip is pressed, the pin 2 of the monitoring chip sends a signal to the FPGA circuit to reset the FPGA circuit.

As shown in fig. 6, the core component of the clock circuit is a crystal oscillator chip Y2, which can generate pulses with a frequency of 4MHz as the clock signal of the FPGA.

The VCC pin of MAX811S is connected to +3.3V power supply; the GND pin is connected with the ground; the MR/pin is connected with the ground through a key switch and is also connected with a power-on reset pin (zBank1_ D21) of the FPGA chip; the RST/pin is connected with a +3.3V power supply through a resistor. VCC is a power input port, GND is a ground port, MR is an artificial reset port, and RST is a reset port.

VCC and CON pins of Y2 are connected with +3.3V regulated power supply; the GND pin is connected with the ground; the ClkOut pin is connected to the FPGA chip clock pin (zBank2_ R22). Where VCC is the power input port, CON is the control port, GND is the ground port, and ClkOut is the clock signal output port.

The communication test of the system comprises the following specific steps:

(1) the first step is as follows: installing each PLC unit according to the label, and electrifying the resource board; and the upper computer sends the configuration information to the FPGA chip, and the FPGA chip initializes the resource board.

(2) The second step is that: operating the upper computer and selecting a corresponding working mode; the FPGA chip receives and transmits data according to the working mode selected by the upper computer, counts the packet loss rate and sends the data to the upper computer; meanwhile, the FPGA chip controls the indicator lamp according to an instruction issued by the upper computer, and the PLC unit is qualified in test or unqualified in test.

(3) The third step: and the upper computer displays the statistical analysis result and feeds the statistical analysis result back to the tester.

Claims (1)

1. The utility model provides a multiunit communication test system based on FPGA realizes which characterized in that: the system comprises a resource board, a PLC module and an upper computer;

the resource board comprises an FPGA circuit, a driving circuit, an Ethernet module, an alternating current bus analog circuit, a direct current power supply circuit, a clock circuit and a reset circuit;

the PLC module comprises 20 client terminal units PLC1-PLC20, 20 work display lamps LED1-LED20, 20 switches S1-S20 and 1 server subunit PLC21, wherein one client terminal unit corresponds to one work display lamp, and the client terminal units and the server subunits belong to the PLC units;

through the FPGA circuit and the Ethernet module, the upper computer can control the data communication test process of the PLC module by controlling an FPGA chip in the FPGA circuit;

in the resource board, the driving circuit, the clock circuit and the reset circuit are connected to the FPGA circuit; the FPGA circuit is connected to an Ethernet module; the alternating current bus analog circuit adopts AC220V to supply power, and each client terminal unit and each server subunit are hung on the alternating current bus analog circuit; the direct current power supply circuit is connected to a direct current part in the circuit and supplies power to the direct current part; the direct current part comprises the PLC module, an FPGA circuit, a driving circuit, an Ethernet module, a clock circuit and a reset circuit;

the client terminal units PLC1-PLC20, the work display lamps LED1-LED20 and the server subunit PLC21 of the PLC modules are connected with the driving circuit in the resource board; the TX and RX ports of each client terminal unit and each server subunit are connected with a serial port of a driving circuit through signal wires, and the serial port of the driving circuit is connected with a serial port of an FPGA circuit to realize the communication between the PLC unit and the FPGA circuit; the client terminal unit and the server subunit complete communication through an alternating current bus analog circuit;

the alternating current bus analog circuit is provided with a live wire bus and a zero line bus, and each client terminal unit and each server subunit in the PLC module are sequentially hung on the buses; a resistor, an inductor and a capacitor are respectively connected in series on a live line and a zero line between two adjacent tested units, and the capacitor is connected in parallel to simulate an actual model when a rail transmits signals;

the direct current power supply circuit consists of a switching power supply module and a linear voltage stabilizer, and converts direct current power supply of the resource board into power supplies required by the PLC module, the FPGA circuit, the driving circuit, the Ethernet module, the clock circuit and the reset circuit;

the upper computer has the functions of selecting a working mode, testing messages, controlling subordinate test boards, displaying the running state and counting the packet loss rate;

at least the following two communication modes are required to realize the complete test process of the test system:

firstly, communication between FPGA circuit and server subunit: the upper computer transmits the data packet to the FPGA circuit through the Ethernet module; next, the FPGA circuit unpacks the data packet and transmits the data to a corresponding PLC client terminal unit through the serial port of the FPGA circuit; the client terminal unit gathers the received data to the server subunit through an alternating current power supply circuit; the server subunit sends all the received data to the FPGA circuit through the serial port of the FPGA circuit; finally, the FPGA circuit packages the received data, counts the sent data and the received data, and transmits the data package and the counting result to the upper computer through the Ethernet module, so that the upper computer can calculate the packet loss rate;

another communication mode is the communication between the FPGA circuit and the client terminal unit: the upper computer transmits the data packet to the FPGA circuit through the Ethernet module; next, the FPGA circuit unpacks the data packet and transmits the data to the PLC server subunit through the serial port of the FPGA circuit; the server subunit broadcasts data to all the client terminal units through the alternating current power supply line, and the client terminal units transmit the received data to the FPGA circuit through the FPGA circuit serial ports; finally, the FPGA circuit packages data in the same way, counts the data receiving and sending conditions, and sends the result to the upper computer to enable the upper computer to calculate the packet loss rate;

the formula for calculating the packet loss rate x is as follows:

through the test results of the two communication modes and the calculation of the corresponding packet loss rate, the function of the PLC receiving and sending data, the quality of data communication and the specific problems can be analyzed.

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