CN110556341B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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CN110556341B
CN110556341B CN201910908571.8A CN201910908571A CN110556341B CN 110556341 B CN110556341 B CN 110556341B CN 201910908571 A CN201910908571 A CN 201910908571A CN 110556341 B CN110556341 B CN 110556341B
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source
region
layer
oxide layer
drain region
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CN110556341A (en
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何志斌
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

The application discloses a manufacturing method of a semiconductor device, which comprises the following steps: covering photoresist in an NMOS (N-channel metal oxide semiconductor) region of a core device, and removing a source-drain region of an IO (input/output) device and a hard mask layer of a source-drain region of a PMOS (P-channel metal oxide semiconductor) region of the core device by etching; etching the first gate oxide layer of the source-drain region of the IO device and the source-drain region of the PMOS region to form a U-shaped groove in the source-drain region of the PMOS region; removing the photoresist of the NMOS region, etching the source and drain regions of the PMOS region, and forming a sigma-shaped groove in the source and drain regions of the PMOS region; growing a silicon germanium layer in the sigma-shaped groove through an epitaxial process; and removing the hard mask layer and the first gate oxide layer of the source and drain region of the IO device by a wet etching process. According to the method, the first gate oxide layer of the source drain region is not required to be removed through an additional photoetching process, so that the process complexity is reduced, and the process cost is further reduced.

Description

Method for manufacturing semiconductor device
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device integrated with an IO device and a core device.
Background
A High Voltage (HV) device and an Input Output (IO) device are important components of a Light Emitting Diode (LED) driving chip. In the semiconductor process below 45 nm, the integration difficulty of high voltage devices and IO devices is increasing, and the requirement for cost control is also increasing.
The gate oxide layer of the IO device has a large thickness (generally higher than 100 angstroms), and after the gate is formed, the gate oxide layers of the Source (Source) region and the Drain (Drain) region (hereinafter, referred to as "Source and Drain regions") still exist, and the gate oxide layers of the Source and Drain regions need to be removed, otherwise, subsequent Source and Drain (SD) implantation cannot be performed.
In the related art, in the manufacturing process of the HV device integrated with the IO device, the source and drain regions of the IO device are generally defined by adding an additional photomask, and then the gate oxide layer of the source and drain regions is removed. However, removing the IO device through the mask increases process complexity and also increases process cost.
Disclosure of Invention
The application provides a manufacturing method of a semiconductor device, which can solve the problem that the manufacturing method of the HV device integrated with the IO device in the related technology has higher process cost because the source-drain region of the IO device needs to be defined through an extra photomask to remove a gate oxide layer.
In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
providing a substrate, wherein the substrate comprises an active area of an IO device and an active area of a core device, the active area of the core device comprises an N-type Metal-Oxide-Semiconductor (NMOS) region and a P-type Metal-Oxide-Semiconductor (PMOS) region, a first gate oxide layer is formed on the active region of the IO device, a first gate is formed on the first gate oxide layer, the first gate oxide layer covers the source and drain regions on the active region of the IO device, the NMOS region is formed with a second gate oxide layer, a second grid electrode is formed on the second grid oxide layer, a third grid oxide layer is formed in the PMOS area, a third grid electrode is formed on the third grid oxide layer, and an isolation layer and a hard mask layer are sequentially formed on the surfaces of the substrate, the first grid electrode, the second grid electrode and the third grid electrode;
covering photoresist on the NMOS region, and removing a source drain region of the IO device and a hard mask layer of the source drain region of the PMOS region by etching;
etching the first gate oxide layer of the source-drain region of the IO device and the source-drain region of the PMOS region, thinning the first gate oxide layer of the source-drain region of the IO device and the substrate of the PMOS region, and forming a U-shaped groove in the source-drain region of the PMOS region;
removing the photoresist of the NMOS region, etching the source and drain regions of the PMOS region, and forming a sigma-shaped groove in the source and drain regions of the PMOS region;
growing a silicon germanium layer in the sigma-shaped groove through an epitaxial process;
removing the hard mask layer on the surfaces of the first grid, the second grid and the third grid through a wet etching process;
and removing the first gate oxide layer of the source-drain region of the IO device by a wet etching process.
Optionally, the isolation layer includes a silicon nitride isolation layer, the hard mask layer includes a silicon nitride hard mask layer, and before the NMOS region is covered with a photoresist, the method further includes:
forming the silicon nitride isolation layer on the periphery of the first gate, the second gate and the third gate;
performing LDD injection on the source drain region of the IO device, the source drain region of the NMOS region and the source drain region of the PMOS region;
and depositing the silicon nitride hard mask layer on the surfaces of the substrate, the first grid, the second grid and the third grid.
Optionally, the removing the hard mask layer on the surfaces of the first gate, the second gate and the third gate by a wet etching process includes:
and removing the hard mask layer on the surfaces of the first grid, the second grid and the third grid through a phosphoric acid wet etching process.
Optionally, the removing the first gate oxide layer in the source/drain region of the IO device by the wet etching process includes:
and removing the first gate oxide layer of the source-drain region of the IO device by a hydrofluoric acid wet etching process.
Optionally, the removing, by etching, the source-drain region of the IO device and the hard mask layer of the source-drain region of the PMOS region includes:
and removing the hard mask layer of the source-drain region of the IO device and the source-drain region of the PMOS region by a dry etching process.
Optionally, the pair of the first gate oxide layer in the source-drain region of the IO device and the source-drain region of the PMOS region are etched to thin the first gate oxide layer in the source-drain region of the IO device and the substrate in the PMOS region, and the source-drain region of the PMOS region forms a U-shaped trench, including:
thinning the silicon dioxide top layers of the first grid electrode and the third grid electrode, the first grid oxide layer of the source-drain region of the IO device and the substrate of the source-drain region of the PMOS region through a dry etching process;
and thinning the silicon dioxide top layers of the first grid electrode and the third grid electrode, the first grid oxide layer of the source-drain region of the IO device and the substrate of the source-drain region of the PMOS region by a dry etching process, and forming the U-shaped groove in the source-drain region of the PMOS region.
Optionally, after the removing the first gate oxide layer in the source/drain region of the IO device by the wet etching process, the method further includes:
forming side walls on the peripheral sides of the first grid, the second grid and the third grid;
and sequentially carrying out SD injection on the active region of the IO device and the active region of the core device.
Optionally, the sidewall spacer includes silicon nitride.
Optionally, before the NMOS area is covered with a photoresist, the method further includes:
forming the first gate oxide layer, the second gate oxide layer and the third gate oxide layer on the substrate in sequence;
depositing a polysilicon layer, a silicon nitride layer and a silicon dioxide layer on the first gate oxide layer, the second gate oxide layer and the third gate oxide layer in sequence;
covering photoresist in the gate regions of the polycrystalline silicon layer, the silicon nitride layer and the silicon dioxide layer, and etching the polycrystalline silicon layer, the silicon nitride layer and the silicon dioxide layer in other regions to form the first gate, the second gate and the third gate.
Optionally, an STI structure is formed between the active region of the IO device, the NMOS region, and the PMOS region.
The technical scheme at least comprises the following advantages:
after a first grid of an IO device, a second grid and a third grid of a core device and a hard mask layer covering the grids and a substrate are formed, an NMOS region of a photomask core device is used for etching an IO device region and a PMOS region through etching to thin a first grid oxidation side and the hard mask layer of a source drain region, the third grid oxidation layer of the source drain region is removed, after a silicon germanium layer is formed in the PMOS region, the hard mask layer and the first grid oxidation layer of the source drain region are removed through a wet etching process, and the first grid oxidation layer of the source drain region does not need to be removed through an additional photoetching process, so that the process complexity is reduced, and the process cost is further reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart of a method of manufacturing a semiconductor device provided in one exemplary embodiment of the present application;
fig. 2 to 11 are schematic flow charts of a method for manufacturing a semiconductor device provided in the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Example 1:
fig. 1 shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application, the method including:
step 101, a substrate is provided.
Illustratively, referring to fig. 2, substrate 210 in this embodiment includes an active region 211 of an IO device and an active region 212 of a core device, which includes an NMOS region 2121 and a PMOS region 2122.
A first gate oxide layer 221 is formed on the active region 211 of the IO device, a first gate 231 is formed on the first gate oxide layer 221, and the first gate oxide layer 221 covers a source-drain region on the active region 211 of the IO device.
The NMOS region 2121 is formed with a second gate oxide layer 222, and a second gate 232 is formed on the second gate oxide layer 222; the PMOS region 2122 is formed with a third gate oxide layer 223, and a third gate 233 is formed on the third gate oxide layer 223.
An isolation layer 201 and a hard mask layer 202 are sequentially formed on the surfaces of the substrate 210, the first gate 231, the second gate 232 and the third gate 233. Optionally, the isolation layer 201 comprises a silicon nitride isolation layer, and the hard mask layer 202 comprises a silicon nitride hard mask layer.
Step 102, covering photoresist on the NMOS region, and removing a hard mask layer of a source-drain region of the IO device and a hard mask layer of a source-drain region of the PMOS region through etching.
For example, referring to fig. 3 and 4, a photoresist may be coated on the substrate 210 and the pattern on the substrate 210, the photoresist in the other regions except the NMOS region 2121 may be exposed through a mask (not shown in fig. 3 and 4), and after the exposed photoresist is removed through development, the hard mask layer 202 in the source and drain regions of the IO device and the source and drain regions of the PMOS region 2122 may be removed through etching. Optionally, the hard mask layer 202 in the source and drain regions of the IO device and the source and drain regions of the PMOS region 2122 may be removed by a dry etching process. After this etching step, as shown in fig. 4, the hard mask layer 202 on top of the first gate 231 and the second gate 232 is also removed.
103, etching the first gate oxide layer of the source-drain region of the IO device and the source-drain region of the PMOS region, thinning the first gate oxide layer of the source-drain region of the IO device and the substrate of the PMOS region, and forming a U-shaped groove in the source-drain region of the PMOS region.
Illustratively, the etching step in step 103 may be divided into two stages: in the first stage, referring to fig. 5, the silicon dioxide top layers of the first gate 231 and the third gate 233, the first gate oxide layer 221 of the source-drain region of the IO device, and the substrate of the source-drain region of the PMOS region 2122 are thinned by a dry etching process; at the second stage, referring to fig. 6, the silicon dioxide top layers of the first gate 231 and the third gate 233, the first gate oxide layer 221 of the source and drain region of the IO device, and the substrate of the source and drain region of the PMOS region 2122 are thinned by a dry etching process, and a U-shaped trench is formed in the source and drain region of the PMOS region 2122.
And 104, removing the photoresist of the NMOS region, etching the source and drain regions of the PMOS region, and forming a sigma-shaped groove in the source and drain regions of the PMOS region.
For example, referring to fig. 7, the photoresist of the NMOS region 2121 is removed, and the source and drain regions of the PMOS region 2122 may be etched by a hydrofluoric acid wet etching process to form a sigma-shaped trench in the source and drain regions of the PMOS region 2122.
Step 105, growing a silicon germanium layer in the sigma-shaped trench by an Epitaxial (EPI) process.
Illustratively, referring to fig. 8, a silicon germanium layer 801 is grown in the sigma-shaped trenches by an EPI process.
And 106, removing the hard mask layer on the surfaces of the first grid, the second grid and the third grid through a wet etching process.
Illustratively, referring to FIG. 9, the reaction can be carried out by phosphoric acid (P)3O4) The hard mask layer 202 on the surfaces of the first gate 231, the second gate 232 and the third gate 233 is removed by a wet etching process.
And 107, removing the first gate oxide layer of the source and drain region of the IO device through a wet etching process.
Illustratively, referring to fig. 9, the first gate oxide layer 221 of the source and drain regions of the IO device may be removed by a hydrofluoric acid (HF) wet etching process.
In summary, in the embodiment, after the first gate of the IO device, the second gate and the third gate of the core device, and the hard mask layer covering the gates and the substrate are formed, the NMOS region of the core device is masked, the IO device region and the PMOS region are etched by etching to thin the first gate oxide side and the hard mask layer of the source drain region, the third gate oxide layer of the source drain region is removed, and after the sige layer is formed in the PMOS region, the hard mask layer and the first gate oxide layer of the source drain region are removed by a wet etching process.
Example 2:
referring to embodiment 1, embodiment 2 differs from embodiment 1 in that, before step 101, it further includes: forming a silicon nitride isolation layer 201 on the periphery of the first gate 231, the second gate 232 and the third gate 233; performing LDD injection on a source drain region of the IO device, a source drain region of the NMOS region 2121 and a source drain region of the PMOS region 2122; a silicon nitride hard mask layer 202 is deposited on the surfaces of the substrate 210, the first gate 231, the second gate 232, and the third gate 233.
Example 3:
referring to embodiment 2 and fig. 10 and 11, embodiment 3 differs from embodiment 2 in that: before the step of embodiment 2, a first gate oxide layer 221, a second gate oxide layer 222 and a third gate oxide layer 223 are sequentially formed on the substrate 210, wherein the thickness of the first gate oxide layer 221 is greater than that of the second gate oxide layer 222 and the third gate oxide layer 223; depositing a polysilicon layer 2301, a silicon nitride layer 2302 and a silicon dioxide layer 2303 on the first gate oxide layer 221, the second gate oxide layer 222 and the third gate oxide layer 223 in sequence; photoresist is covered on the gate regions of the polysilicon layer 2301, the silicon nitride layer 2302 and the silicon dioxide layer 2303, and the polysilicon layer 2301, the silicon nitride layer 2302 and the silicon dioxide layer 2303 in other regions are etched to form the first gate 231, the second gate 232 and the third gate 233.
Example 4:
referring to examples 1 to 3, example 4 differs from the above examples in that: after step 107, further comprising: forming side walls on the peripheral sides of the first grid, the second grid and the third grid; and sequentially injecting Source and Drain (SD) into the active region of the IO device and the active region of the core device. Optionally, the sidewall spacer includes silicon nitride.
Optionally, in the above embodiment, a Shallow Trench Isolation (STI) structure 240 is further disposed between the active region 211, the NMOS region 2121, and the PMOS region 2122 of the IO device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an active area of an IO device and an active area of a core device, the active area of the core device comprises an NMOS area and a PMOS area, a first gate oxide layer is formed on the active area of the IO device, a first gate electrode is formed on the first gate oxide layer, the first gate oxide layer covers a source drain area on the active area of the IO device, a second gate oxide layer is formed on the NMOS area, a second gate electrode is formed on the second gate oxide layer, a third gate oxide layer is formed on the PMOS area, a third gate electrode is formed on the third gate oxide layer, and an isolation layer and a hard mask layer are sequentially formed on the surfaces of the substrate, the first gate electrode, the second gate electrode and the third gate electrode;
covering photoresist on the NMOS region, and removing a source drain region of the IO device and a hard mask layer of the source drain region of the PMOS region by etching;
etching the first gate oxide layer of the source-drain region of the IO device and the source-drain region of the PMOS region, thinning the first gate oxide layer of the source-drain region of the IO device and the substrate of the PMOS region, and forming a U-shaped groove in the source-drain region of the PMOS region;
removing the photoresist of the NMOS region, etching the source and drain regions of the PMOS region, and forming a sigma-shaped groove in the source and drain regions of the PMOS region;
growing a silicon germanium layer in the sigma-shaped groove through an epitaxial process;
removing the hard mask layer on the surfaces of the first grid, the second grid and the third grid through a wet etching process;
and removing the first gate oxide layer of the source-drain region of the IO device by a wet etching process.
2. The method of claim 1, wherein the isolation layer comprises a silicon nitride isolation layer, wherein the hard mask layer comprises a silicon nitride hard mask layer, and wherein before the NMOS region is covered with a photoresist, further comprising:
forming the silicon nitride isolation layer on the periphery of the first gate, the second gate and the third gate;
performing LDD injection on the source drain region of the IO device, the source drain region of the NMOS region and the source drain region of the PMOS region;
and depositing the silicon nitride hard mask layer on the surfaces of the substrate, the first grid, the second grid and the third grid.
3. The method of claim 2, wherein removing the hard mask layer on the surface of the first gate, the second gate and the third gate by a wet etching process comprises:
and removing the hard mask layer on the surfaces of the first grid, the second grid and the third grid through a phosphoric acid wet etching process.
4. The method of claim 3, wherein the removing the first gate oxide layer of the source and drain regions of the IO device by a wet etching process comprises:
and removing the first gate oxide layer of the source-drain region of the IO device by a hydrofluoric acid wet etching process.
5. The method of claim 2, wherein the removing the hard mask layer of the source drain region of the IO device and the source drain region of the PMOS region by etching comprises:
and removing the hard mask layer of the source-drain region of the IO device and the source-drain region of the PMOS region by a dry etching process.
6. The method of claim 2, wherein the etching the first gate oxide layer of the source-drain region of the IO device and the source-drain region of the PMOS region to thin the first gate oxide layer of the source-drain region of the IO device and the substrate of the PMOS region and form a U-shaped trench in the source-drain region of the PMOS region comprises:
thinning the silicon dioxide top layers of the first grid electrode and the third grid electrode, the first grid oxide layer of the source-drain region of the IO device and the substrate of the source-drain region of the PMOS region through a dry etching process;
and thinning the silicon dioxide top layers of the first grid electrode and the third grid electrode, the first grid oxide layer of the source-drain region of the IO device and the substrate of the source-drain region of the PMOS region by a dry etching process, and forming the U-shaped groove in the source-drain region of the PMOS region.
7. The method according to any one of claims 1 to 6, wherein after the removing the first gate oxide layer of the source and drain regions of the IO device by the wet etching process, the method further comprises:
forming side walls on the peripheral sides of the first grid, the second grid and the third grid;
and sequentially carrying out SD injection on the active region of the IO device and the active region of the core device.
8. The method of claim 7, wherein the sidewall spacers comprise silicon nitride.
9. The method of claim 7, wherein before the covering the NMOS region with photoresist, further comprising:
forming the first gate oxide layer, the second gate oxide layer and the third gate oxide layer on the substrate in sequence;
depositing a polysilicon layer, a silicon nitride layer and a silicon dioxide layer on the first gate oxide layer, the second gate oxide layer and the third gate oxide layer in sequence;
covering photoresist in the gate regions of the polycrystalline silicon layer, the silicon nitride layer and the silicon dioxide layer, and etching the polycrystalline silicon layer, the silicon nitride layer and the silicon dioxide layer in other regions to form the first gate, the second gate and the third gate.
10. The method of any of claims 1 to 6, wherein STI structures are formed between the active region of the IO device, the NMOS region, and the PMOS region.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102292800A (en) * 2009-01-21 2011-12-21 飞思卡尔半导体公司 Dual high-K oxides with SiGe channel
CN103378099A (en) * 2012-04-26 2013-10-30 台湾积体电路制造股份有限公司 Device and methods for high-k and metal gate stacks
CN105448832A (en) * 2014-08-21 2016-03-30 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102292800A (en) * 2009-01-21 2011-12-21 飞思卡尔半导体公司 Dual high-K oxides with SiGe channel
CN103378099A (en) * 2012-04-26 2013-10-30 台湾积体电路制造股份有限公司 Device and methods for high-k and metal gate stacks
CN105448832A (en) * 2014-08-21 2016-03-30 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method

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