CN110544462B - Dual-circuit display output circuit of intelligent instrument - Google Patents
Dual-circuit display output circuit of intelligent instrument Download PDFInfo
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- CN110544462B CN110544462B CN201910984328.4A CN201910984328A CN110544462B CN 110544462 B CN110544462 B CN 110544462B CN 201910984328 A CN201910984328 A CN 201910984328A CN 110544462 B CN110544462 B CN 110544462B
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- 239000003990 capacitor Substances 0.000 claims description 32
- 238000004891 communication Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 2
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Automation & Control Theory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
A dual-loop display output circuit of an intelligent instrument comprises a main control CPU, a first display control chip and a second display control chip; the main control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin; the first display control chip comprises a first chip selection port, a first clock port and a first input port; the second display control chip comprises a second chip selection port, a second clock port and a second input port; the first output pin is connected with the first slice selection port through a first slice selection signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus; the fourth output pin is connected with the second chip selection port through the second chip selection signal line, the fifth output pin is connected with the second clock port through the second clock line, and the sixth output pin is connected with the second input port through the second output bus.
Description
Technical Field
The invention relates to the field of electronic devices, in particular to a double-loop display output circuit of an intelligent instrument.
Background
The display interface refreshing work of the existing intelligent instrument generally adopts a mode control display chip with a group of communication buses and two chip selection signal lines, namely, when display information needs to be refreshed each time, a first display control chip is selected firstly, content needing to be displayed is sent to the first display control chip through the communication buses, then the first display control chip is released, a second display control chip is selected, then the same operation as that of the first display control chip is executed, and then the second display control chip is released. When the execution operation is performed and the content of the display interface is refreshed, the refresh of the content displayed by the display control chip is required to be completed piece by piece, and twice the time is required to be spent for completing the refresh operation of the display interface, so that the working efficiency of the system is greatly reduced.
Disclosure of Invention
Aiming at the defects in the background technology, the invention provides a double-loop display output circuit of an intelligent instrument, which realizes the parallel simultaneous output and refresh control of a display interface, improves the efficiency of display output and reduces the invalid overhead of a main control CPU.
To achieve the purpose, the invention adopts the following technical scheme:
a dual-loop display output circuit of an intelligent instrument comprises a main control CPU, a first display control chip and a second display control chip;
the main control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin;
the first display control chip comprises a first chip selection port, a first clock port and a first input port;
the second display control chip comprises a second chip selection port, a second clock port and a second input port;
The first output pin is connected with the first chip select port through a first chip select signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
The fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
Preferably, the LED digital tube comprises a first LED digital tube, a second LED digital tube and a third LED digital tube; the LED nixie tubes are provided with a plurality of pins;
the first display control chip and the second display control chip are respectively provided with a homonymous terminal port with a pin on the LED nixie tube;
And the same-name end ports on the first display control chip are respectively connected with pins of the first LED nixie tube and the second LED nixie tube in a one-to-one correspondence manner to form a loop.
Preferably, the same name end ports of the second display control chip are respectively connected with pins of the third LED nixie tube in a one-to-one correspondence manner to form a loop.
Preferably, the LED lamp comprises a plurality of groups of LED lamps, and the LED lamps are respectively connected with pins of the third LED nixie tube in a one-to-one correspondence manner;
and the LED lamps are respectively connected with the same-name end ports of the second display control chip in a one-to-one correspondence manner.
Preferably, the main control CPU further comprises a first electrolytic capacitor, a first capacitor, an AV port and an AGND analog ground port;
One end of the first electrolytic capacitor is connected with the AV port, and the other end of the first electrolytic capacitor is connected with the AGND analog ground port; one end of the first capacitor is connected with the AV port, and the other end of the first capacitor is connected with the AGND analog ground port.
Preferably, the main control CPU further comprises a second electrolytic capacitor, a second capacitor, a grounding port and a reference voltage port; one end of the second electrolytic capacitor is connected with the reference voltage port, and the other end of the second electrolytic capacitor is connected with the grounding port;
one end of the second capacitor is connected with the reference voltage port, and the other end of the second capacitor is connected with the grounding port.
The beneficial effects are that:
1. By adopting an independent dual-loop control communication bus design mode on hardware, parallel and simultaneous output refreshing control of a display interface is realized, and a second group of display contents can be refreshed simultaneously while a first group of display contents are refreshed, so that the display output efficiency is improved, and the invalid expense of a main control CPU is reduced.
Drawings
Fig. 1 is a circuit diagram of a master CPU of the present invention;
FIG. 2 is a circuit diagram of a first display control chip and an LED nixie tube of the present invention;
FIG. 3 is a circuit diagram of a second display control chip, an LED nixie tube and an LED lamp of the present invention;
Fig. 4 is a circuit connection diagram of the main control CPU, the first display control chip and the second display control chip.
Wherein: the LED display control system comprises a main control CPU (Central processing Unit) -1, a first display control chip-2, a second display control chip-3, a first LED nixie tube-4, a second LED nixie tube-5, a third LED nixie tube-6 and an LED lamp-7.
Detailed Description
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
The orientation in this embodiment is based on the drawings in the specification.
In the prior art, a mode control display chip with a group of communication buses and two chip selection signal lines is adopted, namely, when display information needs to be refreshed each time, a first display control chip is selected, display content needs to be displayed is sent to the first display control chip through the communication buses, then the first display control chip is released, a second display control chip is selected, display content needs to be displayed is sent to the second display control chip through the communication buses, and then the second display control chip is released, so that display content updating is completed.
As described above, in the prior art, when the content of the display interface is refreshed, the refresh of the content displayed in the display control chip must be completed piece by piece, that is, twice the time must be spent to complete the refresh of the display interface, thereby reducing the working efficiency of the system.
The invention relates to a double-loop display output circuit of an intelligent instrument, which is shown in figures 1-4, and comprises a main control CPU1, a first display control chip 2 and a second display control chip 3;
The main control CPU1 comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin;
the first display control chip 2 comprises a first chip selection port, a first clock port and a first input port;
the second display control chip 3 comprises a second chip selection port, a second clock port and a second input port;
The first output pin is connected with the first chip select port through a first chip select signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
The fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
As shown in fig. 1-3, the first output pin is p2.0, the second output pin is p2.1, the third output pin is p2.2, the fourth output pin is p2.3, the fifth output pin is p2.4, and the sixth output pin is p2.5;
The first chip selection port corresponds to an icon 6-CS of the first display control chip 2;
The first clock port corresponds to the icon 7-CLK of the first display control chip 2;
the first input port corresponds to the icon 8-DATA of the first display control chip 2;
the second chip selection port corresponds to an icon CS-6 of the second display control chip 3;
the second clock port corresponds to an icon CLK-7 of the second display control chip 3;
the second input port corresponds to an icon DATA-8 of the second display control chip 3;
A first chip select signal line CS1, a second chip select signal line CS2, a first clock line CLK1, a second clock line CLK2, a first output bus data1, a second output bus data2;
As shown in fig. 4, the first output pin p2.0 is connected to the first chip select port 6-CS through a first chip select signal line CS1, the second output pin p2.1 is connected to the first clock port 7-CLK through a first clock line CLK1, and the third output pin p2.2 is connected to the first input port 8-DATA through a first output bus DATA 1;
The fourth output pin p2.3 is connected to the second chip select port CS-6 through a second chip select signal line CS2, the fifth output pin p2.4 is connected to the second clock port CLK-7 through a second clock line CLK2, and the sixth output pin p2.5 is connected to the second input port DATA-8 through a second output bus DATA 2.
The main control CPU1 is respectively connected with two display control chips in a way of connecting two groups of completely independent chip selection and communication buses, so that the main control CPU1 can simultaneously control two display function chips when performing display content output control, and the display output efficiency is improved;
When the first display control chip is controlled to refresh data, the second display control chip can be controlled simultaneously without waiting for the completion of the first operation, so that the display content can be output in parallel and synchronously, the interaction stability of serial communication is fully utilized, and the display interaction efficiency is improved.
The two display control chips are adopted for display control, so that the power consumption load of the single display control chip is reduced, the abnormal range is reduced when the abnormality occurs, and the investigation and analysis of abnormal working conditions are facilitated;
Preferably, as shown in fig. 3, the LED nixie tube comprises a first LED nixie tube 4, a second LED nixie tube 5 and a third LED nixie tube 6; the LED nixie tubes are provided with a plurality of pins;
The first display control chip 2 and the second display control chip 3 are respectively provided with a homonymous port with a pin on the LED nixie tube;
And the same-name end ports on the first display control chip 2 are respectively connected with pins of the first LED nixie tube 4 and the second LED nixie tube 5 in a one-to-one correspondence manner to form a loop.
Preferably, the same name end ports of the second display control chip 3 are respectively connected with pins of the third LED nixie tube 6 in a one-to-one correspondence manner to form a loop.
Preferably, the LED lamp comprises a plurality of groups of LED lamps 7, and the LED lamps 7 are respectively connected with pins of the third LED nixie tube 6 in a one-to-one correspondence manner;
the LED lamps 7 are respectively connected with the same-name end ports of the second display control chip 3 in a one-to-one correspondence manner.
The pins of the LED nixie tube comprise A, B, C, D, E, F, G, DP;
the same name end ports of the first display control chip 2 and the second display control chip 3 comprise an SA end, an SB end, an SC end, an SE end, an SF end, an SG end and a DP end;
The pin A of the LED nixie tube is connected with the SA ends of the first display control chip 2 and the second display control chip 3; the pin B is connected with SB ends of the first display control chip 2 and the second display control chip 3; by the pushing, the purpose that the first display control chip 2 and the second display control chip 3 control and output the LED nixie tube is achieved.
Preferably, as shown in fig. 1, the main control CPU1 further includes a first electrolytic capacitor C1, a first capacitor C2, AV ports 14-av+ and 11-av+, and AGND analog ground ports 10-AGND and 13-AGND;
One end of the first electrolytic capacitor C1 is connected with the AV ports 14-AV+ and 11-AV+ and the other end is connected with the AGND analog ground ports 10-AGND and 13-AGND; one end of the first capacitor C2 is connected with the AV ports 14-AV+ and 11-AV+ and the other end is connected with the AGND analog ground ports 10-AGND and 13-AGND.
Preferably, the main control CPU1 further includes a second electrolytic capacitor C4, a second capacitor C3, a ground port GND and a reference voltage port AVEF; one end of the second electrolytic capacitor C4 is connected to the reference voltage port AVEF, and the other end is connected to the ground port GND;
one end of the second capacitor C3 is connected to the reference voltage port AVEF, and the other end is connected to the ground port GND.
The technical principle of the present invention is described above in connection with the specific embodiments. The description is made for the purpose of illustrating the general principles of the invention and should not be taken in any way as limiting the scope of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of this specification without undue burden.
Claims (6)
1. A dual-loop display output circuit of an intelligent instrument is characterized in that: the display control system comprises a main control CPU, a first display control chip and a second display control chip;
the main control CPU comprises a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin and a sixth output pin;
the first display control chip comprises a first chip selection port, a first clock port and a first input port;
the second display control chip comprises a second chip selection port, a second clock port and a second input port;
The first output pin is connected with the first chip select port through a first chip select signal line, the second output pin is connected with the first clock port through a first clock line, and the third output pin is connected with the first input port through a first output bus;
The fourth output pin is connected with the second chip selection port through a second chip selection signal line, the fifth output pin is connected with the second clock port through a second clock line, and the sixth output pin is connected with the second input port through a second output bus.
2. The dual-loop display output circuit of a smart meter as set forth in claim 1, wherein:
The LED nixie tube comprises a first LED nixie tube, a second LED nixie tube and a third LED nixie tube; the LED nixie tubes are provided with a plurality of pins;
the first display control chip and the second display control chip are respectively provided with a homonymous terminal port with a pin on the LED nixie tube;
And the same-name end ports on the first display control chip are respectively connected with pins of the first LED nixie tube and the second LED nixie tube in a one-to-one correspondence manner to form a loop.
3. The dual-loop display output circuit of a smart meter as set forth in claim 2, wherein:
And the homonymous end ports of the second display control chip are respectively connected with pins of the third LED nixie tube in a one-to-one correspondence manner to form a loop.
4. A dual-loop display output circuit of a smart meter as defined in claim 3, wherein:
the LED lamps are respectively connected with pins of the third LED nixie tube in a one-to-one correspondence manner;
and the LED lamps are respectively connected with the same-name end ports of the second display control chip in a one-to-one correspondence manner.
5. The dual-loop display output circuit of a smart meter as set forth in claim 1, wherein:
The main control CPU also comprises a first electrolytic capacitor, a first capacitor, an AV port and an AGND analog ground port;
One end of the first electrolytic capacitor is connected with the AV port, and the other end of the first electrolytic capacitor is connected with the AGND analog ground port; one end of the first capacitor is connected with the AV port, and the other end of the first capacitor is connected with the AGND analog ground port.
6. The dual-loop display output circuit of a smart meter as set forth in claim 5, wherein:
The main control CPU also comprises a second electrolytic capacitor, a second capacitor, a grounding port and a reference voltage port; one end of the second electrolytic capacitor is connected with the reference voltage port, and the other end of the second electrolytic capacitor is connected with the grounding port;
one end of the second capacitor is connected with the reference voltage port, and the other end of the second capacitor is connected with the grounding port.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910984328.4A CN110544462B (en) | 2019-10-16 | 2019-10-16 | Dual-circuit display output circuit of intelligent instrument |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910984328.4A CN110544462B (en) | 2019-10-16 | 2019-10-16 | Dual-circuit display output circuit of intelligent instrument |
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| CN110544462A CN110544462A (en) | 2019-12-06 |
| CN110544462B true CN110544462B (en) | 2024-06-11 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5540102A (en) * | 1992-09-23 | 1996-07-30 | Kindrick; Dudley | System for displaying the amount of fluid dispensed from a hand-held sprayer |
| CN200962040Y (en) * | 2005-10-09 | 2007-10-17 | 福建顺昌虹润精密仪器有限公司 | Dual loop measurement display control instrument |
| CN204302345U (en) * | 2014-11-04 | 2015-04-29 | 广州市鑫锋电气设备制造有限公司 | Numerical monitor gauge outfit |
| CN206031081U (en) * | 2016-08-25 | 2017-03-22 | 永康市兰雪龙智能科技有限公司 | Charactron display instrument |
| CN108597470A (en) * | 2018-05-08 | 2018-09-28 | 深圳市华星光电技术有限公司 | Display device drive system and method and display device |
| CN208970149U (en) * | 2018-09-21 | 2019-06-11 | 上海四横电机制造有限公司 | A kind of display driver circuit of communication with the outside world |
| CN210223521U (en) * | 2019-10-16 | 2020-03-31 | 广东科瑞德电气科技有限公司 | Double-loop display output circuit of intelligent instrument |
-
2019
- 2019-10-16 CN CN201910984328.4A patent/CN110544462B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5540102A (en) * | 1992-09-23 | 1996-07-30 | Kindrick; Dudley | System for displaying the amount of fluid dispensed from a hand-held sprayer |
| CN200962040Y (en) * | 2005-10-09 | 2007-10-17 | 福建顺昌虹润精密仪器有限公司 | Dual loop measurement display control instrument |
| CN204302345U (en) * | 2014-11-04 | 2015-04-29 | 广州市鑫锋电气设备制造有限公司 | Numerical monitor gauge outfit |
| CN206031081U (en) * | 2016-08-25 | 2017-03-22 | 永康市兰雪龙智能科技有限公司 | Charactron display instrument |
| CN108597470A (en) * | 2018-05-08 | 2018-09-28 | 深圳市华星光电技术有限公司 | Display device drive system and method and display device |
| CN208970149U (en) * | 2018-09-21 | 2019-06-11 | 上海四横电机制造有限公司 | A kind of display driver circuit of communication with the outside world |
| CN210223521U (en) * | 2019-10-16 | 2020-03-31 | 广东科瑞德电气科技有限公司 | Double-loop display output circuit of intelligent instrument |
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