CN207781155U - Circuit for improving numeral method - Google Patents
Circuit for improving numeral method Download PDFInfo
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- CN207781155U CN207781155U CN201721887305.4U CN201721887305U CN207781155U CN 207781155 U CN207781155 U CN 207781155U CN 201721887305 U CN201721887305 U CN 201721887305U CN 207781155 U CN207781155 U CN 207781155U
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- register clock
- shift register
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Abstract
The utility model provides a kind of circuit for improving numeral method, it solves the technical problems such as prior art poor display effect.This is used to improve the circuit of numeral method, including eight road bus transceiver chips, wherein three signal input pins of the eight road bus transceiver chips respectively with shift register clock signal, storage register clock signal is connected with serial data signal, eight road bus transceiver chips of Qie Gai and shift register clock signal, storage register clock signal and the corresponding signal output pin of serial data signal respectively with the shift register clock input pin of HC595 chips, storage register clock input pin is connected with serial date transfer pin, the residual signal input pin of the eight road bus transceiver chips is connected with ground terminal, the residual signal output pin of the eight road bus transceiver chips is hanging；Advantage is：Improve the display effect of charactron.
Description
Technical field
The utility model belongs to field of circuit technology, more particularly, to a kind of circuit for improving numeral method.
Background technology
Charactron is a kind of light emitting semiconductor device, and basic unit is light emitting diode.Connect by light emitting diode
The mode of connecing can be divided into common-anode charactron and common cathode charactron.Common anode charactron refers to connecing the anode of all light emitting diodes
To the charactron for forming public anode (COM) together, public pole COM should be connected to+5V by common anode charactron in application, when a certain
When the cathode of field light emitting diode is low level, respective field is just lighted, when the cathode of a certain field is high level, accordingly
Field does not just work.Common cathode charactron refers to that the cathode of all light emitting diodes is connected to the number for forming common cathode (COM) together
Code pipe, public pole COM should be connected on ground wire GND by common cathode charactron in application, when the anode of a certain field light emitting diode
For high level when, respective field is just lighted, when the anode of a certain field be low level when, respective field does not just work.
In existing digital pipe display circuit, MCU module is connected to control charactron with charactron by HC595 chips
Display, charactron is susceptible to the phenomenon that coruscating, poor display effect.
Invention content
The purpose of this utility model is can to improve number in view of the above-mentioned problems, provide a kind of reasonable design, simple in structure
The circuit for improving numeral method that pipe is shown.
In order to achieve the above objectives, the utility model uses following technical proposal：This is used to improve the electricity of numeral method
Road, including eight road bus transceiver chips, wherein three signal input pin difference of the eight road bus transceiver chips
It is connected with shift register clock signal, storage register clock signal and serial data signal, eight road bus transceivers of Qie Gai
Chip signal output pin corresponding with shift register clock signal, storage register clock signal and serial data signal
Respectively with the shift register clock input pin of HC595 chips, storage register clock input pin and serial date transfer
Pin is connected, and the residual signal input pin of the eight road bus transceiver chips is connected with ground terminal, and eight tunnels are total
The residual signal output pin of line transceiver chip is hanging；Signal output pin corresponding with shift register clock signal is logical
First resistor is crossed with the shift register clock input pin of HC595 chips to be connected, it is corresponding with storage register clock signal
Signal output pin be connected with the storage register clock input pin of HC595 chips by second resistance, with serial data
The corresponding signal output pin of signal is connected by 3rd resistor with the serial date transfer pin of HC595 chips；In HC595
It is connected with the first capacitance between the shift register clock input pin and ground terminal of chip, is deposited in the storage of HC595 chips
The second capacitance is connected between device clock input pin and ground terminal, in serial date transfer pin and the ground connection of HC595 chips
Third capacitance is connected between end.
Above-mentioned in improving the circuit of numeral method, the first resistor, second resistance and 3rd resistor
Resistance value all same and in 50 Ω between 150 Ω, the capacitance of first capacitance, the second capacitance and third capacitance is equal
It is identical and in 50pF between 150pF.
Above-mentioned in improving the circuit of numeral method, the residual signal of the eight road bus transceiver chips
Three signal input pins in input pin control signal phase with first control signal, second control signal and third respectively
Even.
Above-mentioned in improving the circuit of numeral method, in shift register clock signal, storage register
It is all provided between clock signal, serial data signal, first control signal, second control signal and third control signal and pull-up power supply
There is pull-up resistor.
Above-mentioned in improving the circuit of numeral method, the eight road bus transceiver chips to be
The DIR pins of SN74HCT245 chips, the SN74HCT245 chips are connected with power supply, the SN74HCT245 cores
A1 to the A8 pins of piece are signal input pin, and B1 to the B8 pins of the SN74HCT245 chips are signal output pin,
The VCC pin of the SN74HCT245 chips is connected with power supply, and filtering is connected between power supply and ground terminal
The GND pin of capacitance, the SN74HCT245 chips is connected with ground terminal.
Compared with prior art, the advantages of originally being used to improve the circuit of numeral method is：MCU module with
Eight road bus transceiver chips are set between HC595 chips, and reasonably select the electricity of first resistor, second resistance and 3rd resistor
Resistance value reasonably selects the capacitance of the first capacitance, the second capacitance and third capacitance, keeps the frequency that display refreshes appropriate, to change
Kind the phenomenon that coruscating of charactron, improves the display effect of charactron.
Description of the drawings
Fig. 1 provides the circuit diagram of the utility model.
In figure, eight road bus transceiver chips 1, shift register clock signal 11, storage register clock signal 12, string
Row data-signal 13, first control signal 14, second control signal 15, third control signal 16, first resistor 21, second resistance
22,3rd resistor 23, the first capacitance 31, the second capacitance 32, third capacitance 33, filter capacitor 34, pull-up power supply 41, pull-up resistor
42, power supply 5, ground terminal 6.
Specific implementation mode
The technical issues of in order to keep the utility model solved, technical solution and advantageous effect are more clearly understood, below
The utility model is described further with reference to the drawings and specific embodiments, but the utility model is not limited to described implementation
Example, on the contrary, the utility model includes whole modifications, modification and the equivalent fallen within the scope of the appended claims.
As shown in Figure 1, this circuit for improving numeral method, including eight road bus transceiver chips 1, eight tunnel buses
Wherein three signal input pins of transponder chip 1 are believed with shift register clock signal 11, storage register clock respectively
Numbers 12 are connected with serial data signal 13, and eight road bus transceiver chips 1 of Qie Gai are posted with shift register clock signal 11, storage
Storage clock signal 12 and 13 corresponding signal output pin of the serial data signal shift register with HC595 chips respectively
Clock input pin, storage register clock input pin are connected with serial date transfer pin, eight road bus transceiver chips 1
Residual signal input pin be connected with ground terminal 6, the residual signal output pin of eight road bus transceiver chips 1 is hanging；Number
Eight pins of code pipe are connected with the Q0-Q7 pins of HC595 chips respectively；Due to this circuit for improving numeral method
Improvement part is not related to HC595 chips part, therefore HC595 chips are not shown in the accompanying drawings.
Signal output pin corresponding with shift register clock signal 11 passes through first resistor 21 and HC595 chips
Shift register clock input pin is connected, and signal output pin corresponding with storage register clock signal 12 passes through second
Resistance 22 is connected with the storage register clock input pin of HC595 chips, and signal corresponding with serial data signal 13 is defeated
Go out pin by 3rd resistor 23 to be connected with the serial date transfer pin of HC595 chips；In the shift register of HC595 chips
The first capacitance 31 is connected between clock input pin and ground terminal 6, in the storage register clock input pin of HC595 chips
It is connected with the second capacitance 32 between ground terminal 6, is connected between the serial date transfer pin and ground terminal 6 of HC595 chips
There is third capacitance 33；Preferably, the resistance value all same of first resistor 21, second resistance 22 and 3rd resistor 23 and 50 Ω extremely
Between 150 Ω, the first capacitance 31, the capacitance all same of the second capacitance 32 and third capacitance 33 and 50pF to 150pF it
Between.
Three signal input pins in the residual signal input pin of eight road bus transceiver chips 1 are controlled with first respectively
Signal 14 processed, second control signal 15 are connected with third control signal 16；Signal output corresponding with second control signal 15
Pin is connected by the 4th resistance with module to be controlled, and signal output pin corresponding with third control signal 16 passes through mutual
Concatenated 5th resistance and light emitting diode are connected with power supply 5；In shift register clock signal 11, storage register
Clock signal 12, serial data signal 13, first control signal 14, second control signal 15 and third control signal 16 and pull-up electricity
Pull-up resistor 42 is equipped between source 41.Shift register clock signal 11, storage register clock signal 12, serial number it is believed that
Numbers 13, first control signal 14, second control signal 15 and third control signal 16 are exported by the I/O port of MCU module.
Eight road bus transceiver chips 1 are SN74HCT245 chips, the DIR pins and power supply of SN74HCT245 chips
5 are connected, and A1 to the A8 pins of SN74HCT245 chips are signal input pin, and B1 to the B8 pins of SN74HCT245 chips are letter
Number output pin, the VCC pin of SN74HCT245 chips are connected with power supply 5, connect between power supply 5 and ground terminal 6
Be connected to filter capacitor 34, the GND pin of SN74HCT245 chips is connected with ground terminal 6, the OE pins of SN74HCT245 chips with
Ground terminal 6 is connected.
Eight road bus transceiver chips 1 are set between MCU module and HC595 chips, and reasonably select first resistor 21,
The resistance value of second resistance 22 and 3rd resistor 23 reasonably selects the electricity of the first capacitance 31, the second capacitance 32 and third capacitance 33
Capacitance keeps the frequency that display refreshes appropriate, so as to improve charactron the phenomenon that coruscating, improves the display effect of charactron
Fruit.
The specific embodiments described herein are merely examples of the spirit of the present invention.The utility model institute
Belonging to those skilled in the art can make various modifications or additions to the described embodiments or using similar
Mode substitute, but without departing from the spirit of the present application or beyond the scope of the appended claims.
Although eight road bus transceiver chips 1, shift register clock signal 11, storage deposit is used more herein
Device clock signal 12, serial data signal 13, first control signal 14, second control signal 15, third control signal 16, first
Resistance 21, second resistance 22,3rd resistor 23, the first capacitance 31, the second capacitance 32, third capacitance 33, filter capacitor 34, pull-up
The terms such as power supply 41, pull-up resistor 42, power supply 5, ground terminal 6, but it does not preclude the possibility of using other terms.It uses
These terms are used for the purpose of more easily describing and explaining the essence of the utility model；It is additional to be construed as any type
Limitation be all contrary to the spirit of the present invention.
Claims (5)
1. a kind of circuit for improving numeral method, which is characterized in that described including eight road bus transceiver chips (1)
Eight road bus transceiver chips (1) wherein three signal input pins respectively with shift register clock signal (11), deposit
Memory register clock signal (12) is connected with serial data signal (13), and eight road bus transceiver chips (1) of Qie Gai are posted with displacement
Storage clock signal (11), storage register clock signal (12) and serial data signal (13) corresponding signal output pin
Respectively with the shift register clock input pin of HC595 chips, storage register clock input pin and serial date transfer
Pin is connected, and the residual signal input pin of the eight road bus transceiver chips (1) is connected with ground terminal (6), described
The residual signal output pin of eight road bus transceiver chips (1) is hanging；It is corresponding with shift register clock signal (11)
Signal output pin is connected by first resistor (21) with the shift register clock input pin of HC595 chips, is posted with storage
When storage clock signal (12) corresponding signal output pin is by second resistance (22) and the storage register of HC595 chips
Clock input pin is connected, and signal output pin corresponding with serial data signal (13) passes through 3rd resistor (23) and HC595
The serial date transfer pin of chip is connected；Between the shift register clock input pin and ground terminal (6) of HC595 chips
It is connected with the first capacitance (31), is connected between the storage register clock input pin and ground terminal (6) of HC595 chips
Two capacitances (32) are connected with third capacitance (33) between the serial date transfer pin and ground terminal (6) of HC595 chips.
2. the circuit according to claim 1 for improving numeral method, which is characterized in that the first resistor
(21), the resistance value all same of second resistance (22) and 3rd resistor (23) and in 50 Ω between 150 Ω, the described first electricity
Hold the capacitance all same of (31), the second capacitance (32) and third capacitance (33) and in 50pF between 150pF.
3. the circuit according to claim 1 or 2 for improving numeral method, which is characterized in that eight tunnels are total
Three signal input pins in the residual signal input pin of line transceiver chip (1) respectively with first control signal (14),
Second control signal (15) is connected with third control signal (16).
4. the circuit according to claim 3 for improving numeral method, which is characterized in that in shift register clock
Signal (11), storage register clock signal (12), serial data signal (13), first control signal (14), the second control letter
It is equipped with pull-up resistor (42) between number (15) and third control signal (16) and pull-up power supply (41).
5. the circuit according to claim 1 or 2 for improving numeral method, which is characterized in that eight tunnels are total
Line transceiver chip (1) is SN74HCT245 chips, DIR pins and power supply (5) phase of the SN74HCT245 chips
Even, A1 to the A8 pins of the SN74HCT245 chips are signal input pin, and the B1 of the SN74HCT245 chips is extremely
B8 pins are signal output pin, and the VCC pin of the SN74HCT245 chips is connected with power supply (5), in power supply electricity
Filter capacitor (34), the GND pin and ground terminal of the SN74HCT245 chips are connected between source (5) and ground terminal (6)
(6) it is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721887305.4U CN207781155U (en) | 2017-12-28 | 2017-12-28 | Circuit for improving numeral method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721887305.4U CN207781155U (en) | 2017-12-28 | 2017-12-28 | Circuit for improving numeral method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207781155U true CN207781155U (en) | 2018-08-28 |
Family
ID=63225805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721887305.4U Expired - Fee Related CN207781155U (en) | 2017-12-28 | 2017-12-28 | Circuit for improving numeral method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207781155U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974106A (en) * | 2022-08-02 | 2022-08-30 | 深圳英集芯科技股份有限公司 | LED display device, LED display method and electronic equipment |
-
2017
- 2017-12-28 CN CN201721887305.4U patent/CN207781155U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974106A (en) * | 2022-08-02 | 2022-08-30 | 深圳英集芯科技股份有限公司 | LED display device, LED display method and electronic equipment |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180828 Termination date: 20201228 |
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| CF01 | Termination of patent right due to non-payment of annual fee |