CN105760327B - Internal bus of aerospace electronic product - Google Patents
Internal bus of aerospace electronic product Download PDFInfo
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- CN105760327B CN105760327B CN201510916908.1A CN201510916908A CN105760327B CN 105760327 B CN105760327 B CN 105760327B CN 201510916908 A CN201510916908 A CN 201510916908A CN 105760327 B CN105760327 B CN 105760327B
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention provides an internal bus of an aerospace electronic product, which is used for information interaction between a main module and a plurality of slave modules, and the bus signals comprise: the bus timing is divided into two types of main module operation period using waiting and main module operation period without waiting, and each type is divided into two types of reading and writing. The bus provided by the invention is specific to aerospace electronic products, has strong universality and compatibility, and is beneficial to improving the quality and the working reliability of module interconnection signals.
Description
Technical field
The present invention relates to aerospace electron product scopes, more specifically, it is total to be related to a kind of aerospace electron interiors of products interconnection
Line.
Background technique
Currently, the type of aerospace electron product is various, widely used, work characteristics is more many and diverse, difference research and development factory is opened
The product of hair is also different therewith, and product internal module mutual contact mode is even more multifarious.Only from physically, just there is page
The multiple combinations mode such as formula, board plug type, stacked, blade type, thus intermodule signal interconnection mode be also it is each has something to recommend him, do not have
There is the interconnection specification of a versatile, compatible most products.
With Space Science and Technology gradually develop and the introducing of space industry market mechanism, the development of aerospace electron product by
Original task distribution Custom Prosthesis gradually changes to generalization, off the shelf product selection type.
In addition, being constantly progressive with the entire industry of electronic product, the integrated level raising of circuit brings properties of product
Be substantially improved: working frequency is higher and higher, data throughput capabilities significantly rise.
Under the premise of such, existing aerospace electron interiors of products mutual contact mode starts to seem unable to do what one wishes, often goes out
Now connecting excessively complexity leads to that productibility is not high, definition leads to that uniformity module is generally applicable, cabling is taken into account not without specification repeatedly
The problems such as connection while low-and high-frequency signal is with modulus signal etc..
The shutout of Some Domestic phase has started gradually to recognize such problems, has carried out centainly earlier in this regard
Research work is directed generally to for the versabus technology such as PCI, PXI, VPX being introduced into military computer, obtain
Certain achievement.But since there are functional module division mode differences, modulus compared to military computer for aerospace electron product
The special circumstances such as mixing and control operation mixing, it is difficult to above-mentioned general purpose computer bussing technique is utilized, it is temporarily not proper
Ready-made technical solution.In addition, army grade is seldom since the control chip that above-mentioned bus is related to is mostly technical grade, also very great Cheng
These technologies are limited on degree to apply in aerospace electron product.
For such status and products characteristics, the generalization of Yao Shixian aerospace electron interiors of products module interconnection, specification
Change, prior art can not be introduced directly into, it can only be a set of customized by tailor for aerospace electron product own characteristic
The definition of space product general interconnection and specification are achieved the goal with this.
Summary of the invention
For above-mentioned the problems of the prior art, the purpose of the present invention is to provide a kind of aerospace electron interiors of products is total
Line, for aerospace electron product, have stronger versatility and compatibility, be conducive to improve module interconnecting signal quality and work can
By the interconnected bus of property, the present invention is named as AECI bus (Aeroaspace Embedded Component
Interconnection BUS), the status without suitable bussing technique is changed with this, promotes aerospace electron product industry more
Develop fastly to generalization, goods-shelf type.
In order to achieve the above objectives, the technical solution adopted in the present invention is as follows:
A kind of aerospace electron interiors of products bus, for a main module and multiple information exchanges between module, always
Line signal includes: test signal, system signal, number I/O signal, miscellaneous function signal, power supply signal, clock sync signal,
Bus timing, which is divided into, uses the main module operation cycle waited and the main module operation cycle two types without using waiting, and every kind
Type is divided into reading again and writes two kinds of timing.
In addition to testing signal, remaining signal at least occupies two signaling points, forms Redundancy Design.
Bus physical layer uses coil spring hole electric connector.
The test signal includes debugging serial ports and 12 discrete test signals, wherein 6 test signals can answer
With for standard external JTAG signal.
The system signal includes 4 tunnel interrupt signals, 4 tunnel module chip selection signals, the common control signal, address signal in 7 roads
And data-signal.
The common control signal in 7 road includes: main module reset signal, is input from the outside, from module resets signal, by leading
Module provides, read signal, is provided, write signal, is provided by main module, WAIT signal by main module, by being provided from module, bus behaviour
Make cycle stretch-out, DIR signal, provided by main module, data flow direction instruction, a height of inflow main module, it is low for outflow main module,
ALE is provided by main module, address latch signal, can be cut according to from module timing requirements.
The number I/O signal includes 24 tunnel discrete digital amounts, 4 road serial differentials pair, when the serial signal that design uses
When being non-differential, using only in differential pair+end.
The miscellaneous function signal is primarily referred to as the function signal powered using accessory power supply, in the majority with analog quantity, including
The input of 16 tunnel auxiliary signals and the output of 8 tunnel auxiliary signals.
The power supply signal is divided to two kinds, and one kind is digital power signal, and another kind is auxiliary power supply signal, voltage value according to
Different demands are arranged.
The clock sync signal is divided into two kinds, and respectively SYSCLK and IOCLK, SYSCLK are system synchronised clock, uses
In machine system timing synchronization, IOCLK is I/O functional interface synchronised clock, is provided by main module, as from module corresponding function
The synchronised clock of interface.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1) the connector selection scheme under a variety of physical structures such as board plug type, stacked, blade type, is provided, model is applicable in
Enclose that wide, versatility is good, connector is coil spring type, and connection reliability is high；
2) distribution of aerospace electron product module and master-slave relationship based on the building of AECI bus, are defined, is provided multiple
From the configuration structure of module, stipulated that defer to the naming method of the module of bus specification design, product module standardizes journey
Degree is high, reusability is high；
3) 6 class bus signals, have been divided, 6 class bus signals are covered in aerospace electron product and powered, simultaneously using extensive
The multi-signals such as row, serial, number I/O, simulation, provide the intermodule access control handshake of complete set, and reserve
The a set of test signal that can flexibly define.The bus covers the demand of common aerospace electron product, can be widely applied；
4), the distribution of 6 class bus signals on the connectors is given and is explicitly defined, wherein the signal in addition to test-purpose
Two point Redundancy Design is all carried out, application reliability is high；
5) the basic timing of AECI bus, is defined, provides using waiting and not using waiting both of which, provides respectively
Specific timing requirements, and enough timing allowances have been reserved, enforceability is strong, highly-safe；
6) AECI bus signals electric requirement, is defined, using Transistor-Transistor Logic level, CMOS compatible level is Common levels,
Wide usage is strong.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is that the present invention defers to the specification that AECI bus standard is named module；
When Fig. 2 is the signal that should be met as defined in AECI bus standard of the present invention using the main module write cycles waited
Sequence；
Fig. 3 is the signal that should meet as defined in AECI bus standard of the present invention without using the main module read operation period waited
Timing；
Fig. 4 is the signal that should meet as defined in AECI bus standard of the present invention without using the main module write cycles waited
Timing；
When Fig. 5 is the signal that should be met as defined in AECI bus standard of the present invention using the main module read operation period waited
Sequence；
Fig. 6 is the embedded computer composition block diagram using AECI bus of the present invention.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, various modifications and improvements can be made.These belong to the present invention
Protection scope.
AECI bus provided by the present invention is as follows:
1) system constitutes specification
There is and be only capable of a main module in embedded computer as defined in AECI bus, is controlled by it in AECI bus
Information exchange.The configuration of AECI bus standard is supported multiple from module.
2) module design specification
Physical layer is recommended to use 276 core wire spring hole electric connectors of HMM276 series, which provides board plug type and blade
The workable plugs and sockets subfamily of formula and stacked workable series connection subfamily.In addition to testing signal, remaining signal is equal
Two signaling points are at least occupied, Redundancy Design is formed.
Corresponding module size is recommended as F2 the and F3 standard size in GJB2355.
Module name should defer to AECI bus standard module Naming conventions, carry out specification name according to Fig. 1 demonstration.
3) signal design specifications
A) signal is tested
The test signal of AECI bus definition includes that a debugging (is used with serial ports (RS232) and 12 discrete test signals
Way can customize, wherein 7 to 12 reusables are standard external JTAG signal).
B) system signal
The system signal of AECI bus definition includes 4 tunnel interrupt signals, 4 tunnel module chip selection signals, the common control letter in 7 roads
Number, address signal (addressing bit wide 20) and data-signal (data bit width 16).
Commonly use control signal in 7 tunnels
Main module reset signal (external input)；
From module resets signal (main module provides)；
Read signal (main module provides)；
Write signal (main module provides)；
WAIT signal (provides, bus operation cycle stretch-out) from module；
DIR signal (main module provides, data flow direction instruction, a height of inflow main module, low for outflow main module)；
ALE (main module provides, address latch signal, can cut according to from module timing requirements).
AECI bus supports sixteen-bit system, backward compatible 8 systems.
C) number I/O signal
The digital I/O signal of AECI bus definition is serial including 24 tunnel discrete digital amounts (allowing designer customized), 4 roads
Differential pair (RS422 or CAN).When the serial signal that uses of design is non-differential, using only in differential pair+end.
D) miscellaneous function signal
The miscellaneous function signal of AECI bus definition is primarily referred to as the function signal powered using accessory power supply, with analog quantity
It is in the majority, including the input of 16 tunnel auxiliary signals and the output of 8 tunnel auxiliary signals.When necessary miscellaneous function signal allow on this basis into
Row is customized.
E) power supply signal
The power supply signal of AECI bus definition is divided to two kinds, and one kind is digital power signal, usually+5V, supplemented by another kind
Power supply signal is helped, voltage value is arranged according to different demands.
F) clock sync signal
AECI bus definition two clock sync signals, respectively SYSCLK and IOCLK.When SYSCLK is that system is synchronous
Clock is used for machine system timing synchronization.IOCLK is I/O functional interface synchronised clock, is usually provided by main module, as from mould
The synchronised clock of block corresponding function interface.
4) electrical design specification
AECI bus signals use Transistor-Transistor Logic level, CMOS compatible level.
Input/output argument index is as follows:
VOLmin=0V, VOLmax=0.55V；
VOHmin=2.4V, VOHmax=VCC；
VILmin=-0.5V, VILmax=0.8V；
VIHmin=2V, VIHmax=5.25V；
IOLmin=IOHmin=20mA；
IILmax=IILmin=200uA.
Signal termination requires as follows:
Main module input system high level useful signal terminates 1k Ω over the ground；
Main module input system low level useful signal terminates 4.7k Ω to VCC；
4.7k Ω is terminated over the ground from module input system high level useful signal；
10k Ω is terminated to VCC from module input system low level useful signal.
5) the basic timing of AECI bus
The basic timing of AECI bus is divided into using the main module operation cycle for waiting (WAIT) and without using waiting (WAIT)
Two class of main module operation cycle, reading is divided into according to action type again in every class and writes two kinds of timing.
For above-mentioned four generic operations timing, timing requirements are clearly given in AECI bus specification, AECI bus is deferred to and sets
The module timing Design of meter specification must satisfy these requirements.
AECI bus standard provides that signal sequence shown in Fig. 2 should be met by not using the main module read operation period waited,
Time sequence parameter is shown in Table 1.
Table 1
AECI bus standard provides that signal sequence shown in Fig. 3 should be met by not using the main module write cycles waited,
Time sequence parameter is shown in Table 2.
Table 2
| Explanation | It is minimum | It is typical | It is maximum | Unit | Remarks | |
| t1 | Piece choosing effectively/release delay in address effectively/release time | 5 | 10 | ns | ||
| t8 | Effective time is selected in piece with effect, data flow direction effective delay | 5 | 20 | ns | ||
| t9 | Write low address hold time after discharging | 0 | 5 | ns | ||
| t10 | With the effect retention time | 200 | 300 | ns | ||
| t11 | Write the data flow direction retention time after discharging | 0 | 5 | ns | ||
| t12 | Data effective delay selects effective time in piece | 20 | ns | |||
| t13 | Write data hold time after discharging | 0 | 5 | ns |
AECI bus standard provides that signal sequence shown in Fig. 4 should be met using the main module read operation period of waiting, when
Order parameter is shown in Table 3.
Table 3
AECI bus standard provides that signal sequence shown in fig. 5 should be met using the main module write cycles of waiting, when
Order parameter is shown in Table 4.
Table 4
| Explanation | It is minimum | It is typical | It is maximum | Unit | Remarks | |
| t1 | Piece choosing effectively/release delay in address effectively/release time | 5 | 10 | ns | ||
| t8 | Effective time is selected in piece with effect, data flow direction effective delay | 5 | 20 | ns | ||
| t9 | Write low address hold time after discharging | 0 | 5 | ns | ||
| t11 | Write the data flow direction retention time after discharging | 0 | 5 | ns | ||
| t12 | Data effective delay selects effective time in piece | 5 | 20 | ns | ||
| t13 | Write data hold time after discharging | 0 | 5 | ns | ||
| t16 | Wait effective delay in writing effective time | 5 | 20 | ns | ||
| t17 | Release delay is write in waiting release time | 10 | 20 | 50 | ns |
Based on above-mentioned AECI bus, develop to form a series of dedicated embedded computer class product of space flight, with wherein
One kind is representative, illustrates the specific embodiment of AECI bus.
Type embedded computer composition is as shown in Figure 6.
Based on AECI bus definition, board plug type product structure is used.Built-in function is divided into according to task feature logical
Letter control and two kinds of functional units of data processing, communication control are used as from unit, wherein at data as master unit, data processing
Reason unit has carried out triple redundance design to improve reliability.
Modular connector has selected the domestic substituted type of proposed model in AECI bus specification, is also 276 points of coil spring hole
Connector.Module uses F2 standard size.
Connector is defined referring to requiring to be designed in AECI bus specification, and signal service condition is as follows:
Test signal has used the discrete test signal in 4 roads, remaining is not used；
System signal has used 3 tunnel interrupt signals and 3 tunnel module chip selection signals, commonly uses in control signal ALE is not used
Location latch signal, system are configured to 16 bit wides；
Digital I/O signal has used 8 tunnel discrete digital amounts and 2 road serial differentials to signal, remaining is not used；
Miscellaneous function signal has used 3 tunnels, as analog quantity sampling channel；
Power supply signal has used+5V as digital power signal, and another way+5V is used as accessory power supply signal；
Time synchronizing signal has used system synchronizing clock signals, and interface synchronization clock signal is not used.
The electrical design of all modules is all satisfied the requirement in AECI bus specification, and to all module input/output signals
It is terminated as required.
Master unit and from the access between unit using the main module operation cycle for using waiting, read and to write timing full
Corresponding requirements in sufficient AECI bus specification.
The type embedded computer has had been subjected to all development stage verifyings, is applied to space technology field, and does not adopt
It is compared, is had the advantage that with the similar product of AECI bus
Seriation, generalization degree are high, and part of module therein realizes direct multiplexing, product in homologous series product
Complete machine structure is the standard type cabinet in national military standard, also reusable, reduces the lead time of subsequent product significantly；
Productibility is high, and process is not related to special process, can ensure its manufacturing and production using common processes
Quality；
High reliablity, timing requirements of all intermodule communications due to being all satisfied AECI bus, communication reliability pole
Height remains to work normally under severe environmental conditions；
Connection type is easy, and main screw lift declines to a great extent, and integration degree is high；
Module plug is easy, so that debugging is more convenient.
AECI bus is shown in Table 5 the distribution of 276 core connector pinout signals.
Table 5
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring substantive content of the invention.
Claims (10)
1. a kind of aerospace electron interiors of products bus, special for a main module and multiple information exchanges between module
Sign is that bus signals include: test signal, system signal, number I/O signal, miscellaneous function signal, power supply signal, clock
Synchronization signal, bus timing are divided into the main module operation cycle using waiting and two kinds of the main module operation cycle without using waiting
Type, each type are divided into reading again and write two kinds of timing；
For four generic operation timing, bus standard provides the time sequence parameter that should meet without using the main module read operation period waited
It is as follows:
Bus standard provides that the time sequence parameter that should meet without using the main module write cycles waited is as follows:
Bus standard provides that the time sequence parameter that should meet using the main module read operation period of waiting is as follows:
Bus standard provides that the time sequence parameter that should meet using the main module write cycles of waiting is as follows:
2. aerospace electron interiors of products bus according to claim 1, which is characterized in that in addition to testing signal, remaining letter
Two signaling points number are at least occupied, Redundancy Design is formed.
3. aerospace electron interiors of products bus according to claim 1, which is characterized in that bus physical layer uses coil spring hole
Electric connector.
4. aerospace electron interiors of products bus according to claim 1, which is characterized in that the test signal includes 12
Discrete test signal, wherein 6 test signal reusables are standard external JTAG signal.
5. aerospace electron interiors of products bus according to claim 1, which is characterized in that the system signal includes 4 tunnels
Interrupt signal, 4 tunnel module chip selection signals, the common control signal in 7 roads, address signal and data-signal.
6. aerospace electron interiors of products bus according to claim 5, which is characterized in that the common control signal in 7 road
Include: main module reset signal, is input from the outside, from module resets signal, is provided by main module, read signal, given by main module
Out, write signal is provided, WAIT signal by main module, by being provided from module, bus operation cycle stretch-out, DIR signal, by main mould
Block provides, data flow direction instruction, and a height of inflow main module is low to flow out main module, ALE, is provided by main module, address latch
Signal can be cut according to from module timing requirements.
7. aerospace electron interiors of products bus according to claim 1, which is characterized in that the number I/O signal includes
24 tunnel discrete digital amounts, 4 road serial differentials pair, when the serial signal that uses of design is non-differential, using only in differential pair+
End.
8. aerospace electron interiors of products bus according to claim 1, which is characterized in that the miscellaneous function signal refers to
The function signal powered using accessory power supply, it is in the majority with analog quantity, including 16 tunnel auxiliary signals input and 8 tunnel auxiliary signals are defeated
Out.
9. aerospace electron interiors of products bus according to claim 1, which is characterized in that the power supply signal is divided to two kinds,
One kind is digital power signal, and another kind is auxiliary power supply signal, and voltage value is arranged according to different demands.
10. aerospace electron interiors of products bus according to claim 1, which is characterized in that the clock sync signal point
It is two kinds, respectively SYSCLK and IOCLK, SYSCLK are system synchronised clock, are used for machine system timing synchronization, IOCLK is
I/O functional interface synchronised clock, is provided by main module, as the synchronised clock from module corresponding function interface.
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| CN201510916908.1A CN105760327B (en) | 2015-12-10 | 2015-12-10 | Internal bus of aerospace electronic product |
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| CN108848016B (en) * | 2018-05-29 | 2020-05-12 | 珠海格力电器股份有限公司 | Household appliance data interaction bus design method |
| CN114124277A (en) * | 2021-10-28 | 2022-03-01 | 康威通信技术股份有限公司 | Time service system and method based on local bus between terminals |
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| EP2107468A1 (en) * | 2007-05-24 | 2009-10-07 | Research In Motion Limited | System and method for interfacing an electronic device with a host system |
| CN103279440A (en) * | 2013-05-10 | 2013-09-04 | 北京宇航系统工程研究所 | Bus communication method between single-machine modules |
| CN103617145A (en) * | 2013-12-04 | 2014-03-05 | 包头市稀宝博为医疗系统有限公司 | User-defined bus and achievement method thereof |
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| EP2107468A1 (en) * | 2007-05-24 | 2009-10-07 | Research In Motion Limited | System and method for interfacing an electronic device with a host system |
| CN103279440A (en) * | 2013-05-10 | 2013-09-04 | 北京宇航系统工程研究所 | Bus communication method between single-machine modules |
| CN103617145A (en) * | 2013-12-04 | 2014-03-05 | 包头市稀宝博为医疗系统有限公司 | User-defined bus and achievement method thereof |
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