CN110543224B - System and method for cooperatively resetting inner and outer multiple monitoring timers of master-slave MCU - Google Patents
System and method for cooperatively resetting inner and outer multiple monitoring timers of master-slave MCU Download PDFInfo
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- CN110543224B CN110543224B CN201910838778.2A CN201910838778A CN110543224B CN 110543224 B CN110543224 B CN 110543224B CN 201910838778 A CN201910838778 A CN 201910838778A CN 110543224 B CN110543224 B CN 110543224B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a system for cooperatively resetting multiple monitoring timers inside and outside a master-slave MCU, which comprises: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit. The main MCU chip adopts an STM32F407ZGT6 chip of a Cortex-M4 architecture; the universal GPIO port line of the STM32F407ZGT6 chip of the Cortex-M4 architecture is connected with the universal GPIO port line 1 of the slave MCU, and a pulse signal with fixed frequency is sent to the slave MCU; the nRST pin of the chip is a low-level reset pin and is connected with the universal GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI interface. Under the system of the cooperative work of the master MCU and the slave MCU, the invention cooperatively works the inner and outer 4-fold monitoring timers of the master MCU and the slave MCU to monitor the master MCU and the slave MCU respectively, and reset in time when the MCU works abnormally. The slave MCU performs external reset control on the master MCU, so that the overflow time of the monitoring timer can be flexibly adjusted, and the problem that the system cannot be reset due to abnormal operation during the period from power-on to starting of the built-in monitoring timer of the master MCU for executing complex tasks is effectively solved.
Description
Technical Field
The invention relates to the technical field of collaborative resetting of multiple monitoring timers, in particular to a system and a method for collaborative resetting of multiple monitoring timers inside and outside a master-slave MCU.
Background
The internal reset process of the microprocessor in the prior art is generally as follows: when the microprocessor works normally, the built-in monitoring timer is cleared according to the set time interval, and if the monitoring timer is not cleared in the overflow time, the microprocessor is automatically reset. However, this approach has the disadvantage of: the microprocessor executing complex tasks needs longer time from power-up to starting of the built-in monitoring timer and outputting of the clear monitoring timer signal, and if abnormal working conditions such as program running and the like occur in the period, the microprocessor cannot be reset in time, so that the system is paralyzed.
Meanwhile, the external resetting process of the microprocessor in the technology at the present stage is generally as follows: when the microprocessor works normally, a clear monitoring timer signal with fixed frequency is sent to an external monitoring timer reset circuit, and if the clear monitoring timer signal is not received by the external monitoring timer reset circuit in the overflow time, the microprocessor is judged to work abnormally, and reset control is carried out on the microprocessor. The disadvantages of this approach are: the overflow time of the monitoring timer is not adjustable, the flexibility is low, and the system which works cooperatively by a plurality of microprocessors needs the same number of monitoring timer reset circuits, occupies the surface resources of the printed circuit board, and increases the wiring difficulty and the system cost.
Disclosure of Invention
According to the technical problems, a system and a method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCU are provided. The invention mainly utilizes a system for cooperatively resetting a master-slave MCU internal and external multiple monitoring timer, which is characterized by comprising the following steps: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit.
Further, the main MCU chip adopts an STM32F407ZGT6 chip of a Cortex-M4 architecture; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and pulse signals with fixed frequency are sent to the slave MCU; the nRST pin of the chip is a low-level reset pin, is connected with the universal GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI interface.
Furthermore, the slave MCU chip adopts an STM32F103RCT6 chip of Cortex-M3 architecture; the STM32F103RCT6 chip general purpose GPIO port line 3 of the Cortex-M3 architecture is connected with the WDI pin of the monitoring timer reset circuit, sends a pulse signal with fixed frequency to the monitoring timer reset circuit, and the nRST pin is a low-level reset pin and is connected with the monitoring timer reset circuit
And the pin is connected with the reset control signal of the monitoring timer reset circuit.
Further, the monitoring timer reset circuit adopts a TPS3828 monitoring timer reset chip to provide timing monitoring and reset control with the overflow time of 1.6s for the slave MCU.
Still further, the power supply circuit includes 2 SPX5205 linear voltage stabilizing chips, converts 5.0V voltage to 3.3V voltage, and provides operating power for the master/slave MCU chip and the watchdog reset circuit.
The invention also comprises a method for cooperatively resetting the inner and outer multiple monitoring timers of the master-slave MCU, which is characterized by comprising the following steps:
step S1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and the monitoring timer reset circuit in real time;
step S2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer;
step S3: and resetting the master/slave MCU chip.
Further, the quadruple monitoring timer includes: the slave MCU chip is internally provided with a monitoring timer, the slave MCU chip monitors the monitoring timer of the master MCU chip, and the slave MCU chip is internally provided with the monitoring timer and an external monitoring timer reset circuit monitors the monitoring timer of the slave MCU.
Still further, the master MCU chip is internally provided with a monitoring timer: and when the main MCU chip works normally, clearing the built-in monitoring timer in a working cycle, and if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.
Further, the slave MCU chip monitors the master MCU chip for a timer: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal for more than 3S, judging that the master MCU is in an abnormal working state, resetting by pulling down a reset pin of the master MCU, prolonging the overflow time to be 30S, executing the step S3, and shortening to 3S after the master MCU enters the normal working state.
Further, the slave MCU embeds a monitor timer: when the slave MCU is operating normally, the built-in monitoring timer is cleared in the working cycle, if the operation is not performed for more than 13S, the built-in monitoring timer overflows, the slave MCU is judged to be in an abnormal working state, and the step S3 is executed.
Further, the external watchdog reset circuit resets the watchdog of the slave MCU: and when the slave MCU works normally, continuously sending a pulse signal with the frequency of 100Hz to the monitoring timer reset circuit, and if the monitoring timer reset circuit exceeds 1.6s and does not detect the pulse signal, judging that the slave MCU is in an abnormal working state, and resetting the slave MCU by pulling down a slave MCU reset pin.
Compared with the prior art, the invention has the following advantages:
under the system of the cooperative work of the master MCU and the slave MCU, the invention cooperatively works the inner and outer 4-fold monitoring timers of the master MCU and the slave MCU to monitor the master MCU and the slave MCU respectively, and reset in time when the MCU works abnormally. The slave MCU performs external reset control on the master MCU, so that the overflow time of the monitoring timer can be flexibly adjusted, the problem that the system cannot be reset due to abnormal operation during the period from power-on to starting of the built-in monitoring timer of the master MCU for executing complex tasks is effectively solved, and the reliability of the system is improved.
Meanwhile, the invention only uses 1 external monitoring timer reset chip, thereby effectively reducing the occupation of printed circuit board surface resources and reducing the wiring difficulty and the system cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a circuit module configuration of the present invention;
fig. 2 is a block diagram of a multi-watchdog timer co-operation process of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1-2, the present invention provides a system for cooperatively resetting multiple monitoring timers inside and outside a master-slave MCU, comprising: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit. It will be appreciated that in other embodiments, the synchronous reset system described herein may also include, for example, a feedback circuit or a recording circuit, as long as multiple monitoring and reset can be achieved.
As a preferred implementation manner, the main MCU chip adopts an STM32F407ZGT6 chip of Cortex-M4 architecture in the invention; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and pulse signals with fixed frequency are sent to the slave MCU; the nRST pin of the chip is a low-level reset pin, is connected with the universal GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI interface.
As a preferred implementation manner, the slave MCU chip adopts an STM32F103RCT6 chip of a Cortex-M3 architecture; the STM32F103RCT6 chip general purpose GPIO port line 3 of the Cortex-M3 architecture is connected with the WDI pin of the monitoring timer reset circuit, sends a pulse signal with fixed frequency to the monitoring timer reset circuit, and the nRST pin is a low-level reset pin and is connected with the monitoring timer reset circuit
And the pin is connected with the reset control signal of the monitoring timer reset circuit.
In the application, the monitoring timer reset circuit adopts a TPS3828 monitoring timer reset chip to provide timing monitoring and reset control with the overflow time of 1.6s for the slave MCU. The power supply circuit comprises 2 SPX5205 linear voltage stabilizing chips, converts 5.0V voltage into 3.3V voltage and provides working power for the master/slave MCU chips and the monitoring timer reset circuit.
Meanwhile, as a preferred implementation mode, the invention also comprises a method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCU, which comprises the following steps:
step S1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and the monitoring timer reset circuit in real time;
step S2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer;
step S3: and resetting the master/slave MCU chip.
As a preferred embodiment, the quadruple monitoring timer includes: the slave MCU chip is internally provided with a monitoring timer, the slave MCU chip monitors the monitoring timer of the master MCU chip, and the slave MCU chip is internally provided with the monitoring timer and an external monitoring timer reset circuit monitors the monitoring timer of the slave MCU.
In this embodiment, the master MCU chip has a built-in monitoring timer: and when the main MCU chip works normally, clearing the built-in monitoring timer in a working cycle, and if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.
As a preferred embodiment, the slave MCU chip monitors the master MCU chip for a timer: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal for more than 3S, judging that the master MCU is in an abnormal working state, resetting by pulling down a reset pin of the master MCU, prolonging the overflow time to be 30S, executing the step S3, and shortening to 3S after the master MCU enters the normal working state.
In this application, the slave MCU embeds a monitor timer: when the slave MCU is operating normally, the built-in monitoring timer is cleared in the working cycle, if the operation is not performed for more than 13S, the built-in monitoring timer overflows, the slave MCU is judged to be in an abnormal working state, and the step S3 is executed.
As a preferred embodiment, the external watchdog reset circuit resets the watchdog of the slave MCU: and when the slave MCU works normally, continuously sending a pulse signal with the frequency of 100Hz to the monitoring timer reset circuit, and if the monitoring timer reset circuit exceeds 1.6s and does not detect the pulse signal, judging that the slave MCU is in an abnormal working state, and resetting the slave MCU by pulling down a slave MCU reset pin.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed technology content may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (5)
1. The method for cooperatively resetting the inner and outer multiple monitoring timers of the master-slave MCU is characterized by comprising the following steps:
s1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and a monitoring timer reset circuit in real time; the quad monitoring timer includes: the slave MCU chip is internally provided with a monitoring timer, the slave MCU chip monitors the monitoring timer of the master MCU chip, and the slave MCU chip is internally provided with the monitoring timer and an external monitoring timer reset circuit monitors the monitoring timer of the slave MCU;
s2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer; the main MCU chip adopts an STM32F407ZGT6 chip of a Cortex-M4 architecture; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and pulse signals with fixed frequency are sent to the slave MCU; the nRST pin of the chip is a low-level reset pin, is connected with the universal GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI interface;
s3: and resetting the master/slave MCU chip.
2. The method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCUs according to claim 1, further characterized by: the main MCU chip is internally provided with a monitoring timer: and when the main MCU chip works normally, clearing the built-in monitoring timer in a working cycle, and if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.
3. The method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCUs according to claim 1, further characterized by: the slave MCU chip monitors the timer of the master MCU chip: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal for more than 3S, judging that the master MCU is in an abnormal working state, resetting by pulling down a reset pin of the master MCU, prolonging the overflow time to be 30S, executing the step S3, and shortening to 3S after the master MCU enters the normal working state.
4. The method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCUs according to claim 1, further characterized by: the slave MCU embeds a monitor timer: when the slave MCU is operating normally, the built-in monitoring timer is cleared in the working cycle, if the operation is not performed for more than 13S, the built-in monitoring timer overflows, the slave MCU is judged to be in an abnormal working state, and the step S3 is executed.
5. The method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCUs according to claim 1, further characterized by: the external monitor timer reset circuit monitors the monitor timer of the slave MCU: and when the slave MCU works normally, continuously sending a pulse signal with the frequency of 100Hz to the monitoring timer reset circuit, and if the monitoring timer reset circuit exceeds 1.6s and does not detect the pulse signal, judging that the slave MCU is in an abnormal working state, and resetting the slave MCU by pulling down a slave MCU reset pin.
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| CN201910838778.2A CN110543224B (en) | 2019-09-05 | 2019-09-05 | System and method for cooperatively resetting inner and outer multiple monitoring timers of master-slave MCU |
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| CN111274064A (en) * | 2020-01-15 | 2020-06-12 | 武汉兴图新科电子股份有限公司 | double-CPU system and cooperative soft reset method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101635646B (en) * | 2009-06-24 | 2012-11-28 | 中兴通讯股份有限公司 | Method and system for switching main/standby board cards |
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| JPH02142255A (en) * | 1988-11-24 | 1990-05-31 | Fujitsu Ltd | Multiple monitoring system |
| CN1916916A (en) * | 2006-08-31 | 2007-02-21 | 株洲南车时代电气股份有限公司 | Circuit and method for guaranteeing reliable configurartion of field programmable gate array |
| CN205910667U (en) * | 2016-06-08 | 2017-01-25 | 浙江科聪智能科技有限公司 | Multi -processor control circuit that resets |
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