CN110534479A - 改善第零层内介电层的填充能力的栅极及工艺方法 - Google Patents
改善第零层内介电层的填充能力的栅极及工艺方法 Download PDFInfo
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Abstract
本发明公开了一种改善第零层内介电层的填充能力的栅极,在半导体基板上具有多个栅极,所述多个栅极之间具有一定间距;所述栅极的剖面呈梯形,即栅极剖面的顶部宽度小于底部的宽度。本发明通过形成一种剖面呈梯形结构的栅极以取代传统的垂直型栅极设计,从而增加栅极之间沟槽顶部的开口距离,降低其深宽比,以此有效改善第零层内介电层制备过程中填充能力有限的问题,从而减少空洞的形成,提高器件的性能进而提高产品良率。本发明所述的工艺方法简单易于实施。
Description
技术领域
本发明涉及半导体器件制造工艺领域,特别是指一种在半导体制造的后栅极工艺中改善第零层内介电层的填充能力的栅极。
本发明还提供所述栅极的工艺方法。
背景技术
互补型金属氧化物半导体器件(CMOS :Complementary Metal-Oxide-Semiconductor)制造技术沿着摩尔定律不断发展,伴随器件尺寸的不断缩小,栅极介质的厚度不断减薄,栅极的漏电流也随之增大,在5nm以下,由于电子的隧穿效应,SiO2作为栅极介质所产生的漏电流已经无法接受。采用高介电常数(high-k)介质取代SiO2看可以有效降低等效二氧化硅绝缘厚度,同时可得到较大的栅极介质的物理厚度,从而在源头堵住栅极漏电。目前在32nm节点中可以采用先栅极(gate-first)工艺和后栅极(gate-last)工艺两种制程来获得高介电常数金属栅极(HKMG:High-K Metal Gate)结构。在28nm HK后栅极工艺,即替代金属栅(RMG:Replacement Metal Gate)工艺中,High-K材料不用经历高温过程,可以有效降低阈值电压Vt的漂移,从而提高器件的可靠性,但是RMG工艺需包含更多工艺步骤,给制造带来更多的挑战。
在RMG工艺中,不同栅极之间需要填充一种绝缘材料来分开,即第零层内介电层(ILD0))。然而随着器件尺寸的微缩,受Design Rule的限制,栅极之间的空隙越来越小,沟槽的深宽比变大,在填充内介电层的过程中不可避免的会生成空洞(Void ),在后续制程中,由于空洞顶部ILD0比较薄,极易被酸侵蚀或者再研磨过程中被消耗掉,在两个栅极之间形成一开放的孔槽,从而失去隔离功能。
为改善ILD0层的填充性能,现在普遍选用填充能力更好的ILD0制备工艺手段,如高深宽比工艺(HARP:High Aspect Ratio Process),然而由于该工艺直接采用O2和TEOS(正硅酸乙酯)发生热化学反应,没有等离子体辅助,所以仍会有空洞形成。
发明内容
本发明所要解决的技术问题在于提供一种改善第零层内介电层的填充能力的栅极结构。
本发明所述的改善第零层内介电层的填充能力的栅极,包括:提供一半导体基板,在所述半导体基板上具有多个栅极,所述多个栅极之间具有一定间距。
所述栅极的剖面呈梯形,即栅极剖面的顶部宽度小于底部的宽度。
进一步的改进是,所述的多个栅极之间,还填充有第零层内介电层。
进一步的改进是,所述的第零层内介电层为绝缘介质层,优选地为氧化硅。
进一步的改进是,所述的半导体基板,为半导体硅衬底,或者是砷化镓、锗硅衬底,或者是外延。
进一步的改进是,所述的梯形结构的栅极,能增大栅极之间的开口宽度,具有更高的填充性能。
进一步的改进是,所述的栅极与半导体基板之间,还具有栅介质层。
为解决上述问题,本发明提供一种改善第零层内介电层的填充能力的工艺方法,以形成上述的栅极结构,其工艺包含:
步骤一,提供一半导体基板,在所述半导体基板上依次淀积栅介质层、第一多晶硅层、氮化硅硬掩模层、氧化硅硬掩模层以及无定形碳层。
步骤二,通过光刻定义栅极的高度及宽度,通过控制刻蚀模式,形成多个平行的、剖面形状为上小下大的梯形栅极;再去除顶部的无定形碳层。
步骤三,在所述栅极两侧形成第一层侧墙。
步骤四,进行LDD注入。
步骤五,在所述栅极两侧再形成第二层侧墙。
步骤六,再进行离子注入,形成器件的源区、漏区。
步骤七,去除光刻胶,去除顶部的硬掩模层,包括氧化硅硬掩模层、氮化硅硬掩模层;去除第二层侧墙。
步骤八,在整个半导体基板表面淀积一层钨接触孔刻蚀停止层。
步骤九,在整个半导体基板上再淀积一层第零层介电层,填充栅极之间的空隙。
进一步的改进是,所述步骤三中,形成第一层侧墙的工艺包含沉积膜层、刻蚀以及湿法清洗工艺。
进一步的改进是,所述步骤四中,形成LDD的工艺包含光刻、离子注入、干法灰化以及湿法清洗工艺;根据不同的器件需求形成不同器件的LDD。
进一步的改进是,所述步骤五中,形成第一层侧墙的工艺包含沉积膜层、刻蚀以及湿法清洗工艺。
进一步的改进是,所述步骤六中,形成器件的源区、漏区的工艺包含光刻、离子注入、干法灰化以及湿法清洗工艺;根据不同的器件需求形成不同器件的LDD。
进一步的改进是,所述步骤七中,通过光刻、刻蚀以及湿法清洗标准工艺进行光刻胶回刻过程,将栅极上方的硬掩膜层去除,消除宽窄栅极之间的高度落差。
进一步的改进是,所述步骤八中,采用化学气相沉积工艺生长一层具有拉应力的钨接触孔刻蚀停止层。
进一步的改进是,所述步骤九中,采用高深宽比工艺在栅极之间的空隙中填充绝缘介质层。
本发明所述的改善第零层内介电层的填充能力的栅极结构,通过形成一种剖面呈梯形结构的栅极以取代传统的垂直型栅极设计,从而增加栅极之间沟槽顶部的开口距离,降低其深宽比,以此有效改善第零层内介电层制备过程中填充能力有限的问题,从而减少空洞的形成,提高器件的性能进而提高产品良率。本发明所述的工艺方法简单易于实施。
附图说明
图1 是现有的填充工艺在完成填充之后栅极之间具有空隙的示意图。
图2 是本发明提供的栅极的结构,其剖面呈现上小下大的梯形结构,能增大栅极之间沟槽的开口大小,有利于填充。
图3~11 是本发明提供的工艺方法步骤图。
附图标记说明
1是衬底,2是多晶硅(栅极),3是空洞或缝隙,4是第零层内介电层ILD0,5是栅介质层,6是氮化硅硬掩模层,7是氧化硅硬掩模层,8是无定形碳层,9是第一层侧墙,10是LDD,11是第二层侧墙,12是源/漏区,13是钨接触孔刻蚀停止层。
具体实施方式
为了使本发明的内容更加清楚易懂,下面结合具体实施例和附图对本发明的内容进行详细描述,但本发明所涉及的技术内容不仅限于所给出的具体实施例。
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比率,仅用以方便、明晰地辅助说明本发明实施例的目的。
如图1所示,在32nm以下的工艺节点中,受设计规则的限制,栅极之间的空隙越来越小,栅极之间形成的沟槽的深宽比变大,在栅极之间的空隙中填充内介电层时,由于深宽比变大,制程工艺的填充能力有限,会不可避免的会生成空洞。这使得在后续制程中,由于空洞顶部的ILD0层比较薄,极易被酸侵蚀或者在研磨过程中被消耗掉,在两个栅极之间形成一开孔的孔槽,从而失去隔离功能。为改善ILD0层的填充性能,本发明提供一种剖面结构呈梯形结构的栅极以取代传统的垂直型栅极设计,从而增加栅极沟槽顶部的开口距离,降低其深宽比,以期有效改善改善第零层内介电层制备过程中填充能力有限的问题,从而减少空洞的形成,提高器件的性能进而提高产品良率。如图2所示,在一半导体基板上具有多个平行的栅极,所述多个栅极之间具有一定间距。栅极之间填充第零层内介电层,本发明增大的栅极之间沟槽的开口能提高沟槽的填充能力,将填充的空洞或者空隙降低或消除。
为实现上述栅极结构,本发明提供一种改善第零层内介电层的填充能力的栅极结构的工艺方法,其一实施例结合附图3~11说明如下:
步骤一,如图3所示,在基于半导体制程的器件晶圆衬底上依次沉积栅介质层、第一多晶硅层、以及氮化硅硬掩膜层和氧化硅硬掩膜层,最上层覆盖一层无定形碳层。
步骤二,通过光刻定义栅极的宽度和高度,通过控制刻蚀模式,比如通过控制干法刻蚀的角度等,获得剖面结构为上窄下宽的梯形的栅极结构。
步骤三,在衬底表面沉积一层氮化膜,采用刻蚀以及湿法清洗标准工艺制备第一层侧墙。
步骤四,进行光刻、注入、干法灰化以及湿法清洗标准工艺的浅源、漏离子注入,形成器件的LDD。针对不同的器件,需要根据器件需求定义不同器件的LDD。
步骤五,循环工艺,在衬底表面再沉积一层氮化膜,刻蚀以及湿法清洗标准工艺制备第二侧墙。
步骤六,通过光刻定义,进行离子注入、干法灰化以及湿法清洗标准工艺,形成器件的源区、漏区;依据器件需求定义不同器件的源漏极。
步骤七,通过光刻、刻蚀以及湿法清洗标准工艺进行光刻胶回刻过程(PR EtchBack,PREB),将栅极的氧化硅硬掩膜层去除,消除宽窄栅极之间的高度落差,使栅极顶部处于同一平面上。再将第二侧墙去除。
步骤八,采用化学气相沉积技术生长一层具有拉应力的钨接触孔刻蚀停止层。
步骤九,采用高深宽比工艺在栅极空隙间填充绝缘的氧化硅,从而获得无空洞的第零层内介电层ILD0层。
后续工艺还包括对ILD0层进行CMP工艺以使表面平坦化,CPM研磨至磨掉栅极顶部的钨接触孔刻蚀停止层,以使原形成栅极的多晶硅露出。基于后栅极工艺,将该多晶硅移除,然后淀积金属层将原多晶硅去除后形成的空间填满,形成金属栅极。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (14)
1.一种改善第零层内介电层的填充能力的栅极,其特征在于:提供一半导体基板,在所述半导体基板上具有多个栅极,所述多个栅极之间具有一定间距;
所述栅极的剖面呈梯形,即栅极剖面的顶部宽度小于底部的宽度。
2.如权利要求1所述的改善第零层内介电层的填充能力的栅极,其特征在于:所述的多个栅极之间,还填充有第零层内介电层。
3.如权利要求2所述的改善第零层内介电层的填充能力的栅极,其特征在于:所述的第零层内介电层为绝缘介质层,优选地为氧化硅。
4.如权利要求1所述的改善第零层内介电层的填充能力的栅极,其特征在于:所述的半导体基板,为半导体硅衬底,或者是砷化镓、锗硅衬底,或者是外延。
5.如权利要求1所述的改善第零层内介电层的填充能力的栅极,其特征在于:所述的梯形结构的栅极,能增大栅极之间的开口宽度,具有更高的填充性能。
6.如权利要求1所述的改善第零层内介电层的填充能力的栅极,其特征在于:所述的栅极与半导体基板之间,还具有栅介质层。
7.一种改善第零层内介电层的填充能力的工艺方法,其特征在于:包含:
步骤一,提供一半导体基板,在所述半导体基板上依次淀积栅介质层、第一多晶硅层、氮化硅硬掩模层、氧化硅硬掩模层以及无定形碳层;
步骤二,通过光刻定义栅极的高度及宽度,通过控制刻蚀模式,形成多个平行的、剖面形状为上小下大的梯形栅极;再去除顶部的无定形碳层;
步骤三,在所述栅极两侧形成第一层侧墙;
步骤四,进行LDD注入;
步骤五,在所述栅极两侧再形成第二层侧墙;
步骤六,再进行离子注入,形成器件的源区、漏区;
步骤七,去除光刻胶,去除顶部的硬掩模层,包括氧化硅硬掩模层、氮化硅硬掩模层;去除第二层侧墙;
步骤八,在整个半导体基板表面淀积一层钨接触孔刻蚀停止层;
步骤九,在整个半导体基板上再淀积一层第零层介电层,填充栅极之间的空隙。
8.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤三中,形成第一层侧墙的工艺包含沉积膜层、刻蚀以及湿法清洗工艺。
9.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤四中,形成LDD的工艺包含光刻、离子注入、干法灰化以及湿法清洗工艺;根据不同的器件需求形成不同器件的LDD。
10.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤五中,形成第一层侧墙的工艺包含沉积膜层、刻蚀以及湿法清洗工艺。
11.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤六中,形成器件的源区、漏区的工艺包含光刻、离子注入、干法灰化以及湿法清洗工艺;根据不同的器件需求形成不同器件的LDD。
12.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤七中,通过光刻、刻蚀以及湿法清洗标准工艺进行光刻胶回刻过程,将栅极上方的硬掩膜层去除,消除宽窄栅极之间的高度落差。
13.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤八中,采用化学气相沉积工艺生长一层具有拉应力的钨接触孔刻蚀停止层。
14.如权利要求7所述的改善第零层内介电层的填充能力的工艺方法,其特征在于:所述步骤九中,采用高深宽比工艺在栅极之间的空隙中填充绝缘介质层。
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