CN110534409B - Method for epitaxial growth of GaAs on silicon substrate and semiconductor device manufactured by method - Google Patents
Method for epitaxial growth of GaAs on silicon substrate and semiconductor device manufactured by method Download PDFInfo
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- CN110534409B CN110534409B CN201910713563.8A CN201910713563A CN110534409B CN 110534409 B CN110534409 B CN 110534409B CN 201910713563 A CN201910713563 A CN 201910713563A CN 110534409 B CN110534409 B CN 110534409B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
Abstract
The invention relates to a method for extending GaAs on a silicon substrate and a manufactured semiconductor device. The method comprises the following steps: forming regularly and densely distributed corrosion pits on a silicon substrate; growing GaAs for the first time at low temperature in the etch pits; performing first ion implantation and annealing on the GaAs grown at the first low temperature; performing second low-temperature GaAs growth after the first ion implantation and annealing; performing secondary ion implantation and annealing on the GaAs grown at the second low temperature; and growing GaAs at high temperature after the second ion implantation and annealing. The invention realizes the high-efficiency epitaxy of the silicon device and the upper GaAs, avoids using a Ge intermediate layer, improves the material quality, can greatly reduce the thickness of the buffer layer by adopting an epitaxy mode, and realizes the lightness and thinness of the silicon-based GaAs material.
Description
Technical Field
The invention relates to the field of semiconductor materials, in particular to a method for extending GaAs on a silicon substrate and a manufactured semiconductor device.
Background
Modern integrated circuits based on silicon-based CMOS technology are continuously advancing in integration level, power consumption and device characteristics as the feature size of CMOS devices is continuously shrinking. On the other hand, compound semiconductor devices and integrated circuits have been developed in the fields of ultra-high-speed circuits, microwave circuits, terahertz circuits, optoelectronic integrated circuits, and the like. Because the silicon-based semiconductor CMOS chip and the compound semiconductor chip are difficult to produce in the same wafer factory and can not realize process compatibility, if the silicon-based semiconductor CMOS chip and the compound semiconductor chip are organically combined, the problems that the device selection is limited in the field of integrated circuit design and devices made of different materials can not be mixed and integrated are solved, and the design and the performance of the integrated circuit are certainly greatly improved.
The realization of the epitaxy of the GaAs material on the silicon-based semiconductor is an important way for realizing the integration of a silicon device and a GaAs-based device, and the manufacturing capability of a heterogeneous integrated circuit can be improved inevitably.
In the prior art, the epitaxy of GaAs is realized mainly by growing Ge on a silicon substrate and then growing GaAs, and the problems of the technology are as follows: ge diffusion problems are severe and can degrade material quality.
Disclosure of Invention
The invention aims to provide a method for extending GaAs on a silicon substrate, which realizes the high-efficiency extension of a silicon device and the upper GaAs, avoids using a Ge intermediate layer, improves the material quality, can greatly reduce the thickness of a buffer layer by adopting an extension mode, and realizes the lightness and thinness of a silicon-based GaAs material.
In order to achieve the above purpose, the invention provides the following technical scheme:
a method of epitaxial GaAs on a silicon substrate comprising the steps of:
step a: forming regularly and densely distributed corrosion pits on a silicon substrate;
step b: growing GaAs for the first time at low temperature in the etch pits;
step c: performing first ion implantation and annealing on the GaAs grown at the first low temperature;
step d: performing second low-temperature GaAs growth after the first ion implantation and annealing;
Step e: performing secondary ion implantation and annealing on the GaAs grown at the second low temperature;
step f: and growing GaAs at high temperature after the second ion implantation and annealing.
The method achieves the following technical effects:
the buffer layer adopted by the invention is doped by GaAs grown at low temperature and injected ions, so that on one hand, a Ge intermediate layer is avoided, the problem of Ge diffusion is avoided, and the material quality is improved; on the other hand, the quality optimization of the GaAs epitaxial material is realized by the GaAs growth technology, ion implantation, activation and the like in the over-corrosion pit, the thickness of the buffer layer can be greatly reduced, and the lightness and thinness of the silicon-based GaAs material are realized. In addition, the invention adopts simple procedures, and half of the procedures adopt the same operation, thus realizing the high-efficiency epitaxy of GaAs.
In addition, the method and the process conditions of each step are optimized, and the method and the process conditions are specifically as follows.
Preferably, the etch pits are cubic pits with a depth of 500 nm-1 μm, and are preferably obtained by dry etching combined with wet etching.
In order to improve the uniformity of the material quality, the distribution of the etch pits needs to have a certain regularity (such as an array with equal spacing or concentric circles, etc.), the shape of the pits is preferably symmetrical, such as typical cubic pits, and the depth can be 500nm, 700nm, 900nm, 1 μm, etc. And preferably, dry etching and wet etching are combined to obtain the etch pits in combination with the physical and chemical properties of silicon.
Preferably, after the first low-temperature growth of GaAs and before the first ion implantation and annealing, the method further includes: and (5) chemically and mechanically polishing.
The existence of the corrosion pit during the first low-temperature growth of GaAs easily causes the unevenness of the surface of the silicon wafer, so the chemical mechanical polishing (CMP polishing) procedure is added to solve the problem and improve the material quality.
Preferably, the chemical mechanical polishing is performed until the surface roughness is between 2nm and 10 nm.
Preferably, the thickness of the first low-temperature-grown GaAs is 700nm to 2 μm.
The low-temperature growth GaAs of the invention refers to the conventional low-temperature growth temperature in the field, such as typical growth at 450-550 ℃.
Generally, the thickness of the first low temperature grown GaAs is greater than or equal to the depth of the etch pits, preferably 700nm to 2 μm.
Preferably, the first ion implantation is: implanting silicon ions to a depth of 100-120 nm.
Preferably, the temperature of the first annealing is 550-650 ℃, and the time is 1-3 min.
Preferably, the thickness of the second low-temperature-grown GaAs is 80nm to 120 nm.
Preferably, the second ion implantation is: be ions are implanted into the substrate to a depth of 100-120 nm.
Silicon ions and Be ions are respectively injected twice, so that epitaxial defects can Be effectively reduced, and the material quality is improved.
Preferably, the temperature of the second annealing is 550-650 ℃, and the time is 1-3 min.
The thickness of the high temperature grown GaAs depends on the material requirements.
The high-temperature growth GaAs of the invention refers to the conventional high-temperature growth temperature in the field, such as the typical growth at 600-700 ℃.
In summary, compared with the prior art, the invention achieves the following technical effects:
(1) the Ge intermediate layer is avoided, and the material quality is improved;
(2) the thickness of the buffer layer is greatly reduced, and the silicon-based GaAs material is light and thin;
(3) and realizing the high-efficiency epitaxy of the silicon-based GaAs.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
Fig. 1 is a flowchart of a method provided in embodiment 1 of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
Example 1
A method of epitaxial GaAs on a silicon substrate, as shown in fig. 1, comprising the steps of:
1) dry etching and wet etching are carried out on a silicon substrate body to form regularly and densely distributed cubic corrosion pits with the depth of 500 nm;
2) growing a GaAs material in a pit of the silicon wafer at a low temperature, wherein the thickness of the GaAs material is 700 nm;
3) carrying out CMP polishing on the silicon-based epitaxial wafer until the surface roughness is 2-10 nm;
4) ion implantation: implanting silicon ions with the implantation depth of 100 nm;
5) high-temperature annealing: at 550 ℃, the time is 3 min;
6) growing GaAs material on the silicon wafer at low temperature, wherein the thickness of the GaAs material is 80 nm;
7) ion implantation: implanting Be ions with the implantation depth of 100 nm;
8) high-temperature annealing: at 550 ℃, the time is 3 min;
9) and growing the high-quality GaAs material at high temperature.
Example 2
A method of epitaxial GaAs on a silicon substrate comprising the steps of:
1) dry etching and wet etching are carried out on a silicon substrate to form regularly and densely distributed cubic corrosion pits with the depth of 1 mu m;
2) growing a GaAs material in a pit of the silicon wafer at a low temperature, wherein the thickness of the GaAs material is 1.5 mu m;
3) carrying out CMP polishing on the silicon-based epitaxial wafer until the surface roughness is 2-10 nm;
4) ion implantation: implanting silicon ions to the depth of 120 nm;
5) high-temperature annealing: 650 ℃ for 1 min;
6) Growing GaAs material on the silicon wafer at low temperature, wherein the thickness is 120 nm;
7) ion implantation: implanting Be ions with the implantation depth of 120 nm;
8) high-temperature annealing: 650 ℃ for 1 min;
9) and growing the high-quality GaAs material at high temperature.
Example 3
A method of epitaxial GaAs on a silicon substrate comprising the steps of:
1) dry etching and wet etching are carried out on a silicon substrate to form regularly and densely distributed cubic corrosion pits with the depth of 1 mu m;
2) growing a GaAs material in a pit of the silicon wafer at a low temperature, wherein the thickness of the GaAs material is 1.5 mu m;
3) carrying out CMP polishing on the silicon-based epitaxial wafer until the surface roughness is 2-10 nm;
4) ion implantation: implanting silicon ions with the implantation depth of 100 nm;
5) high-temperature annealing: at 600 deg.C for 1 min;
6) growing GaAs material on the silicon wafer at low temperature, wherein the thickness is 100 nm;
7) ion implantation: implanting Be ions with the implantation depth of 100 nm;
8) high-temperature annealing: at 600 deg.C for 1 min;
9) and growing the high-quality GaAs material at high temperature.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A method of epitaxial GaAs on a silicon substrate, comprising the steps of:
step a: forming regularly and densely distributed corrosion pits on a silicon substrate, wherein the corrosion pits are cubic pits with the depth of 500 nm-1 mu m;
step b: growing GaAs in the corrosion pit at a low temperature for the first time, wherein the thickness of the GaAs is 700 nm-2 mu m;
step c: performing first ion implantation and annealing on the GaAs grown at the first low temperature;
step d: performing secondary low-temperature growth of GaAs after the first ion implantation and annealing, wherein the thickness is 80-120 nm;
step e: performing second ion implantation and annealing after the second low-temperature growth of GaAs;
step f: and growing GaAs at high temperature after the second ion implantation and annealing.
2. The method of claim 1, wherein the etch pits are obtained by dry etching in combination with wet etching.
3. The method of claim 1, further comprising, after the first low temperature growth of GaAs and before the first ion implantation, annealing: chemical mechanical polishing;
and chemically and mechanically polishing until the surface roughness is 2 nm-10 nm.
4. The method of claim 1, wherein the first ion implantation is: implanting silicon ions to a depth of 100-120 nm.
5. The method according to claim 4, wherein the temperature of the first annealing is 550-650 ℃ and the time is 1-3 min.
6. The method of claim 1, wherein the second ion implantation is: be ions are implanted into the substrate to a depth of 100-120 nm.
7. The method according to claim 6, wherein the temperature of the second annealing is 550-650 ℃ and the time is 1-3 min.
8. A semiconductor device, characterized in that it is obtained by the method according to any one of claims 1 to 7.
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Citations (4)
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| US20020000610A1 (en) * | 2000-06-30 | 2002-01-03 | Jang Min Sik | Method for manufacturing a device separation film in a semiconductor device |
| US20080277686A1 (en) * | 2007-05-08 | 2008-11-13 | Huga Optotech Inc. | Light emitting device and method for making the same |
| CN102034689A (en) * | 2009-10-08 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| CN102244007A (en) * | 2011-07-22 | 2011-11-16 | 中国科学院半导体研究所 | Preparation of silicon-based gallium arsenide material by utilizing V-shaped groove |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000610A1 (en) * | 2000-06-30 | 2002-01-03 | Jang Min Sik | Method for manufacturing a device separation film in a semiconductor device |
| US20080277686A1 (en) * | 2007-05-08 | 2008-11-13 | Huga Optotech Inc. | Light emitting device and method for making the same |
| CN102034689A (en) * | 2009-10-08 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| CN102244007A (en) * | 2011-07-22 | 2011-11-16 | 中国科学院半导体研究所 | Preparation of silicon-based gallium arsenide material by utilizing V-shaped groove |
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