CN110517993A - Plate grade fan-out packaging structure with high-cooling property and preparation method thereof - Google Patents
Plate grade fan-out packaging structure with high-cooling property and preparation method thereof Download PDFInfo
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- CN110517993A CN110517993A CN201910865147.XA CN201910865147A CN110517993A CN 110517993 A CN110517993 A CN 110517993A CN 201910865147 A CN201910865147 A CN 201910865147A CN 110517993 A CN110517993 A CN 110517993A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
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- 239000002184 metal Substances 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 claims description 29
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- 229910052802 copper Inorganic materials 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
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- 238000005538 encapsulation Methods 0.000 claims description 9
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- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention discloses a kind of plate grade fan-out packaging structure and preparation method thereof with high-cooling property.Wherein, plate grade fan-out packaging structure with high-cooling property includes: support plate, including the first encapsulated layer and the heat conducting frame that is packaged in the first encapsulated layer, the first encapsulated layer has first side and a second side, heat conducting frame along its thickness direction one side adjacent to the first encapsulated layer first side；Thermal paste is affixed on first side；Chip is affixed in thermal paste, and the front of chip is directed away from the side of support plate；Encapsulating structure is located in thermal paste, and chip package is in encapsulating structure.Under hundreds of mm size ranges permanent thermal paste and high-intensitive support plate, the warpage issues occurred when substantially improving chip package can be arranged in multiple chip backs simultaneously in the present invention.After chip package and cutting, the thermal paste and high-intensitive support plate can be used as radiator structure, not only realize the high efficiency heat radiation of chip, but also realize the recycling of support plate.
Description
Technical field
The present invention relates to technical field of electronic encapsulation, and in particular to a kind of plate grade fan-out packaging structure with high-cooling property
And preparation method thereof.
Background technique
Chip high-density packages are widely paid attention to by industrial circle.In recent years, big plate grade fan-out package technology achieves length
It is in progress enough, big plate grade fan-out package area is smaller, without substrate and intermediary layer；Encapsulation chip thickness is thinner, and number of pins is close
Degree is also bigger；More importantly the chip of the technique has lower thermal impedance, better electric property, can preferably meet
Terminal market is to chip miniaturization and high performance demand.
With the development of big plate grade fan-out package technology, smaller encapsulating structure is continued to bring out.Chip mainly leads to
The substrate of large area is crossed to radiate, and the chip of plate grade fan-out package does not have substrate, and encapsulation is smaller, leads to core
The cooling surface area of piece is also just smaller, and this requires the heating conduction of packaged chip is good enough；Currently, by chip heat
The main method for being transmitted to package outside more quickly is using the higher material of thermal conductivity and optimized packaging structure.
With the development of big plate grade fan-out package technology, encapsulating structure is more and more thinner.After encapsulating structure is thinning, encapsulation
The rigidity of structure significantly reduces, and encapsulates intracorporal material thermal expansion coefficient (CTE, Coefficient Thermal
Expansion) difference is big, it is easier to deform, warpage is caused to significantly increase, this will affect the yield of chip package.To reduce envelope
Warpage is filled, in the improvement on the one hand showing material property, vertical carrier on the other hand can be used, avoids contact with the side such as substrate
Formula slows down warpage issues, such as Manz equipment asked using the horizontal transmission mode of double rollers conveying stabilizer to slow down warpage
Topic.
Summary of the invention
One of the objects of the present invention is to provide a kind of plate grade fan-out packaging structure with high-cooling property, can reduce and stick up
Qu Wenti improves chip cooling efficiency.
The second object of the present invention is to provide a kind of preparation method of plate grade fan-out packaging structure with high-cooling property,
The warpage issues occurred when can improve chip package realize the high efficiency heat radiation of chip and the recycling of support plate.
To achieve this purpose, the present invention adopts the following technical scheme:
On the one hand, a kind of plate grade fan-out packaging structure with high-cooling property is provided, comprising:
Support plate, the support plate include the first encapsulated layer and the heat conducting frame that is packaged in first encapsulated layer, and described the
One encapsulated layer have first side and second side, the heat conducting frame along its thickness direction one side adjacent to first envelope
Fill the first side of layer；
Thermal paste, the thermal paste are affixed on the first side；
Chip, the chip are affixed in the thermal paste, and the front of the chip is directed away from the side of the support plate；
Encapsulating structure, the encapsulating structure is located in the thermal paste, and the chip package is in the encapsulating structure.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, the heat conducting frame using Cu,
One of Al, steel or Graphene material are made.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, the encapsulating structure includes:
Second encapsulated layer, the chip package is in second encapsulated layer；
Transport layer and again wiring layer, positioned at the side of second encapsulated layer far from the support plate, the one of the transport layer
The I/O interface of side and the chip is electrically connected, and the other side is electrically connected by copper post and the wiring layer again, described to be routed again
Layer has pad area and non-pad area；
Solder mask, the solder mask is located at described in the side of second encapsulated layer far from the support plate and covering to be routed again
The non-pad area and the transport layer of layer expose to the region of the wiring layer again；
The pad area of metal coupling, the metal coupling and the wiring layer welds.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, the transport layer includes being affixed on institute
The seed layer stating the dielectric layer on the second encapsulated layer and being attached on the dielectric layer, the dielectric layer have along its thickness direction
The through-hole for keeping the I/O interface of the chip exposed, the seed layer extends in the through-hole electrically to be connected with the I/O interface
It connects.
On the other hand, a kind of preparation method of plate grade fan-out packaging structure with high-cooling property, including following step are provided
It is rapid:
S10, heat conducting frame is provided, processing is packaged to the heat conducting frame using plastic packaging material and forms the first encapsulated layer,
And make the one side of the heat conducting frame adjacent to the first side of first encapsulated layer, support plate is made；
S20, thermal paste and several chips are provided, so that the front of the chip is faced away from the side of the support plate, passes through
The chip is affixed on the support plate adjacent to the side of the heat conducting frame by the thermal paste；
S30, it is packaged processing to the chip, and the I/O interface of the chip is drawn and is electrically connected with metal coupling
It connects.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, step S30 is specifically included:
S31, processing the second encapsulated layer of formation is packaged to the chip using plastic packaging material；
S32, transport layer is made on second encapsulated layer, keeps the I/O interface of the chip and the transport layer electrical
Connection；
S33, wiring layer again is made in the transport layer；
S34, solder mask is made far from the side of the support plate in second encapsulated layer, made described in the solder mask covering
The non-pad area of wiring layer and the pad area of the wiring layer again is made to expose to the solder mask；
S35, metal coupling is provided, the metal coupling is implanted into the pad area.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, step S32 is specifically included:
S32a, dielectric layer is provided, the dielectric layer is affixed on second encapsulated layer；
S32b, laser drill processing is carried out to the dielectric layer, the dielectric layer is made to form through-hole along its thickness direction, with
Keep the I/O interface of the chip exposed；
S32c, seed layer is formed in the dielectric layer and the through-hole by vacuum sputtering, the dielectric layer and described
Seed layer forms the transport layer.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, step S33 is specifically included:
S33a, light-sensitive surface is provided, the light-sensitive surface is attached in the transport layer；
S33b, pass through exposure, development treatment, being formed on the light-sensitive surface makes the exposed seed layer in the light-sensitive surface
Figure；
S33c, electroplating processes are carried out to the figure and the through-hole, copper post is formed in the through-hole, in the figure
Wiring layer, the wiring layer again are electrically connected by the I/O interface of the copper post and the chip again described in interior formation；
S33d, the remaining light-sensitive surface of removal.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, step S34 is specifically included:
S34a, it is removed rear exposed seed layer to the light-sensitive surface is etched, to remove the seed layer；
Photosensitive-ink is coated on S34b, dielectric layer exposed after removing seed layer, forms solder mask after solidification, is made described
Solder mask covers the non-pad area of wiring layer again and the pad area of the wiring layer again is made to expose to the solder mask.
As a kind of preferred embodiment of the plate grade fan-out packaging structure with high-cooling property, the ingredient of the thermal paste includes
Graphene, silica gel, silicone grease, methylvinyl-polysiloxane mixture, methyl hydrogen based polysiloxane mixture, aluminium oxide.
Beneficial effects of the present invention: heat conducting frame is packaged in the first encapsulated layer and forms support plate by the present invention, and chip is led to
It crosses thermal paste to be attached on support plate and be packaged, support plate plays a supporting role to the encapsulation of chip.After chip package and cutting,
The heat generated when chip operation is transferred on heat conducting frame by thermal paste, by heat conducting frame by the heat derives of chip,
Improve the radiating efficiency of chip.Be not necessarily to tear open bonding removal support plate during chip package, and the high intensity of heat conducting frame and
The characteristic that the thermal expansion coefficient of first encapsulated layer and the second encapsulated layer matches can be effectively improved the warpage occurred when chip package
Problem, support plate can be used as the radiator structure of chip after cutting, not only realize the high efficiency heat radiation of chip, but also realize support plate again
It utilizes.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described.It should be evident that drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the top view of support plate described in the embodiment of the present invention.
Fig. 2 is the cross-sectional view of support plate described in the embodiment of the present invention.
Fig. 3 is the cross-sectional view that thermal paste described in the embodiment of the present invention is affixed on support plate.
Fig. 4 is the cross-sectional view that chip described in the embodiment of the present invention is affixed on support plate by thermal paste.
Fig. 5 is chip package described in the embodiment of the present invention in the cross-sectional view on support plate.
Fig. 6 is the cross-sectional view of the intermediate products after the grinding of the second encapsulated layer described in the embodiment of the present invention.
Fig. 7 is the cross-sectional view for the intermediate products that dielectric layer described in the embodiment of the present invention is affixed on after the second encapsulated layer.
Fig. 8 is the cross-sectional view of the intermediate products after dielectric layer laser boring described in the embodiment of the present invention.
Fig. 9 is the cross-sectional view of intermediate products of the titanium coating magnetron sputtering after dielectric layer described in the embodiment of the present invention.
Figure 10 is the section view of intermediate products of the copper metal layer magnetron sputtering after titanium coating described in the embodiment of the present invention
Figure.
Figure 11 is the cross-sectional view for the intermediate products that light-sensitive surface described in the embodiment of the present invention is affixed on after seed layer.
Figure 12 is the cross-sectional view of the intermediate products after light-sensitive surface exposure development described in the embodiment of the present invention.
Figure 13 is the cross-sectional view of treated the intermediate products of graphic plating described in the embodiment of the present invention.
Figure 14 is the cross-sectional view of the intermediate products after the remaining light-sensitive surface of removal described in the embodiment of the present invention.
Figure 15 is the cross-sectional view of the intermediate products after the etching of seed layer described in the embodiment of the present invention.
Figure 16 is the cross-sectional view of the product after coating photosensitive-ink and implanted metal ball described in the embodiment of the present invention.
In figure:
1, support plate；11, the first encapsulated layer；12, heat conducting frame；
2, thermal paste；
3, chip；
4, the second encapsulated layer；
5, transport layer；51, dielectric layer；52, titanium coating；53, copper metal layer；
6, wiring layer again；
7, solder mask；
8, metal coupling；
9, light-sensitive surface.
Specific embodiment
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.
Wherein, the drawings are for illustrative purposes only and are merely schematic diagrams, rather than pictorial diagram, should not be understood as to this
The limitation of patent；Embodiment in order to better illustrate the present invention, the certain components of attached drawing have omission, zoom in or out, not
Represent the size of actual product；It will be understood by those skilled in the art that certain known features and its explanation may be omitted and be in attached drawing
It is understood that.
The same or similar label correspond to the same or similar components in the attached drawing of the embodiment of the present invention；It is retouched in of the invention
In stating, it is to be understood that closed if there is the orientation of the instructions such as term " on ", "lower", "left", "right", "inner", "outside" or position
System is merely for convenience of description of the present invention and simplification of the description to be based on the orientation or positional relationship shown in the drawings, rather than indicates
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore retouch in attached drawing
The term for stating positional relationship only for illustration, should not be understood as the limitation to this patent, for the common skill of this field
For art personnel, the concrete meaning of above-mentioned term can be understood as the case may be.
In the description of the present invention unless specifically defined or limited otherwise, if there are the indicate indicators such as term " connection "
Between connection relationship, which shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or at
One；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection of two components interiors or the interaction relationship of two components.For those of ordinary skill in the art and
Speech, can understand the concrete meaning of above-mentioned term in the present invention with concrete condition.
Unless specific instructions, used in the preparation method of the plate grade fan-out packaging structure with high-cooling property of the invention
Various raw materials it is commercially available buy, or be prepared according to the conventional method of the art.
As shown in figure 16, the embodiment of the present invention provides a kind of plate grade fan-out packaging structure with high-cooling property, comprising:
Support plate 1, the heat conducting frame that the support plate 1 encapsulated layer 11 and be packaged in first encapsulated layer 11 including first
12, first encapsulated layer 11 has first side and second side, one side of the heat conducting frame 12 along its thickness direction
The first side of neighbouring first encapsulated layer 11；
Thermal paste 2, the thermal paste 2 are affixed on the first side；
Chip 3, the chip 3 are affixed in the thermal paste 2, and the front of the chip 3 is directed away from the support plate 1
Side；
Encapsulating structure, the encapsulating structure is located in the thermal paste 2, and the chip 3 is packaged in the encapsulating structure
It is interior.
In the present embodiment, unless otherwise specified, term " covering " refers both to wrap some component non-contact with other component
Outer surface.For example, thermal paste 2 covers heat conducting frame 12, refer to that thermal paste 2 wraps heat conducting frame 12 and the first encapsulated layer
11 non-contacting outer surfaces.
Wherein, the heat conducting frame 12 is along the one side of its thickness direction adjacent to the first side of first encapsulated layer 11
Face refers to that heat conducting frame 12 exposes to the first side of the first encapsulated layer 11 along the one side of its thickness direction, can also be located at
The inside of first encapsulated layer 11, i.e. heat conducting frame 12 and 2 non-direct contact of thermal paste.
Wherein, the front of chip 3 refers to the one side equipped with I/O interface.
Heat conducting frame 12 is packaged in formation support plate 1 in the first encapsulated layer 11 by the present embodiment, and chip 3 is passed through thermal paste 2
It is attached on support plate 1 and is packaged, support plate 1 plays a supporting role to the encapsulation of chip 3.After chip 3 is encapsulated and is cut, chip
The heat generated when 3 work is transferred on heat conducting frame 12 by thermal paste 2, is led the heat of chip 3 by heat conducting frame 12
Out, the radiating efficiency of chip 3 is improved.In the present embodiment, without tearing bonding removal support plate 1 open in 3 encapsulation process of chip, and it is thermally conductive
The characteristic that the thermal expansion coefficient of the high intensity of frame 12 and the first encapsulated layer 11 and the second encapsulated layer 4 matches can be effectively improved
The warpage issues that chip 3 occurs when encapsulating, the radiator structure as chip 3, the high efficiency for both having realized chip 3 dissipate again after cutting
Heat, and realize the recycling of support plate 1.
Optionally, the heat conducting frame 12 is using one of Cu, Al, steel or Graphene (graphene) material
It is made, there is good heat dissipation effect and high intensity.
In the present embodiment, the material of heat conducting frame 12 includes but is not limited to Cu, Al, steel or Graphene, Ren Heqi
There is high-intensitive, high-cooling property material to be applicable in for he.
The heat conducting frame 12 is made of several subframes, and the subframe is groined type, diamond shape, rice font or field word
Any one shape in shape.Wherein, subframe includes but is not limited to groined type, diamond shape, rice font or matrix pattern structure, such as
Shown in Fig. 2, heat conducting frame 12 is made of four rice font frames, can be improved heat conducting frame 12 intensity and with the first encapsulated layer
Connective stability between 11.
Preferably, the support plate 1 with a thickness of 0.5~0.8mm, specific thickness can be designed according to actual conditions, can be with
It passes the heat of heat conducting frame 12 quickly by the first encapsulated layer 11, while guaranteeing the stability of chip-packaging structure.
Further, the encapsulating structure includes:
Second encapsulated layer 4, the chip 3 are packaged in second encapsulated layer 4；
Transport layer 5 and again wiring layer 6, the side positioned at second encapsulated layer 4 far from the support plate 1, the transport layer 5
Side and the I/O interface of the chip be electrically connected, the other side is electrically connected by copper post and the wiring layer again 6, described
Wiring layer 6 has pad area and non-pad area again；
Solder mask 7, the solder mask 7 is located at side of second encapsulated layer 4 far from the support plate 1 and covering is described again
The non-pad area and the transport layer 5 of wiring layer 6 expose to the region of the wiring layer 6 again；
The pad area of metal coupling 8, the metal coupling 8 and the wiring layer again 6 welds.
Wherein, the thickness of the chip 3 be less than second encapsulated layer 4 thickness, subsequently through laser drill or its
His mode can make the I/O interface of chip 3 exposed.
In the present embodiment, chip 3 is fixed on support plate 1 by the encapsulation of the second encapsulated layer 4, then passes through transport layer 5 and again cloth
The I/O interface of chip 3 is electrically drawn and is welded with metal coupling 8 by line layer 6.
In the present embodiment, the first encapsulated layer 11 can be identical with the material of the second encapsulated layer 4, the thermal expansion system of the two
Number exact matching, to be further reduced warpage issues.
In the present embodiment, the solder mask 7 is photosensitive printing ink layer.Using photosensitive-ink as solder mask 7, can both play
Transport layer 5 and the effect of wiring layer 6 again are protected, and work can be simplified by exposure, development, etching removal Some seeds layer 5
Skill.
Optionally, metal coupling 8 is tin solder, silver solder or gold-tin eutectic solder, and the metal coupling 8 of the present embodiment is
Metal spherical structure, metal ball bonding are implanted in pad area, to realize that again the electrical of wiring layer 6 is drawn.
Further, the transport layer 5 includes that the dielectric layer 51 that is affixed on second encapsulated layer 4 and being attached to is given an account of
Seed layer in electric layer 51, the dielectric layer 51 have the through-hole for keeping the I/O interface of the chip 3 exposed along its thickness direction,
The seed layer is extended in the through-hole and is electrically connected with the I/O interface.Dielectric layer 51 is ABF (Ajinomoto
Build-up Film) or PP (Polypropylene, polypropylene) material, it is attached on the second encapsulated layer 4, plays the work of insulation
With.Laser drill mode can be used in the present embodiment in the next steps, forms the through-hole for making I/O interface exposed, and in through-hole
Face copper facing forms copper post, so that the electric signal of chip 3 be made to be connected to wiring layer 6 again through copper post.
Further, the seed layer includes being located at titanium coating of second encapsulated layer 4 far from 1 side of support plate
52 and the copper metal layer 53 on the titanium coating 52.Wherein, the adhesive force of titanium coating 52 is high, conductivity is excellent and thick
The stabilization of copper metal layer 53 uniformly, can be attached on the second encapsulated layer 4 by degree by titanium coating 52.
Certainly, the seed layer of the present embodiment is not limited to double-layer structure (titanium coating 52, copper metal layer 53), or single
Layer or two layers or more of structure.The material of seed layer is also not necessarily limited to two kinds of single metal material stacked combinations, or
A kind of single metal material or alloy material can be realized again wiring layer stabilization and are attached on encapsulating structure, specifically not
It repeats again.
Optionally, the material of the first encapsulated layer 11 and the second encapsulated layer 4 includes polyimides, silica gel and EMC (Epoxy
Any one of Molding Compound, epoxy-plastic packaging material), the preferred EMC of the present embodiment, i.e., the described encapsulated layer 4 is asphalt mixtures modified by epoxy resin
Rouge encapsulated layer can be such that the stabilization of chip 3 is fitted on support plate 1, play the role of protecting chip 3.
As shown in Fig. 1 to 16, the embodiment of the present invention also provides a kind of plate grade fan-out packaging structure with high-cooling property
Preparation method, comprising the following steps:
S10, heat conducting frame 12 is provided, processing is packaged to the heat conducting frame 12 using plastic packaging material, makes plastic packaging material shape
At the first encapsulated layer 11, and make the one side of the heat conducting frame 12 adjacent to the first side of first encapsulated layer 11, is made
Support plate 1, as depicted in figs. 1 and 2；
S20, thermal paste 2 and several chips 3 are provided, the front of the chip 3 are made to face away from the side of the support plate 1,
The chip 3 is affixed on the support plate 1 adjacent to the side of the heat conducting frame 12, such as Fig. 3 and Fig. 4 institute by the thermal paste 2
Show,；
S30, it is packaged processing to the chip 3, and the I/O interface of the chip 3 is drawn with metal coupling 8 electrically
Connection, as shown in Fig. 5 to 16.
In step S10, after plastic packaging material is packaged and solidifies to heat conducting frame 12, the first encapsulated layer 11 is formed, such as Fig. 5
It is shown, it is also necessary to grinding reduction processing be carried out along at least one side of its thickness direction to the first encapsulated layer 11, make its surface
It keeps smooth and makes side (Fig. 6) of the side of heat conducting frame 12 adjacent to the first encapsulated layer 11, in order to paste thermal paste 2.Heat dissipation
It can be radiated by plastic packaging material between glue 2 and heat conducting frame 12, can also directly contact heat dissipation.
The present embodiment is packaged obtained support plate 1 to heat conducting frame 12 using plastic packaging material, and chip 3 is passed through thermal paste 2
It is affixed on support plate 1, heat conducting frame 12 has high intensity, can encapsulate and play a supporting role to chip 3, and due to heat conducting frame 12
Plastic packaging material it is consistent with the plastic packaging material of chip 3, the thermal expansion coefficient of the two exact matching, therefore the production of warpage can be effectively reduced
Raw, support plate 1 and the radiator structure as chip, not only realize high efficiency heat radiation, but also realize the recycling of support plate 1 after cutting.
Further, in this embodiment step S30 specifically include:
S31, processing is packaged to the chip 3 using plastic packaging material, the plastic packaging material is made to form the second encapsulated layer 4；Specifically
Ground is carried out grinding thinned (grinding) processing by the second encapsulated layer 4, the surface of the second encapsulated layer 4 can be made to keep smooth,
In the present embodiment, the thickness after the grinding of the second encapsulated layer 4 is greater than the thickness of chip 3；
S32, transport layer 5 is made on second encapsulated layer 4, make the I/O interface of the chip 3 and the transport layer 5
It is electrically connected；
S33, wiring layer 6 again are made in the transport layer 5；
S34, solder mask 7 is made far from the side of the support plate 1 in second encapsulated layer 4, covers the solder mask 7
The non-pad area of the wiring layer again 6 and the pad area of the wiring layer 6 again is made to expose to the solder mask 7；
S35, metal coupling 8 is provided, the metal coupling 8 is implanted into the pad area.
In the present embodiment, plastic packaging material can be liquid, solid-state or sheet.
Further, step S32 is specifically included:
S32a, dielectric layer 51 is provided, the dielectric layer 51 is affixed on second encapsulated layer 4, realize the second encapsulated layer 4
Insulation processing (as shown in Figure 7)；
S32b, laser drill processing (UV laser) is carried out to the dielectric layer 51, makes the dielectric layer 51 along its thickness side
To through-hole (as shown in Figure 8) is formed, so that the I/O interface of the chip 3 is exposed, convenient for the connection of subsequent conditioning circuit；
S32c, seed layer, 51 He of dielectric layer are formed in the dielectric layer 51 and the through-hole by vacuum sputtering
The seed layer forms the transport layer 5.
Specifically, it is heated first in high vacuum state to through intermediate products made from step S32b, on intermediate products
Moisture and pollutant removal after, then there is high adhesion force, excellent conductivity and in homogeneous thickness by magnetron sputtering preparation
Titanium coating 52 (as shown in Figure 9) finally prepares copper metal layer 53 (as shown in Figure 10), the titanium by magnetron sputtering again
Layer 52 and the copper metal 53 form the seed layer.
Further, step S33 is specifically included:
The light-sensitive surface 9 is attached in the transport layer 5 by S33a, offer light-sensitive surface 9 as shown in figure 11；Specifically,
Light-sensitive surface 9 is attached in seed layer；
S33b, pass through exposure, development treatment, being formed on the light-sensitive surface 9 makes the exposed seed layer in described photosensitive
The figure of film 9, as shown in figure 12；
S33c, electroplating processes are carried out to the figure and the through-hole, copper post is formed in the through-hole, in the figure
Wiring layer 6, the wiring layer again 6 are electrically connected by the I/O interface of the copper post and the chip 3 again described in interior formation, such as
Shown in Figure 13；
S33d, the remaining light-sensitive surface 9 of removal, as shown in figure 14.
Wherein, according to actual needs, one layer, two layers, three layers of even more multilayer can will be designed as by wiring layer 6 again.
Further, step S34 is specifically included:
S34a, as shown in figure 15, rear exposed seed layer is removed to the light-sensitive surface 9 and is etched, with removal
The seed layer；
S34b, as shown in figure 16, coat photosensitive-ink on exposed dielectric layer 51 after removing seed layer, formed after solidification
Solder mask 7 makes the solder mask 7 cover the non-pad area of wiring layer 6 again and make outside the pad area of wiring layer 6 again
It is exposed to the solder mask 7.
In this present embodiment, the thermal paste 2 is permanent thermal paste, and ingredient includes graphene, silica gel, silicone grease, first
Base vinyl polysiloxane mixture, methyl hydrogen based polysiloxane mixture, aluminium oxide.
After the pad area implanted metal ball of wiring layer 6 again, that is, the production (Figure 16) of plastic part is completed, by the plastic part
The packaging body for being cut into one single chip realizes the preparation of the plate grade fan-out packaging structure with high-cooling property.
Under hundreds of mm size ranges permanent thermal paste 2 can be arranged in multiple chip backs simultaneously in the present invention
With high-intensitive support plate 1, the warpage issues occurred when chip 3 encapsulates are substantially improved.After chip 3 is encapsulated and is cut, the thermal paste 2
It can be used as radiator structure with high-intensitive support plate 1, not only realized the high efficiency heat radiation of chip 3, but also realize the recycling of support plate 1.
Above embodiments are only used to illustrate method detailed of the invention, and the invention is not limited to above-mentioned method detaileds, i.e.,
Do not mean that the invention must rely on the above detailed methods to implement.Person of ordinary skill in the field should be understood that pair
Any improvement of the invention, the addition of equivalence replacement and auxiliary element to each raw material of product of the present invention, the selection of concrete mode
Deng all of which fall within the scope of protection and disclosure of the present invention.
Claims (10)
1. a kind of plate grade fan-out packaging structure with high-cooling property characterized by comprising
Support plate, the support plate include the first encapsulated layer and the heat conducting frame that is packaged in first encapsulated layer, first envelope
Fill layer have first side and second side, the heat conducting frame along its thickness direction one side adjacent to first encapsulated layer
First side；
Thermal paste, the thermal paste are affixed on the first side；
Chip, the chip are affixed in the thermal paste, and the front of the chip is directed away from the side of the support plate；
Encapsulating structure, the encapsulating structure is located in the thermal paste, and the chip package is in the encapsulating structure.
2. the plate grade fan-out packaging structure according to claim 1 with high-cooling property, which is characterized in that the thermally conductive frame
Frame is made of one of Cu, Al, steel or Graphene material.
3. the plate grade fan-out packaging structure according to claim 1 with high-cooling property, which is characterized in that the encapsulation knot
Structure includes:
Second encapsulated layer, the chip package is in second encapsulated layer；
Transport layer and again wiring layer, positioned at the side of second encapsulated layer far from the support plate, the side of the transport layer with
The I/O interface of the chip is electrically connected, and the other side is electrically connected by copper post and the wiring layer again, the tool of wiring layer again
There are pad area and non-pad area；
Solder mask, the solder mask are located at the side of second encapsulated layer far from the support plate and cover the wiring layer again
Non- pad area and the transport layer expose to the region of the wiring layer again；
The pad area of metal coupling, the metal coupling and the wiring layer welds.
4. the plate grade fan-out packaging structure according to claim 3 with high-cooling property, which is characterized in that the transport layer
Including the dielectric layer being affixed on second encapsulated layer and the seed layer being attached on the dielectric layer, the dielectric layer is along its thickness
Degree direction has the through-hole for keeping the I/O interface of the chip exposed, and the seed layer is extended in the through-hole and connect with the I/O
Mouth is electrically connected.
5. a kind of preparation method of the plate grade fan-out packaging structure with high-cooling property, which comprises the following steps:
S10, heat conducting frame is provided, processing is packaged to the heat conducting frame using plastic packaging material and forms the first encapsulated layer, and is made
Support plate is made adjacent to the first side of first encapsulated layer in the one side of the heat conducting frame；
S20, thermal paste and several chips are provided, so that the front of the chip is faced away from the side of the support plate, by described
The chip is affixed on the support plate adjacent to the side of the heat conducting frame by thermal paste；
S30, it is packaged processing to the chip, and the I/O interface of the chip is drawn and is electrically connected with metal coupling.
6. the preparation method of the plate grade fan-out packaging structure according to claim 5 with high-cooling property, which is characterized in that
Step S30 is specifically included:
S31, processing the second encapsulated layer of formation is packaged to the chip using plastic packaging material；
S32, transport layer is made on second encapsulated layer, is electrically connected the I/O interface of the chip and the transport layer；
S33, wiring layer again is made in the transport layer；
S34, solder mask is made far from the side of the support plate in second encapsulated layer, the solder mask is made to cover the wiring
The non-pad area of layer and the pad area of the wiring layer again is made to expose to the solder mask；
S35, metal coupling is provided, the metal coupling is implanted into the pad area.
7. the preparation method of the plate grade fan-out packaging structure according to claim 6 with high-cooling property, which is characterized in that
Step S32 is specifically included:
S32a, dielectric layer is provided, the dielectric layer is affixed on second encapsulated layer；
S32b, laser drill processing is carried out to the position of the I/O interface of chip described in the dielectric layer face, makes the dielectric layer
Through-hole is formed along its thickness direction；
S32c, seed layer, the dielectric layer and the seed are formed in the dielectric layer and the through-hole by vacuum sputtering
Layer forms the transport layer.
8. the preparation method of the plate grade fan-out packaging structure according to claim 7 with high-cooling property, which is characterized in that
Step S33 is specifically included:
S33a, light-sensitive surface is provided, the light-sensitive surface is attached in the transport layer；
S33b, pass through exposure, development treatment, being formed on the light-sensitive surface makes the exposed seed layer in the figure of the light-sensitive surface
Shape；
S33c, electroplating processes are carried out to the figure and the through-hole, forms copper post in the through-hole, the shape in the figure
At the wiring layer again, the wiring layer again is electrically connected by the I/O interface of the copper post and the chip；
S33d, the remaining light-sensitive surface of removal.
9. the preparation method of the plate grade fan-out packaging structure according to claim 8 with high-cooling property, which is characterized in that
Step S34 is specifically included:
S34a, it is removed rear exposed seed layer to the light-sensitive surface is etched, to remove the seed layer；
Photosensitive-ink is coated on S34b, dielectric layer exposed after removing seed layer, solder mask is formed after solidification, makes the welding resistance
Layer covers the non-pad area of wiring layer again and the pad area of the wiring layer again is made to expose to the solder mask.
10. the preparation method of the plate grade fan-out packaging structure according to claim 5 with high-cooling property, feature exist
In the ingredient of the thermal paste includes graphene, silica gel, silicone grease, methylvinyl-polysiloxane mixture, the poly- silicon of methyl hydrogen-based
Oxygen alkane mixture, aluminium oxide.
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| CN111403362A (en) * | 2020-03-27 | 2020-07-10 | Tcl华星光电技术有限公司 | Chip on film packaging method, packaging structure, display device and electronic equipment |
| CN113299564A (en) * | 2021-05-21 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | Packaging structure of board-level fan-out flexible packaging substrate and preparation method thereof |
| CN113394120A (en) * | 2021-06-03 | 2021-09-14 | 广东工业大学 | Fan-out type packaging structure based on laser forming and preparation method thereof |
| CN114203664A (en) * | 2021-12-06 | 2022-03-18 | 气派科技股份有限公司 | High-reliability packaging structure and preparation method |
| WO2023246932A1 (en) * | 2022-06-24 | 2023-12-28 | 惠州市聚飞光电有限公司 | Led lamp panel |
| US12027470B2 (en) | 2021-10-18 | 2024-07-02 | Industrial Technology Research Institute | Package carrier having a stiffener between solder bumps |
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