CN110515437B - High-temperature protection method and device for FPGA accelerator card - Google Patents
High-temperature protection method and device for FPGA accelerator card Download PDFInfo
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Abstract
The invention discloses a high-temperature protection method and device for an FPGA accelerator card. Through the scheme, if all read temperatures are greater than the preset threshold value, the FPGA is forced to stop working, when the temperature of the FPGA is reduced to a normal level, the FPGA is enabled to recover normal working, through the protection mechanism, a user can be reminded to check whether the FPGA is correctly installed and whether a server machine room has a problem or not, and the purpose of avoiding burning the FPGA is achieved.
Description
Technical Field
The invention relates to the technical field of cloud computing, in particular to a high-temperature protection method and device for an FPGA accelerator card.
Background
With the development of technology, the demand of people on computing power far exceeds the capability of a traditional CPU processor, heterogeneous computing is considered as a key technology for solving the computing gully at the present stage, and an FPGA accelerator card is used as an important component of heterogeneous acceleration, starts to be widely used in the field of data centers, and plays an important role in the fields of big data processing, AI, network function acceleration and the like. With the faster and faster computing speed of the chip, the power consumption is larger and larger, and more heat is generated when the chip works. If the junction temperature of the chip is to be maintained within a normal range, some method is needed to quickly dissipate the heat generated by the chip to the environment.
In the prior art, a general server generally has 4 powerful CPU cooling fans, the heterogeneous FPGA accelerator cards are connected to the server through a PCIE interface slot, and the cooling fans of the server can be used for cooling, so that most of the heterogeneous FPGA accelerator cards adopt passive cooling, and a small number of board cards are designed with fans for active cooling.
However, when the passive radiating heterogeneous FPGA accelerator card is installed and connected to a server, attention must be paid to keeping the wind direction of a fan of the server consistent with the wind guiding direction of a radiating fin of the accelerator card, if a user is not used properly, the installation direction is inconsistent, the heat of the FPGA accelerator card cannot be radiated, the temperature of a chip rises continuously, and finally the board card is burnt. In addition, if the air conditioner of server computer lab appears unusually, no matter be the accelerator card of initiative heat dissipation or passive heat dissipation all face the chip temperature and constantly rise and finally lead to the risk that the integrated circuit board chip burns out.
Disclosure of Invention
In view of this, the invention provides a high-temperature protection method and device for an FPGA accelerator card, which can remind a user to check whether an FPGA is correctly installed and whether a server room has a problem, and the like, so as to achieve the purpose of avoiding burning of the FPGA.
In order to achieve the above object, the following solutions are proposed:
the invention discloses a high-temperature protection method of an FPGA accelerator card, which is applied to the FPGA accelerator card comprising a digital temperature sensor, a complex programmable logic device CPLD and a field programmable gate array FPGA, and comprises the following steps:
the digital temperature sensor acquires the temperature of the FPGA acceleration board card and stores the temperature;
the CPLD initiates a reading request to the digital temperature sensor, reads the temperature of the FPGA acceleration board card acquired by the digital temperature sensor, and judges whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times;
if all the read temperatures are greater than a preset threshold value, configuring a rechfig pin of the FPGA as a low level, and stopping the FPGA from working;
and if all the read temperatures are within the normal working temperature range, configuring the reconfig pin of the FPGA as a high level.
Preferably, the method further comprises the following steps:
and if any temperature in all the read temperatures is smaller than a preset threshold value, the digital temperature sensor acquires the temperature of the FPGA acceleration board again.
Preferably, after configuring the reconfig pin of the FPGA to be at a high level, the method further includes:
and after the level state of the reconfig pin of the FPGA is kept for a preset time, configuring the reconfig pin of the FPGA to be in a high-impedance state.
Preferably, the digital temperature sensor acquires the temperature of the FPGA acceleration board card, and stores the temperature, including:
the digital temperature sensor acquires an analog voltage signal on a thermistor of the FPGA;
the digital temperature sensor converts the analog voltage signal into an original digital temperature signal;
the digital temperature sensor stores the raw digital temperature signal.
Preferably, the step of initiating a reading request to the digital temperature sensor by the CPLD, reading the temperature of the FPGA acceleration board acquired by the digital temperature sensor, and when the number of times of reading the temperature reaches a preset number, judging whether all the read temperatures are greater than a preset threshold value includes:
the CPLD initiates a reading request based on an I2C Master module, and reads an original digital temperature signal acquired by the FPGA acceleration board card by the digital temperature sensor;
the CPLD converts the original digital temperature signal to obtain the temperature of the FPGA acceleration board card;
and when the times of reading the temperatures reach the preset times, judging whether all the read temperatures are greater than a preset threshold value.
The second aspect of the invention discloses a high-temperature protection device for an FPGA accelerator card, which comprises:
the digital temperature sensor is used for acquiring the temperature of the FPGA acceleration board card and storing the temperature;
the CPLD is used for initiating a reading request to the digital temperature sensor, reading the temperature of the FPGA acceleration board card collected by the digital temperature sensor, and judging whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times; if all the read temperatures are greater than a preset threshold value, configuring a rechfig pin of the FPGA as a low level, and stopping the FPGA from working; and if all the read temperatures are within the normal working temperature range, configuring the reconfig pin of the FPGA as a high level.
Preferably, the digital temperature sensor is further specifically configured to:
and if any temperature in all the read temperatures is smaller than a preset threshold value, re-acquiring the temperature of the FPGA acceleration board card.
Preferably, the FPGA after configuring the reconfig pin of the FPGA to a high level is further specifically configured to:
and after the level state of the reconfig pin is kept for a preset time, configuring the reconfig pin of the FPGA to be in a high-impedance state.
Preferably, the digital temperature sensor is used for acquiring the temperature of the FPGA acceleration board card and storing the temperature, and is specifically used for:
and collecting an analog voltage signal on a thermistor of the FPGA, converting the analog voltage signal into an original digital temperature signal, and storing the original digital temperature signal.
Preferably, a reading request is initiated to the digital temperature sensor, the digital temperature sensor is read to acquire the temperature of the FPGA acceleration board, and when the number of times of reading the temperature reaches a preset number, the CPLD which determines whether all the read temperatures are greater than a preset threshold is specifically used for:
initiating a reading request based on an I2C Master module, reading an original digital temperature signal acquired by the digital temperature sensor through the FPGA acceleration board card, converting the original digital temperature signal to obtain the temperature of the FPGA acceleration board card, and judging whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times.
According to the technical scheme, the digital temperature sensor acquires the temperature of the FPGA acceleration board card, the CPLD reads the temperature of the FPGA acquired by the digital temperature sensor, when the temperature reading times reach the preset times, whether all the read temperatures are greater than the preset threshold value or not is judged, if all the read temperatures are greater than the preset threshold value, the FPGA stops working, and if all the read temperatures are within the normal working temperature range, the rechonfig pin of the FPGA is configured to be at a high level. Through the scheme, if all read temperatures are greater than the preset threshold value, the FPGA is forced to stop working, when the temperature of the FPGA is reduced to a normal level, the FPGA is enabled to recover normal working, through the protection mechanism, a user can be reminded to check whether the FPGA is correctly installed and whether a server machine room has a problem or not, and the purpose of avoiding burning the FPGA is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is an architecture diagram of a high temperature protection device of an FPGA accelerator card according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a high-temperature protection method for an FPGA accelerator card according to an embodiment of the present invention;
fig. 3 is a schematic flow diagram illustrating a process of acquiring the temperature of the FPGA acceleration board and storing the temperature by the digital temperature sensor disclosed in the embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a CPLD reading digital temperature sensor acquiring the temperature of an FPGA acceleration board, and determining whether the temperature is greater than a preset threshold value when the temperature reading times reach preset times;
fig. 5 is a schematic structural diagram of a high-temperature protection device of an FPGA accelerator card according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, a passive heat dissipation heterogeneous accelerator card (field programmable Gate Array, FPGA) is adopted, when the accelerator card is installed and connected to a server, attention must be paid to the fact that the wind direction of a fan of the server is consistent with the wind guiding direction of a heat sink of the accelerator card, if a user is not properly used, the installation direction is inconsistent, the heat of the FPGA accelerator card cannot be dissipated, the temperature of a chip continuously rises, and finally a board card is burnt. In addition, if the air conditioner of server computer lab appears unusually, no matter be the accelerator card of initiative heat dissipation or passive heat dissipation all face the chip temperature and constantly rise and finally lead to the risk that the integrated circuit board chip burns out.
Therefore, the invention discloses a high-temperature protection method and device for an FPGA accelerator card, which can remind a user to check whether the FPGA is installed correctly, whether a server room has problems or not and the like, and achieve the purpose of avoiding burning of the FPGA.
As shown in fig. 1, an architecture diagram of a high temperature protection device of an FPGA accelerator card disclosed in an embodiment of the present invention is shown, where the high temperature protection device of the FPGA accelerator card mainly includes:
a digital temperature sensor 11, a complex programmable logic device CPLD12 and a field programmable gate array FPGA 13.
The temperature sensor 11 is connected with the complex programmable logic device CPLD12 through an I2C bus, and the complex programmable logic device CPLD12 is connected with the field programmable gate array FPGA13 through a reconfig pin.
It should be noted that I2C is a bus protocol, and is controlled by Slave, and Master controls the Slave.
The complex programmable logic device CPLD12 is a master device, and the digital temperature sensor 11 is a slave device.
And the digital temperature sensor 11 is used for acquiring the temperature of the FPGA acceleration board card.
It should be noted that the digital temperature sensor 11 supports the I2C bus protocol, and is used as a Slave of the I2C bus.
The complex programmable logic device CPLD12 includes an I2C Master module 14, a temperature calculation module 15 and a sampling decision module 16.
And the I2C Master module 14 is used for reading the temperature of the FPGA acceleration board card acquired by the digital temperature sensor 11.
And the temperature calculation module 15 is used for converting the temperature of the FPGA acceleration board card into effective environment temperature data through calculation.
The sampling decision module 16 is configured to perform sampling decision on the effective ambient temperature, and control whether the field programmable gate array FPGA13 works.
And the field programmable gate array FPGA13 is used for processing data sent by the upper computer and realizing algorithms such as AI, network acceleration or image processing and the like.
It should be noted that the field programmable gate array FPGA13 is a main operation unit of the FPGA accelerator card.
The working flow of the architecture of the high-temperature protection device of the FPGA accelerator card is as follows:
step 1, the digital temperature sensor 11 acquires an analog voltage signal on a thermistor of the FPGA acceleration board, and gives the analog-digital converter ADC the analog signal to convert the analog signal into an original digital temperature signal, and the original digital temperature signal is stored in an internal register of the digital temperature sensor 11.
Step 2, an I2C Master module in the complex programmable logic device CPLD12 initiates a reading request to the digital temperature sensor 11, and reads the original digital temperature signal acquired by the digital temperature sensor 11.
And Step 3, calculating the complex programmable logic device CPLD12 according to circuit device parameters such as thermistor values and the like and special public signs, and converting the original digital temperature signals into effective environment temperature.
Step 4, the sampling decision module 16 samples the effective ambient temperature for a plurality of times.
And Step 5, judging whether the temperature sampled for multiple times is greater than a preset high-temperature threshold value or not by the complex programmable logic device CPLD12, if so, configuring a rechfig pin of the field programmable gate array FPGA13 to be a low level to stop the field programmable gate array FPGA13, and if one of the temperature sampled for multiple times is less than the preset high-temperature threshold value, resampling.
And Step 6, the complex programmable logic device CPLD12 judges that the temperatures sampled for multiple times are all reduced to be within the normal working temperature range, the rechfig pin of the field programmable gate array FPGA13 is configured to be high level, and if one of the temperatures sampled for multiple times is higher than the normal temperature threshold value, the sampling is carried out again.
Step 7, the complex programmable logic device CPLD12 configures the reconfig pin of the field programmable gate array FPGA13 to a high impedance state, so that the field programmable gate array FPGA13 starts to work after being restarted.
In the embodiment of the invention, the temperature of the FPGA acceleration board card is acquired through the digital temperature sensor, the CPLD reads the temperature of the FPGA acquired by the digital temperature sensor, when the temperature reading times reach the preset times, whether all the read temperatures are greater than the preset threshold value or not is judged, if all the read temperatures are greater than the preset threshold value, the FPGA stops working, and if all the read temperatures are within the normal working temperature range, the rechfig pin of the FPGA is configured to be at a high level. Through the scheme, if all read temperatures are greater than the preset threshold value, the FPGA is forced to stop working, when the temperature of the FPGA is reduced to a normal level, the FPGA is enabled to recover normal working, through the protection mechanism, a user can be reminded to check whether the FPGA is correctly installed and whether a server machine room has a problem or not, and the purpose of avoiding burning the FPGA is achieved.
As shown in fig. 2, a schematic flow chart of a high-temperature protection method for an FPGA accelerator card disclosed in the embodiment of the present invention specifically includes the following steps:
step S201: the digital temperature sensor acquires the temperature of the FPGA acceleration board card and stores the temperature.
In the process of implementing step S201 specifically, the digital temperature sensor acquires an analog voltage signal on the thermistor of the FPGA acceleration board, converts the analog voltage signal into a temperature of the FPGA acceleration board through the analog-to-digital converter, and stores the temperature of the FPGA acceleration board into the content register of the digital temperature sensor.
It should be noted that the type of the digital temperature sensor may be a MAX1619 digital temperature sensor, a MAX31826 digital temperature sensor, or a MAX6695 digital temperature sensor, and the specific digital temperature sensor is selected by a skilled person according to the actual situation, which is not limited in the present invention.
The FPGA is a product developed on the basis of programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The raw data collected by the digital temperature sensor, such as "0 x0 a", is generally not directly usable, and needs to be calculated by a formula to obtain temperature data.
Step S202: the CPLD initiates a reading request to the digital temperature sensor, reads the temperature of the FPGA acceleration board acquired by the digital temperature sensor, judges whether all the read temperatures are greater than a preset threshold value when the times of reading the temperature reach the preset times, executes step S203 if all the read temperatures are greater than the preset threshold value, and executes step S204 if all the read temperatures are within a normal working temperature range.
In the process of specifically implementing the step S202, the I2C Master module in the CPLD initiates a read request to the digital temperature sensor, and reads the temperature of the FPGA acceleration board acquired by the digital temperature sensor.
It should be noted that the preset number may be 10 times or 12 times, and the specific preset number is set by a technician according to actual situations.
The preset threshold may be 40 degrees celsius or 50 degrees celsius, and the specific setting of the preset threshold is set by a technician according to actual conditions.
Step S203: and configuring the reconfig pin of the FPGA to be at a low level, so that the FPGA stops working.
In the process of implementing step S203 specifically, the pin name of the CPLD end connected to the reconfig of the FPGA end is pin _ a, the reconfig pin of the FPGA is configured to be at low level, and the assign pin _ a is 1' b0 at the CPLD end.
It should be noted that the low level (Vil) refers to the maximum input low level allowed when the input of the logic gate is guaranteed to be low, and when the input level is lower than the low level (Vil), the input level is considered to be low.
Step S204: and configuring a reconfig pin of the FPGA to be high level.
In the process of implementing step S204 specifically, the pin name of the CPLD end connected to the reconfig of the FPGA end is pin _ a, the reconfig pin of the FPGA is configured to be at high level, and the assign pin _ a is 1' b1 at the CPLD end.
It should be noted that high level refers to high voltage as opposed to low level, which is a term of electrical engineering. Among the logic levels, the minimum input high level allowed when the input of the logic gate is a high level is guaranteed, and when the input level is higher than the input high voltage (Vih), the input level is considered as a high level.
In the embodiment of the invention, the temperature of the FPGA acceleration board card is acquired through the digital temperature sensor, the CPLD reads the temperature of the FPGA acquired by the digital temperature sensor, when the temperature reading times reach the preset times, whether all the read temperatures are greater than the preset threshold value or not is judged, if all the read temperatures are greater than the preset threshold value, the FPGA stops working, and if all the read temperatures are within the normal working temperature range, the reconfig pin of the FPGA is configured to be at a high level. Through the scheme, if all read temperatures are greater than the preset threshold value, the FPGA is forced to stop working, when the temperature of the FPGA is reduced to a normal level, the FPGA is enabled to recover normal working, through the protection mechanism, a user can be reminded to check whether the FPGA is correctly installed and whether a server machine room has a problem or not, and the purpose of avoiding burning the FPGA is achieved.
In an application scenario of the embodiment of the invention, if any temperature among all the read temperatures is smaller than a preset threshold, the digital temperature sensor acquires the temperature of the FPGA acceleration board again.
It should be noted that the preset threshold is set by a technician according to actual situations, and the present invention is not limited in particular.
In the application scenario of the embodiment of the invention, if any temperature in all the read temperatures is smaller than the preset threshold, the purpose that the digital temperature sensor acquires the temperature of the FPGA acceleration board card again is achieved.
In another application scenario of the embodiment of the present invention, after the reconfig pin of the FPGA is configured to be at a high level and the level state of the reconfig pin of the FPGA is kept for a preset time, the reconfig pin of the FPGA is configured to be at a high impedance state.
In another application scenario for specifically implementing the embodiment of the present invention, after configuring the reconfig pin of the FPGA to be in a high-impedance state, the FPGA is reconfigured, that is, the FPGA is restarted, in a process of reconfiguring the FPGA, the reconfig pin of the FPGA is pulled up for 10 seconds, and then released, so that the reconfig pin of the FPGA is loaded with a program from a memory of the FPGA acceleration board, where the program is an operation program of the FPGA.
It should be noted that the pin name of the CPLD end connected to the reconfig of the FPGA end is pin _ a, the reconfig pin of the FPGA is configured to be in a high impedance state, and the ssignpin _ a is 1' bz at the CPLD end.
The time for pulling the reconfig of the FPGA up may be 10 seconds or 12 seconds, and the setting is performed according to specific situations, which is not specifically limited in the present invention.
The high-resistance state refers to an output state of the circuit, which is neither high level nor low level, and has no influence on a next stage circuit if the high-resistance state is input into the next stage circuit again, and the high-resistance state is not input into the next stage circuit.
In an application scenario of the embodiment of the present invention, after the reconfig pin of the FPGA is configured to be at a high level and the level state of the reconfig pin of the FPGA is maintained for a preset time, the reconfig pin of the FPGA is configured to be at a high impedance state, so as to restart and start working of the FPGA.
In the process of step S201, a process in which the digital temperature sensor acquires the temperature of the FPGA acceleration board and stores the temperature is involved, as shown in fig. 3, the method specifically includes the following steps:
step S301: and the digital temperature sensor acquires an analog voltage signal on the thermistor of the FPGA.
It should be noted that the analog voltage signal is a voltage signal that continuously changes with time, such as a sine wave, a square wave, and the like.
Step S302: the digital temperature sensor converts the analog voltage signal to a raw digital temperature signal.
It should be noted that the analog voltage signal collected by the digital temperature sensor generally cannot be directly used, and an analog-to-digital converter is required to convert the analog voltage signal into an original digital temperature signal.
Step S303: the digital temperature sensor stores the raw digital temperature signal.
Through the steps S301 to S303, the digital temperature sensor acquires an analog voltage signal on the thermistor of the FPGA, the digital temperature sensor converts the analog voltage signal into an original digital temperature signal, and the digital temperature sensor stores the original digital temperature signal.
In the embodiment of the invention, the digital temperature sensor acquires an analog voltage signal on the thermistor of the FPGA, the digital temperature sensor converts the analog voltage signal into an original digital temperature signal, and the digital temperature sensor stores the original digital temperature signal, so that the aim of acquiring the temperature of the FPGA acceleration board card is fulfilled.
In the step S202, a process is involved in which the CPLD issues a read request to the digital temperature sensor, the digital temperature sensor reads the temperature of the FPGA acceleration board, and when the number of times of reading the temperature reaches a preset number, it is determined whether all the read temperatures are greater than a preset threshold, as shown in fig. 4, the method specifically includes the following steps:
step S401: the CPLD initiates a reading request based on an I2C Master module, and reads an original digital temperature signal acquired by the FPGA acceleration board card by the digital temperature sensor.
In the process of executing step S401, the CPLD initiates a read request to the digital temperature sensor, and the CPLD reads the original digital temperature signal of the FPGA acceleration board in the internal register of the digital temperature sensor.
Step S402: and the CPLD converts the original digital temperature signal to obtain the temperature of the FPGA acceleration board card.
Step S403: and when the times of reading the temperatures reach the preset times, judging whether all the read temperatures are greater than a preset threshold value.
It should be noted that, when the number of times of reading the temperatures reaches the preset number of times, if all the read temperatures are greater than the preset threshold, the reconfig pin of the FPGA is configured to be at a low level, so that the FPGA stops working.
Through the steps S401 to S403, the CPLD initiates a reading request based on the I2C Master module, reads an original digital temperature signal of the FPGA acceleration board acquired by the digital temperature sensor, converts the original digital temperature signal to obtain the temperature of the FPGA acceleration board, and determines whether all the read temperatures are greater than a preset threshold value when the number of times of reading the temperature reaches a preset number.
In the embodiment of the invention, a CPLD initiates a reading request based on an I2C Master module, a reading digital temperature sensor acquires an original digital temperature signal of an FPGA acceleration board card, the CPLD converts the original digital temperature signal to obtain the temperature of the FPGA acceleration board card, and when the times of reading the temperature reach a preset number, whether all the read temperatures are greater than a preset threshold value or not is judged, so that the FPGA executes corresponding operation according to whether all the read temperatures are greater than the preset threshold value or not is realized.
Based on the high-temperature protection method for the FPGA accelerator card disclosed in the embodiment of the present invention, the embodiment of the present invention also discloses a high-temperature protection device for the FPGA accelerator card correspondingly, as shown in fig. 5, the high-temperature protection device 500 for the FPGA accelerator card mainly includes:
a digital temperature sensor 501, a complex programmable logic device CPLD502 and a field programmable gate array FPGA 503.
The digital temperature sensor 501 is used for acquiring the temperature of the FPGA acceleration board card and storing the temperature;
the CPLD502 is configured to initiate a reading request to the digital temperature sensor, read the temperature of the FPGA acceleration board acquired by the digital temperature sensor, and when the number of times of reading the temperature reaches a preset number, determine whether all the read temperatures are greater than a preset threshold; if all the read temperatures are greater than a preset threshold value, configuring a rechfig pin of the FPGA503 to be a low level, and stopping the FPGA503 from working; and if all the read temperatures are within the normal working temperature range, configuring the reconfig pin of the FPGA503 to be at a high level.
Further, the digital temperature sensor 501 is specifically configured to:
and if any temperature in all the read temperatures is smaller than a preset threshold value, re-acquiring the temperature of the FPGA acceleration board card.
Further, the FPGA503 after configuring the reconfig pin of the FPGA503 to be at a high level is specifically further configured to:
and after the level state of the reconfig pin is kept for a preset time, configuring the reconfig pin of the FPGA503 to be in a high-impedance state.
Further, the digital temperature sensor 501 is configured to collect the temperature of the FPGA acceleration board, and store the temperature, and is specifically configured to:
and collecting an analog voltage signal on a thermistor of the FPGA503, converting the analog voltage signal into an original digital temperature signal, and storing the original digital temperature signal.
Further, a reading request is sent to the digital temperature sensor, the digital temperature sensor is read to acquire the temperature of the FPGA acceleration board, and when the number of times of reading the temperature reaches a preset number, the CPLD502 that determines whether all the read temperatures are greater than a preset threshold is specifically configured to:
initiating a reading request based on an I2C Master module, reading an original digital temperature signal acquired by the digital temperature sensor through the FPGA acceleration board card, converting the original digital temperature signal to obtain the temperature of the FPGA acceleration board card, and judging whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times.
The invention discloses a high-temperature protection device of an FPGA accelerator card, wherein a digital temperature sensor acquires the temperature of the FPGA accelerator card, a CPLD reads the temperature of the FPGA acquired by the digital temperature sensor, when the times of reading the temperature reach preset times, whether all the read temperatures are greater than a preset threshold value or not is judged, if all the read temperatures are greater than the preset threshold value, the FPGA stops working, and if all the read temperatures are within a normal working temperature range, a rechfig pin of the FPGA is configured to be at a high level. Through the scheme, if all read temperatures are greater than the preset threshold value, the FPGA is forced to stop working, when the temperature of the FPGA is reduced to a normal level, the FPGA is enabled to recover normal working, through the protection mechanism, a user can be reminded to check whether the FPGA is correctly installed and whether a server machine room has a problem or not, and the purpose of avoiding burning the FPGA is achieved.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus or apparatus embodiments, since they are substantially similar to the method embodiments, they are described relatively simply, and reference may be made to some descriptions of the method embodiments for related points. The above-described apparatuses and apparatus embodiments are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
It is to be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A high-temperature protection method of an FPGA acceleration card is characterized in that the method is applied to the FPGA acceleration card comprising a digital temperature sensor, a Complex Programmable Logic Device (CPLD) and a Field Programmable Gate Array (FPGA), and comprises the following steps:
the digital temperature sensor acquires an analog voltage signal on a thermistor of the FPGA acceleration board card, converts the analog voltage signal into the temperature of the FPGA acceleration board card through an analog-digital converter, and stores the temperature;
the CPLD initiates a reading request to the digital temperature sensor, reads the temperature of the FPGA acceleration board card acquired by the digital temperature sensor, and judges whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times;
if any temperature in all the read temperatures is smaller than a preset threshold value, the digital temperature sensor acquires the temperature of the FPGA acceleration board again;
if all the read temperatures are greater than a preset threshold value, configuring a rechfig pin of the FPGA as a low level, and stopping the FPGA from working;
if all the read temperatures are within the normal working temperature range, configuring the reconfig pin of the FPGA as a high level;
and after the level state of the reconfig pin of the FPGA is kept for a preset time, configuring the reconfig pin of the FPGA to be in a high-impedance state.
2. The method of claim 1, wherein the digital temperature sensor collects an analog voltage signal on a thermistor of the temperature of the FPGA acceleration board, converts the analog voltage signal into the FPGA acceleration board through an analog-to-digital converter, and stores the temperature, and the method comprises:
the digital temperature sensor acquires an analog voltage signal on a thermistor of the FPGA;
the digital temperature sensor converts the analog voltage signal into an original digital temperature signal;
the digital temperature sensor stores the raw digital temperature signal.
3. The method according to claim 1, wherein the CPLD issues a read request to the digital temperature sensor, reads the temperature of the FPGA acceleration board acquired by the digital temperature sensor, and when the number of times of reading the temperature reaches a preset number, determines whether all the read temperatures are greater than a preset threshold, including:
the CPLD initiates a reading request based on an I2CMaster module, and reads an original digital temperature signal acquired by the FPGA acceleration board card by the digital temperature sensor;
the CPLD converts the original digital temperature signal to obtain the temperature of the FPGA acceleration board card;
and when the times of reading the temperatures reach the preset times, judging whether all the read temperatures are greater than a preset threshold value.
4. A high temperature protection device of an FPGA accelerator card, the device comprising:
the digital temperature sensor is used for acquiring an analog voltage signal on a thermistor of the FPGA acceleration board card, converting the analog voltage signal into the temperature of the FPGA acceleration board card through an analog-digital converter and storing the temperature;
the CPLD is used for initiating a reading request to the digital temperature sensor, reading the temperature of the FPGA acceleration board card collected by the digital temperature sensor, and judging whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times; if all the read temperatures are greater than a preset threshold value, configuring a rechfig pin of the FPGA as a low level, and stopping the FPGA from working; if all the read temperatures are within the normal working temperature range, configuring the reconfig pin of the FPGA as a high level;
the digital temperature sensor is specifically further configured to: if any temperature in all the read temperatures is smaller than a preset threshold value, the temperature of the FPGA acceleration board card is collected again;
the CPLD, after configuring the reconfig pin of the FPGA to a high level, is specifically further configured to: and after the level state of the reconfig pin is kept for a preset time, configuring the reconfig pin of the FPGA to be in a high-impedance state.
5. The device of claim 4, wherein the digital temperature sensor is configured to collect an analog voltage signal on a thermistor of the FPGA acceleration board, convert the analog voltage signal into a temperature of the FPGA acceleration board through an analog-to-digital converter, and store the temperature, and is specifically configured to:
and collecting an analog voltage signal on a thermistor of the FPGA, converting the analog voltage signal into an original digital temperature signal, and storing the original digital temperature signal.
6. The device according to claim 4, wherein a read request is issued to the digital temperature sensor, the digital temperature sensor is read to acquire the temperature of the FPGA acceleration board, and when the number of times of reading the temperature reaches a preset number, the CPLD that determines whether all the read temperatures are greater than a preset threshold is specifically configured to:
initiating a reading request based on an I2CMaster module, reading an original digital temperature signal acquired by the FPGA acceleration board card by the digital temperature sensor, converting the original digital temperature signal to obtain the temperature of the FPGA acceleration board card, and judging whether all the read temperatures are greater than a preset threshold value or not when the times of reading the temperature reach preset times.
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| CN112526904A (en) * | 2020-11-26 | 2021-03-19 | 合肥富煌君达高科信息技术有限公司 | Working mode switching control method of electronic product circuit containing FPGA |
| TWI761134B (en) * | 2021-03-16 | 2022-04-11 | 英業達股份有限公司 | Smart nic with fpga chip overheating monitoring function |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201795876U (en) * | 2010-07-16 | 2011-04-13 | 湖南工程学院 | Digital thermometer |
| CN107193680A (en) * | 2017-05-18 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of heartbeat detecting method, equipment and system |
| CN107346170A (en) * | 2017-07-20 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of FPGA Heterogeneous Computings acceleration system and method |
| CN109240966A (en) * | 2018-08-20 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of accelerator card based on CPLD, collecting method and device |
| CN109614293A (en) * | 2018-12-13 | 2019-04-12 | 广东浪潮大数据研究有限公司 | A kind of management system and method for FPGA isomery accelerator card |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106200840A (en) * | 2016-07-07 | 2016-12-07 | 山东超越数控电子有限公司 | A kind of computer temperature method for handover control |
| CN107066067A (en) * | 2017-01-25 | 2017-08-18 | 郑州云海信息技术有限公司 | A kind of board Over Current Protection System, method, computer-readable recording medium and storage control |
| CN107038104A (en) * | 2017-04-27 | 2017-08-11 | 郑州云海信息技术有限公司 | A kind of method of remote monitoring isomery accelerator card |
-
2019
- 2019-08-16 CN CN201910757416.0A patent/CN110515437B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201795876U (en) * | 2010-07-16 | 2011-04-13 | 湖南工程学院 | Digital thermometer |
| CN107193680A (en) * | 2017-05-18 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of heartbeat detecting method, equipment and system |
| CN107346170A (en) * | 2017-07-20 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of FPGA Heterogeneous Computings acceleration system and method |
| CN109240966A (en) * | 2018-08-20 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of accelerator card based on CPLD, collecting method and device |
| CN109614293A (en) * | 2018-12-13 | 2019-04-12 | 广东浪潮大数据研究有限公司 | A kind of management system and method for FPGA isomery accelerator card |
Non-Patent Citations (1)
| Title |
|---|
| "Configuring Altera FPGAs";Altera Corporation;《https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cfg/cfg_cf51001.pdf》;20141215;第1-4页 * |
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