TWI761134B - Smart nic with fpga chip overheating monitoring function - Google Patents

Abstract

A smart NIC with FPGA chip overheating monitoring function includes a FPGA module and a CPLD module. The FPGA module includes an FPGA chip, a thermal detection unit, and a clock signal generation unit. The thermal detection unit detects a temperature of the FPGA chip to generate a chip temperature value. The clock signal generating unit is built-in with a first temperature warning value and a second temperature warning value greater than the first temperature warning value, and the clock signal generating unit generates a clock signal at different clock frequencies according to the chip temperature values. The CPLD module has a built-in counter clock that oscillates with a reference frequency, so that the clock frequency of the clock signal can be analyzed according by the counter clock, so that generates the clock frequencies of the clock signal, and then sent a cooling signal or an emergency cooling signal to a host.

Description

Smart NIC with FPGA chip thermal monitoring function

The present invention relates to an intelligent network card, in particular to an intelligent network card with the function of overheating monitoring of FPGA chips.

Generally speaking, the overheating monitoring and protection of the FPGA chip of the smart network card is performed by the CPLD, and the specific method is mainly to use the hot signal channel and the thermtrip signal channel to connect the FPGA and the CPLD respectively; among them, when the CPLD receives the FPGA When the transmitted hot signal is sent, the host will be notified to reduce the frequency so that the temperature of the FPGA chip can be lowered. In addition, when the CPLD receives the thermtrip signal sent by the FPGA, it will notify the host to turn off the power of the smart network card or directly shut down to prevent the temperature of the FPGA chip from continuing to rise.

As mentioned above, although the existing FPGA chip overheating protection mechanism can effectively protect the FPGA chip, it needs to occupy two pins of the FPGA and the CPLD, which limits the components that the FPGA and the CPLD can control.

In view of the fact that in the prior art, the FPGA chip of the existing smart network card mainly informs the CPLD whether the detected temperature value exceeds the preset safe value through the hot signal channel and the thermtrip signal channel. The number of pins of the CPLD; therefore, the main purpose of the present invention is to provide a smart network card with the function of monitoring the overheating of the FPGA chip, so that the FPGA can only use one channel to notify the CPLD of two overheating degrees of its chip, so that both the FPGA and the CPLD are overheated. A pin can be released to connect other components for control.

In order to solve the problems of the prior art, the present invention adopts the necessary technical means to provide an intelligent network card with an FPGA chip overheating monitoring function, which is electrically connected to a host, and the intelligent network card includes an FPGA module and a CPLD module. The FPGA module includes an FPGA chip, a thermal detection unit and a clock signal generation unit.

The thermal detection unit is used for detecting the temperature of the FPGA chip to generate a chip temperature value, and accordingly send out a temperature sensing signal. The clock signal generating unit is electrically connected to the thermal detection unit for receiving the temperature sensing signal, and has a built-in first temperature warning value and a second temperature warning value greater than the first temperature warning value, and the clock signal The generating unit sends a clock signal at different clock frequencies according to the chip temperature value, and sends the clock signal at a first clock frequency when the chip temperature value is between the first temperature warning value and the second temperature warning value , when the chip temperature value is greater than or equal to the second temperature warning value, a clock signal is sent out at a second clock frequency less than the first clock frequency.

The CPLD module is electrically connected to the clock signal generating unit, and has a built-in clock clock that oscillates with a reference clock frequency, so as to analyze the clock frequency of the clock signal according to the oscillation number of the clock clock. When the clock frequency of the analyzed clock signal is the first clock frequency, send a cooling signal to the host, and when the clock frequency of the analyzed clock signal is the second clock frequency, send an emergency cooling signal to the host.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the CPLD module further includes a count unit, a clock analysis unit and an overheat monitoring unit.

The timing unit is electrically connected to the clock signal generating unit, and has a built-in timing clock, so as to calculate the number of oscillations at the reference timing frequency during the oscillation period of the clock signal to generate a real-time cumulative number of oscillations.

The clock analysis unit is electrically connected to the timing unit, and has a built-in first oscillation judgment value and a second oscillation judgment value greater than the first oscillation judgment value. When the oscillation of the timing clock meets the oscillation of the clock signal period, and the cumulative number of real-time oscillations is less than or equal to the first oscillation judgment value, the clock frequency of the clock signal is judged to be the first clock frequency; The clock frequency of the clock signal is the second clock frequency.

The overheat monitoring unit is electrically connected to the clock analysis unit, and is used for sending a cooling signal to the host when the clock analysis unit determines that the clock frequency of the clock signal is the first clock frequency, and when the clock analysis unit determines When the clock frequency of the pulse signal is the second clock frequency, an emergency cooling signal is sent to the host.

Preferably, the reference count frequency is 10 times the first clock frequency, and the first oscillation judgment value is 10. In addition, the reference count frequency is 100 times the second clock frequency, and the second oscillation judgment value is greater than 10 and less than 100; further, the second oscillation judgment value is 30.

As mentioned above, because the smart network card with FPGA chip overheating monitoring function of the present invention mainly uses the clock signal generation unit of the FPGA module to send clock signals to the CPLD module with different clock frequencies according to different chip temperature values, and The CPLD module then analyzes the clock frequency of the clock signal through the oscillation of the reference count frequency oscillation, and then determines the temperature value of the FPGA chip, so as to further notify the host to perform actions such as frequency reduction or shutdown.

The specific embodiments adopted by the present invention will be further described by the following embodiments and drawings.

Please refer to the first figure. The first figure is a system block diagram of an intelligent network card with an overheat monitoring function of an FPGA chip provided by a preferred embodiment of the present invention. As shown in the first figure, a smart network card (hereinafter referred to as a smart network card) 100 with an FPGA chip overheating monitoring function is electrically connected to a host 200, and the host 200 includes an overheating unit 201, a processor 202 and a Power supply unit 203 .

The smart network card 100 includes an FPGA module 1 and a CPLD module 2 . The FPGA module 1 includes an FPGA chip 11 , a thermal detection unit 12 and a clock signal generation unit 13 . The thermal detection unit 12 is used for detecting the temperature of the FPGA chip 11 to generate a chip temperature value, and accordingly send a temperature sensing signal 12a.

The clock signal generating unit 13 is electrically connected to the thermal detection unit 12 for receiving the temperature sensing signal 12a, and has a first temperature warning value and a second temperature warning value greater than the first temperature warning value built in. And the clock signal generating unit 13 sends out a clock signal 13a with different clock frequencies according to the chip temperature value; wherein, when the chip temperature value is between the first temperature warning value and the second temperature warning value, a first temperature warning value is used. The clock signal 13a is sent out at a clock frequency, and the clock signal 13a is sent out at a second clock frequency less than the first clock frequency when the chip temperature value is greater than or equal to the second temperature warning value.

The CPLD module 2 includes a count unit 21 , a clock analysis unit 22 and an overheat monitoring unit 23 . The counting unit 21 is electrically connected to the clock signal generating unit 13, and has a built-in counting clock 211. The counting clock 211 oscillates at a reference counting frequency, so that during the oscillation period of the clock signal 13a, the counting clock 211 oscillates. , calculate the number of oscillations at the reference frequency to generate a cumulative number of real-time oscillations.

The clock analysis unit 22 is electrically connected to the counting unit 21, and has a built-in first oscillation judgment value 221 and a second oscillation judgment value 222 greater than the first oscillation judgment value 221; When the oscillation meets the oscillation period of the clock signal, and the cumulative number of real-time oscillations is less than or equal to the first oscillation judgment value 221, it is determined that the clock frequency of the clock signal 13a is the first clock frequency. When the accumulated number of times is greater than the second oscillation determination value, it is determined that the clock frequency of the clock signal 13a is the second clock frequency.

The overheat monitoring unit 23 is electrically connected to the clock analysis unit 22 for sending a cooling signal 23a to the overheating of the host 200 when the clock analysis unit 22 determines that the clock frequency of the clock signal 13a is the first clock frequency The processing unit 201 enables the overheating unit 201 to send a frequency reduction signal 201a to the processor 202 according to the temperature reduction signal 23a, so that the processor 202 can reduce the burden of the FPGA chip 11 through frequency reduction operation, thereby reducing the temperature of the FPGA chip 11; , when the clock analysis unit 22 determines that the clock frequency of the clock signal 13a is the second clock frequency, the overheat monitoring unit 23 sends an emergency cooling signal 23b to the overheating unit 201 of the host 200, so that the overheating unit 201 responds to the emergency The cooling signal 23b sends a shutdown signal 201b to the power supply unit 203, so that the power supply unit 203 shuts down the operation of the smart network card 100 by stopping the power supply, thereby preventing the FPGA chip 11 from being damaged due to the high temperature generated by the continuous operation.

Please continue to refer to the first figure to the third figure, the second figure is a schematic diagram showing the comparison between the reference clock frequency of the clock clock and the first clock frequency; the third figure shows the reference clock frequency of the clock clock and A schematic diagram of the comparison of the second clock frequency. As shown in the first to second diagrams, in this embodiment, the reference count frequency is, for example, 10KHz, the first clock frequency is, for example, 1KHz, and the second clock frequency is, for example, 100Hz, whereby the clock signal 13a is When the clock frequency is the first clock frequency of 1KHz, during the oscillation period P of the clock signal 13a, the cumulative number of real-time oscillations generated by the timing clock 211 oscillating at the reference timing frequency of 10KHz will be 10. More specifically, the oscillation period P of the clock signal 13a is further divided into the first half period P1 and the second half period P2. When the clock signal 13a oscillates with the first clock frequency of 1KHz as the clock frequency to the time point T1 of the first half period P1 , the cumulative number of real-time oscillations at the reference frequency of 10KHz is 5, and the clock signal 13a uses the first clock frequency of 1KHz as the clock frequency to oscillate from the time point T1 to the time point T2 of the second half cycle P2, and the reference count frequency is 10KHz. The number of real-time oscillation accumulation will be accumulated to 10.

In addition, when the clock frequency of the clock signal 13a is the second clock frequency of 100Hz, during the oscillation period P' of the clock signal 13a, the timing clock 211 oscillates at the reference clock frequency of 10KHz, and the real-time oscillation accumulated The number of times will be 100. More specifically, the oscillation period P' of the clock signal 13a is also further divided into the first half period P1' and the second half period P2'. At the time point T1', the cumulative number of real-time oscillations at the reference frequency of 10KHz is 50, and the clock signal 13a uses the second clock frequency of 100Hz as the clock frequency from the time point T1' to the time point of the second half cycle P2'. At T2', the real-time oscillation accumulation times of the reference frequency of 10KHz will accumulate to 100.

As mentioned above, in this embodiment, when the thermal detection unit 12 detects that the chip temperature value of the FPGA chip 11 is between the first temperature warning value and the second temperature warning value, the clock signal generating unit 13 The clock signal 13a is sent to the CPLD module 2 at the first clock frequency. At this time, the clock signal 13a is calculated by the clock clock 211 to oscillate at the reference clock frequency during the oscillation period of the clock signal 13a. Accumulated times, and since the reference counting frequency 10KHz is 10 times the first clock frequency 1KHz, when the counting clock 211 oscillates at the reference counting frequency to satisfy the oscillation period P of the clock signal 13a, its counting The cumulative number of real-time oscillations of the clock 211 will be 10; thus, the clock analysis unit 22 will determine the time of the clock signal 13 a because the cumulative number of real-time oscillations is less than or equal to the first oscillation judgment value 221 (10 in this embodiment). The pulse frequency is the first clock frequency, so that the overheat monitoring unit 23 can determine that the chip temperature value of the FPGA chip 11 is between the first temperature warning value and the second temperature according to the clock frequency of the clock signal 13a being the first clock frequency between the warning values.

In addition, when the thermal detection unit 12 detects that the chip temperature value of the FPGA chip 11 is greater than or equal to the second temperature warning value, the clock signal generating unit 13 will send the clock signal 13a to the CPLD module at the second clock frequency 2. At this time, through the calculation of the timing clock 211, the cumulative number of real-time oscillations generated by oscillating at the reference timing frequency within the oscillation period P' of the clock signal 13a, and since the reference timing frequency 10KHz is the second clock The frequency is 100 times of 100Hz, so when the timing clock 211 oscillates at the reference timing frequency to satisfy the oscillation period P' of the clock signal 13a, the cumulative number of real-time oscillations of the timing clock 211 will be 100; however, Since the second oscillation determination value of this embodiment is 30, although the timing clock 211 oscillates at the reference timing frequency until the accumulated number of real-time oscillations exceeds 30, the clock analysis unit 22 will determine the clock signal 13a The clock frequency is the second clock frequency, so that the overheat monitoring unit 23 can determine that the chip temperature value of the FPGA chip 11 is greater than or equal to the second temperature warning value according to the clock frequency of the clock signal 13a being the second clock frequency.

It should be noted that, although in this embodiment, the timing clock 211 oscillates at the reference timing frequency until the oscillation period P' of the clock signal 13a is satisfied, the accumulated number of real-time oscillations of the timing clock 211 will be is 100, but since the cumulative number of real-time oscillations of the timing clock 211 exceeds the first oscillation judgment value, the chip temperature value of the FPGA chip 11 is already greater than or equal to the second temperature warning value, so the second oscillation judgment value is set as 30 can determine in advance that the chip temperature value of the FPGA chip 11 is greater than or equal to the second temperature warning value. In other words, setting the second oscillation judgment value to 11 to 100 can reflect that the chip temperature value of the FPGA chip 11 is greater than or equal to the second temperature For the warning value, only the second oscillation judgment value is slightly more than 10 of the first oscillation judgment value, which can avoid misjudgment, and is less than half of the maximum value of 100, which can improve the judgment efficiency.

To sum up, compared with the smart network card of the prior art, the temperature of the FPGA chip is notified to the CPLD through the hot signal channel and the thermtrip signal channel, thereby limiting the number of pins of the FPGA and the CPLD. The present invention has the function of monitoring the overheating of the FPGA chip. The smart network card is mainly that the FPGA module uses the clock signal generation unit to send clock signals to the CPLD module at different clock frequencies according to different chip temperature values, and the CPLD module then analyzes the oscillation of the reference frequency oscillation. The clock frequency of the clock signal, and then determine the temperature value of the FPGA chip, so as to further notify the host to perform actions such as frequency reduction or shutdown. In this way, the FPGA module and the CPLD module can be separated from each other because one signal channel is missing. A pin is released, which can then be used to connect other components for control.

Through the detailed description of the preferred embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the claimed scope of the present invention.

100: Smart NIC with FPGA chip overheating monitoring function 1: FPGA module 11:FPGA chip 12: Thermal detection unit 13: Clock signal generation unit 2: CPLD module 21: Counting unit 211: count clock 22: Clock analysis unit 221: The first oscillation judgment value 222: The second oscillation judgment value 23: Overheating monitoring unit 200: host 201: Overheating unit 202: Processor 203: Power Supply Unit 12a: Temperature sensing signal 13a: Clock signal 23a: cooling signal 23b: Emergency cooling signal 201a: Down-frequency signal 201b: Shutdown signal P,P': oscillation period P1,P1': the first half cycle P2,P2': the second half cycle T1,T1',T2,T2': time points

The first figure shows the system block diagram of the smart network card with FPGA chip overheating monitoring function provided by the preferred embodiment of the present invention; The second figure is a schematic diagram showing the comparison between the reference clock frequency of the clock clock and the first clock frequency; and The third figure is a schematic diagram showing the comparison between the reference clock frequency of the clock clock and the second clock frequency.

100: Smart NIC with FPGA chip overheating monitoring function

1: FPGA module

11:FPGA chip

12: Thermal detection unit

13: Clock signal generation unit

2: CPLD module

21: Counting unit

211: count clock

22: Clock analysis unit

221: The first oscillation judgment value

222: The second oscillation judgment value

23: Overheating monitoring unit

200: host

201: Overheating unit

202: Processor

203: Power Supply Unit

12a: Temperature sensing signal

13a: Clock signal

23a: cooling signal

23b: Emergency cooling signal

201a: Down-frequency signal

201b: Shutdown signal

Claims (5)

An intelligent network card with an FPGA chip overheating monitoring function is electrically connected to a host, and the intelligent network card comprises: An FPGA module, including: an FPGA chip; a thermal detection unit for detecting the temperature of the FPGA chip to generate a chip temperature value, and to send a temperature sensing signal accordingly; and A clock signal generating unit is electrically connected to the thermal detection unit for receiving the temperature sensing signal, and has a built-in first temperature warning value and a second temperature warning value greater than the first temperature warning value, And the clock signal generating unit sends out a clock signal at different clock frequencies according to the chip temperature value, when the chip temperature value is between the first temperature warning value and the second temperature warning value, a first temperature warning value is used. The clock signal is sent at a clock frequency, and the clock signal is sent at a second clock frequency less than the first clock frequency when the chip temperature value is greater than or equal to the second temperature warning value; and A CPLD module, which is electrically connected to the clock signal generating unit, has a built-in clock clock oscillating at a reference clock frequency, and the reference clock frequency is greater than the first clock frequency or the first clock frequency. Two clock frequencies, so as to analyze the clock frequency of the clock signal according to the number of oscillations of the timing clock, when the clock frequency of the clock signal is analyzed to be the first clock frequency, a cooling signal Send to the host, and send an emergency cooling signal to the host when the clock frequency of the clock signal is analyzed to be the second clock frequency. The smart network card with FPGA chip overheating monitoring function as described in claim 1, wherein the CPLD module further comprises: A counting unit, which is electrically connected to the clock signal generating unit, has the counting clock built in, and is generated by calculating the number of oscillations at the reference counting frequency during the oscillation period of the clock signal. 1. The cumulative number of real-time oscillations; A clock analysis unit is electrically connected to the count unit, and has a built-in first oscillation judgment value and a second oscillation judgment value greater than the first oscillation judgment value. When the oscillation of the count clock meets the The oscillation period of the clock signal, and the cumulative number of real-time oscillations is less than or equal to the first oscillation judgment value, determine that the clock frequency of the clock signal is the first clock frequency, when the real-time oscillation of the timing clock When the accumulated number of times is greater than the second oscillation determination value, determine that the clock frequency of the clock signal is the second clock frequency; and an overheat monitoring unit electrically connected to the clock analysis unit for sending the cooling signal to the host when the clock analysis unit determines that the clock frequency of the clock signal is the first clock frequency, And when the clock analysis unit determines that the clock frequency of the clock signal is the second clock frequency, the emergency cooling signal is sent to the host. The smart network card with FPGA chip overheating monitoring function as described in claim 2, wherein the reference count frequency is 10 times the first clock frequency, and the first oscillation judgment value is 10. The smart network card with FPGA chip overheat monitoring function as claimed in claim 3, wherein the reference count frequency is 100 times the second clock frequency, and the second oscillation judgment value is greater than 10 and less than 100. The smart network card with FPGA chip overheating monitoring function according to claim 4, wherein the second oscillation judgment value is 30.

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