CN110504250A - Cascade enhanced GaNHEMT power module package structure and packaging method - Google Patents

Cascade enhanced GaNHEMT power module package structure and packaging method Download PDF

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CN110504250A
CN110504250A CN201910789617.9A CN201910789617A CN110504250A CN 110504250 A CN110504250 A CN 110504250A CN 201910789617 A CN201910789617 A CN 201910789617A CN 110504250 A CN110504250 A CN 110504250A
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gan hemt
cascade
binding line
hemt device
enhanced gan
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CN110504250B (en
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周德金
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Zhuhai Jiadan Technology Co ltd
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Wuxi Paiwei Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/0406—Modifications for accelerating switching in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0045—Full bridges, determining the direction of the current through the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present invention relates to a kind of enhanced GaN HEMT power module package structures of cascade, including package casing, metal lead wire frame and pin, in package casing further include: the enhanced GaN HEMT device of the first cascade, the enhanced GaN HEMT device of the second cascade, third cascades enhanced GaN HEMT device, the fourth stage joins enhanced GaN HEMT device, full-bridge gate drive circuit；It includes: high-pressure depletion transistor npn npn, low-voltage enhancement-mode transistor, voltage-regulating circuit, Ji Dao, the first electrically-conductive backing plate, the second electrically-conductive backing plate, third electrically-conductive backing plate that each, which cascades enhanced GaN HEMT device,.Module provided by the present invention, which passes through, will bind the optimization that body inductance is posted in line length minimum realization；In addition, also adding voltage-regulating circuit, guarantee that the high voltage depletion mode GaN device of its inside modules works in safety zone state.

Description

Cascade enhanced GaNHEMT power module package structure and packaging method
Technical field
The present invention relates to a kind of enhanced GaN HEMT power module integrated encapsulation structure of cascade and packaging methods, belong to function Rate electronic technology field.
Background technique
In the 21st century, is under the traction of the new industries such as smart grid, mobile communication and new-energy automobile, electric power electricity Sub- application system requires to further increase the efficiency of system, miniaturization and increases function, and special requirement circuit is applied in size, matter Tradeoff between amount, power and efficiency, such as micro- inverter of server power supply management, battery charger and solar energy electric field. Above-mentioned application requirement power electronic system also has high power density (> 500W/in while design efficiency > 95%3, i.e., 30.5W/cm3), high-specific-power (10kW/ pounds, 22kW/kg) and high total load point (> 1000W).With super node MOSFET and insulation The appearance and application popularization of grid bipolar transistor (IGBT), device performance move closer to the limit of silicon materials, and every 4 years power is close The rule that degree promotes 1 times tends to be saturated (Moore's Law of field of power electronics), and power density is only the silicon-based power of units The exploitation of semiconductor devices is for these reasons and difficult.
It is in recent years the third generation semiconductor power device of representative with gallium nitride (GaN), because forbidden band is wide, breakdown field strength High, high electron saturation velocities are fast, lead in high-power, high temperature, high frequency, anti-radiation microelectronic field and short-wavelength light electronics There is the performance for being substantially better than the first generation such as Si, Ge, GaAs and second generation semiconductor material in domain.GaN power device and Si device phase Than with superior on-state characteristic and extraordinary switching characteristic, therefore the pass of industry is just attracted in a relatively short period of time Note.Studies have shown that switching frequency can be increased substantially with GaN device replacement Si device, while keeping good efficiency index.
The characteristic of GaN device, so that gate driving charge (Qg) very little of GaN device, junction capacity is also very small, therefore opens It is faster to close speed ratio Si device.Good is that switching frequency can be improved, but bad one side is exactly to switch in switching process on one side The curent change of branch is very fast, di/dt is very high.Due to inevitably there is parasitic inductance in loop of power circuit, work as electric current Rapidly when variation, very high peak overvoltage can be generated at switching device both ends.It is light then cause circuit erroneous action, EMI exceeded, weight Then device breakdown is caused to be damaged.The very high switching speed of GaN device cause in its switching process oscillation caused by parasitic inductance and Overvoltage phenomenon is obvious more than Si device.To realize that switching frequency maximizes, the parasitic inductance of GaN device must be minimized.
GaN HEMT can be divided into enhanced and two kinds of depletion type, the enhanced type GaN HEMT of high pressure under technical conditions at present Transistor is difficult to manufacture.The voltage rating maximum of the enhanced GaN HEMT device of monomer can reach 300V at present.Monomer is increased Strong type GaN HEMT, when its driving voltage reaches threshold voltage Vth=1.5V, device will be connected, and device is fully on Grid voltage is 4.5V~5.5V, and since its maximum gate source voltage Vgs is 6V, enhanced GaN device wants driving design Ask higher.And monomer depletion type GaN HEMT device is easily achieved 650V or more high pressure, and its drive voltage range is -30 ~2V, the fully on grid voltage of device are -5V, and drive voltage range is wider.However, current machine system is more biased towards in use Enhanced switching device.Therefore high voltage depletion mode GaN HEMT transistor is formed in conjunction with other low-voltage enhancement-mode transistors Enhanced GaN HEMT device is mixed with very big current demand.Mix enhanced GaN HEMT device can with single high pressure The identical mode of enhancement transistor operates, and realizes special with the same or similar output of the enhanced HEMT transistor of single high pressure Property, it is used convenient for machine system.
Fig. 1 a show a kind of existing schematic diagram for cascading enhanced GaN HEMT device, is a kind of typical mixing increasing Strong type GaN HEMT device.The mixing enhancement device of Fig. 1 a includes the high voltage depletion mode crystalline substance being enclosed in packaging body 00 simultaneously Body pipe 10 and low-voltage enhancement-mode transistor 11.The source S of low-voltage enhancement-mode transistor 11 and the grid of high-pressure depletion transistor npn npn 10 Pole is joined together and is electrically connected to source lead output S.The grid of low-voltage enhancement-mode transistor 11 is connected to grid Lead G.The drain electrode of high-pressure depletion transistor npn npn 10 is electrically connected to drain lead D, and the source electrode of high-pressure depletion transistor npn npn 10 is electrically connected It is connected to the drain electrode of low-voltage enhancement-mode transistor 11.
The working principle of the enhanced GaN HEMT device of cascade shown in Fig. 1 a are as follows: when G voltage is > high voltage of Vth10 when, Low-voltage enhancement-mode transistor 11 is in saturation conduction state, the source-drain voltage Vds11 ≈ 0 of low-voltage enhancement-mode transistor 11, high pressure The gate source voltage Vgs10=Vds11 ≈ 0 of depletion mode transistor 10, high-pressure depletion transistor npn npn 10 open conducting, and cascade increases at this time Strong type GaN HEMT device is in the conductive state, and high back voltage Vds=(Vds11+Vds10) ≈ 0；When G voltage be < When the low-voltage of Vth10, low-voltage enhancement-mode transistor 11 is in off state, the source-drain voltage of low-voltage enhancement-mode transistor 11 Vds11 " 0 (the partial pressure pressure drop depending on transistor 11 under cut-off condition and transistor 10), the grid of high-pressure depletion transistor npn npn 10 Source voltage Vgs10=-Vds11, if Vgs10 is lower than Vth10, high-pressure depletion transistor npn npn 10 is similarly in off state, this When cascade enhanced GaN HEMT device and be in off state, and high back voltage Vds's is most of by high voltage depletion mode crystal Pipe 10 undertakes.It can be seen that the control mode and function and the enhanced switching device class of ordinary high pressure of the enhanced HEMT device of mixing Seemingly.
When cascading enhanced GaN HEMT device and being in off state, due to Vds=Vds11+Vds10, usually it is arranged The ratio of Vds10/Vds11 is higher than 5 times or more (being also possible to 10 times, 20 times), to guarantee to cascade enhanced GaN HEMT device Reverse withstand voltage is largely undertaken by high-pressure depletion transistor npn npn 10 when part ends.It is packed when cascading enhanced GaN HEMT device After fixation, the ratio of Vds10/Vds11 is fixed value regardless of how many.For different actual application backgrounds, cascade enhanced The reverse withstand voltage of GaN HEMT device is not quite similar, and the gate source voltage Vgs10=-Vds11 of high-pressure depletion transistor npn npn 10, And the ratio of Vds10/Vds11 is fixed value, this will lead to gate source voltage of the same device in different application systems The maximum value of absolute value ︱ Vgs10=-Vds11 ︱ is different.For conventional high-pressure enhanced power switch, gate source voltage Vgs Unbearable high pressure, to improve power switch reliability, gate source voltage Vgs is generally fixed value in the case of cut-off, and electric close to 0 Pressure.And for the high-pressure depletion transistor npn npn 10 described in Fig. 1 a, gate source voltage Vgs10's is absolute under cut-off condition Value ︱-Vds11 ︱ is much larger than 0, and is not also fixed voltage for different application systems absolute value ︱-Vds11 ︱, inevitable The overall reliability of the enhanced GaN HEMT device of cascade shown in serious limitation Fig. 1 a.Therefore, increase to improve to cascade shown in Fig. 1 a The overall reliability of strong type GaN HEMT device, it is necessary to by the gate source voltage under 10 cut-off condition of high-pressure depletion transistor npn npn Absolute value ︱-Vds11 the ︱ of Vgs10 is set as the fixed value not fluctuated with whole reverse withstand voltage Vds.And the fixed value should It is small as far as possible, it is only necessary to can smoothly to turn off high-pressure depletion transistor npn npn 10 lower than Vth10 voltage 2V guarantee.
Fig. 1 b show a kind of typical package way of realization for the enhanced GaN HEMT device of cascade that Fig. 1 a is provided.High pressure Depletion mode transistor 10 and low-voltage enhancement-mode transistor 11 are placed on electrically-conductive backing plate J0, and are encapsulated in the same packaging body In 00.Since low-voltage enhancement-mode transistor 11 generallys use VDMOS device, its source S 11 is directly welded at downward usually and is led On electric substrate J0.And the generally planar device of existing GaN HEMT high-pressure depletion transistor npn npn 10, usually by its back side using exhausted Edge glue sticking is on electrically-conductive backing plate J0.The grid of low-voltage enhancement-mode transistor 11 by binding line B02 be connected to cascade it is enhanced The drain D 11 of the grid G 00 of GaN HEMT device, low-voltage enhancement-mode transistor 11 is connected to high-pressure depletion by binding line B04 The grid G 10 of the source S 10 of transistor npn npn 10, high-pressure depletion transistor npn npn 10 is connected to by binding line B03 in electrically-conductive backing plate The drain D 10 of J0 and the source S 00 for cascading enhanced GaN HEMT device, high-pressure depletion transistor npn npn 10 passes through binding line B01 It is connected to the drain D 00 for cascading enhanced GaN HEMT device.Binding line B01, binding line B02, binding line B03 and binding line The length of B04 is influenced by the size of packaging body physical size, position and chip size, especially binding line B01, binding line B02 It is difficult to reduce with the length of binding line B04.When the switch operating frequency of the enhanced GaN HEMT device of cascade reduces, tie up The influence of alignment B01, binding line B02 and binding line B04 can be ignored, when the enhanced GaN HEMT device of cascade (500KHz is greater than) when switch operating frequency is very big, and binding line B01, binding line B02 and binding line B04 are equivalent to 3 Parasitic inductance.As shown in Fig. 2, binding line B01, binding line B02 and the corresponding parasitic inductance of binding line B04 are respectively L13, L12 And L11.Especially L11, which is located at, states 00 front end of grid G for cascading enhanced GaN HEMT device, and voltage overshoot caused by L11 will The reliability for cascading the grid G 00 of enhanced GaN HEMT device can be seriously affected, and as switch operating frequency is higher, shadow Sound is more obvious.Therefore, it is to improve the switching frequency for cascading enhanced GaN HEMT device, binding line B01, binding line B02 and ties up Parasitic inductance effect caused by alignment B04 must minimize.
Fig. 3 show a kind of schematic diagram of highly reliable enhanced GaN HEMT device of cascade, in the mixing that Fig. 1 a is provided A voltage-regulating circuit 30 is increased on the basis of enhanced GaN HEMT device.Newly-increased voltage-regulating circuit 30 acts on Absolute value ︱-Vds11 the ︱ of the gate source voltage Vgs10 under 10 cut-off condition of high-pressure depletion transistor npn npn is controlled in adjustment, it will Absolute value ︱-Vds11 the ︱ of Vgs10 is set as the fixed value not fluctuated with whole reverse withstand voltage Vds.
The enhanced GaN HEMT device of cascade described in Fig. 3 includes the high voltage depletion mode crystalline substance being enclosed in packaging body 00 simultaneously Body pipe 10, low-voltage enhancement-mode transistor 11 and voltage-regulating circuit 30.The source S of low-voltage enhancement-mode transistor 11, high-pressure depletion The grid of transistor npn npn 10 and the lower end 31 of voltage-regulating circuit 30 are joined together and to be electrically connected to source lead defeated S out.The grid of low-voltage enhancement-mode transistor 11 is connected to grid lead G.The drain electrode of high-pressure depletion transistor npn npn 10 is electrically connected to Drain lead D, the source electrode of high-pressure depletion transistor npn npn 10 are electrically connected to the drain electrode and voltage adjustment of low-voltage enhancement-mode transistor 11 The upper end 32 of circuit 30.
In the application of practical electrical engineering system, full bridge power module is most common power integration module.Therefore, it cascades Enhanced GaN HEMT device is likely in practical engineering applications using full-bridge switch structure, and to realize that volume is minimum Change, full-bridge switch structure, which is generally integrated, is packaged into full bridge power module.Based on this, the present invention determines to cascade using low parasitic inductance Connection type inside enhanced GaN HEMT device designs full bridge power module.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, it is enhanced to propose a kind of low parasitic inductance cascade The construction and packaging method of GaN power module integration packaging not only solve the enhanced GaN HEMT device of cascade of Fig. 1 a, Fig. 1 b Gate source voltage Vgs10 under 10 cut-off condition of part mesohigh depletion mode transistor be not fixed caused by integrity problem, it is also right Parasitic inductance effect problem caused by binding line B01, binding line B02 and binding line B04 is optimized to greatest extent.
According to technical solution provided by the invention, the enhanced GaN HEMT power module package structure of the cascade includes Package casing, metal lead wire frame and pin, in package casing further include: the enhanced GaN HEMT device of the first cascade, the The enhanced GaN HEMT device of two cascades, third cascade enhanced GaN HEMT device, the fourth stage joins enhanced GaN HEMT device Part, full-bridge gate drive circuit；The first input end of full-bridge gate drive circuit connects the 5th pin, full-bridge by the 19th binding line Second input terminal of gate drive circuit connects the 6th pin by the 20th binding line；The first switch of full-bridge gate drive circuit is believed Number G0 output is connected to the left end in the first inner lead bonding area by the first binding line, and the right end in the first inner lead bonding area passes through Second binding line is connected to the grid end input point of the enhanced GaN HEMT device of the first cascade；The second of full-bridge gate drive circuit opens OFF signal G1 exports the left end that the second inner lead bonding area is connected to by third binding line, the right end in the second inner lead bonding area The grid end input point of the enhanced GaN HEMT device of the second cascade is connected to by the 4th binding line；The of full-bridge gate drive circuit Three switching signal G2 export the left end that third inner lead bonding area is connected to by the 5th binding line, third inner lead bonding area Right end is connected to the grid end input point that third cascades enhanced GaN HEMT device by the 6th binding line；Full-bridge gate drive circuit The 4th switching signal G3 output the left end in the 4th inner lead bonding area, the 4th inner lead bonding are connected to by the 7th binding line The right end in area is connected to the grid end input point that the fourth stage joins enhanced GaN HEMT device by the 8th binding line；
The drain electrode of the first enhanced GaN HEMT device of cascade is connected to third pin, the first cascade by the 9th binding line The source electrode of enhanced GaN HEMT device is connected to the first pin；The drain electrode of the second enhanced GaN HEMT device of cascade passes through the 11 binding lines are connected to the first pin, and the source electrode of the second enhanced GaN HEMT device of cascade is connected by the 12nd binding line To the 4th pin；The drain electrode that third cascades enhanced GaN HEMT device is connected to third pin by the 14th binding line, the The source electrode of the three enhanced GaN HEMT devices of cascade is connected to second pin by the 16th binding line；Fourth stage connection is enhanced The drain electrode of GaN HEMT device is connected to second pin by the 17th binding line, and the fourth stage joins enhanced GaN HEMT device Source electrode is connected to the 4th pin；The output of first pin is that the first bridge arm exports SW0, and the output of second pin is that the second bridge arm is defeated SW1 out, the output of third pin are high voltage bus VSS, and the output of the 4th pin is low-voltage bus bar GND, the input of the 5th pin For the first driving signal PWH, the input of the 6th pin is the second driving signal PWL.
Further, the enhanced GaN HEMT device of first cascade, the enhanced GaN HEMT device of the second cascade, the The structure that the three enhanced GaN HEMT devices of cascade join enhanced GaN HEMT device with the fourth stage is identical with implementation.
Further, the stringent phase of length of first binding line, third binding line, the 5th binding line and the 7th binding line Deng；Second binding line, the 4th binding line, the length of the 6th binding line and the 8th binding line are strictly equal；In described first Pin bonding area, the second inner lead bonding area, the geometric dimension in third inner lead bonding area and the 4th inner lead bonding area are stringent It is equal.
Further, it includes: that high-pressure depletion transistor npn npn, low pressure are enhanced that each, which cascades enhanced GaN HEMT device, Transistor, voltage-regulating circuit, Ji Dao, the first electrically-conductive backing plate, the second electrically-conductive backing plate, third electrically-conductive backing plate, the first electrically-conductive backing plate, The front that insulating cement is bonded in Ji Dao is respectively adopted in the back side of second electrically-conductive backing plate and third electrically-conductive backing plate；The enhanced crystal of low pressure The grid of pipe is connected to the front of the first electrically-conductive backing plate, and the front of the first electrically-conductive backing plate is connected to the affiliated enhanced GaN of cascade The grid of HEMT device；The drain electrode of low-voltage enhancement-mode transistor is connected to the front of third electrically-conductive backing plate, third electrically-conductive backing plate Front is also connected to the upper end of voltage-regulating circuit and the source electrode of high-pressure depletion transistor npn npn；The grid of high-pressure depletion transistor npn npn It is connected to the source electrode in the front of Ji Dao, the lower end of voltage-regulating circuit and the affiliated enhanced GaN HEMT device of cascade；High pressure The drain electrode of depletion mode transistor is connected to the front of the second electrically-conductive backing plate, and the front of the second electrically-conductive backing plate is connected to affiliated cascade and increases The drain electrode of strong type GaN HEMT device；The source electrode of low-voltage enhancement-mode transistor is connected to the front of Ji Dao by binding line.
Further, the low-voltage enhancement-mode transistor uses VDMOS device, and after flip chip bonding, grid passes through Conductive solder is directly welded at the first electrically-conductive backing plate front, and drain electrode is being directly welded at third electrically-conductive backing plate just by conductive solder Face.
Further, the high-pressure depletion transistor npn npn is planar device, and using flip-chip method, grid, which directly passes through, is led Electric welding material is welded on the front of the first Ji Dao, and source electrode is welded on third electrically-conductive backing plate front by conductive solder, and drain electrode is logical It crosses conductive solder and is welded on the second electrically-conductive backing plate front.
The packaging method of the above-mentioned enhanced GaN HEMT power module package structure of cascade, includes the following steps:
Step 1, designs and produces metal lead wire frame, and the island each unit You Wuchuji is used to place grid driving chip and function Rate device；
Step 2 applies insulating cement, the gluing of each Ji Dao in the first, second, third and fourth base island front corresponding position Position respectively corresponds the position of its first, second and third electrically-conductive backing plate；
The reverse side of first, second and third electrically-conductive backing plate is fixed on base island front by insulating cement by step 3, until the One, second, third, the 4th Ji Dao be fully completed electrically-conductive backing plate stickup；
Step 4 needs the position of interface unit electrode to apply conductive solder on the front of all electrically-conductive backing plates, and first leads The drain electrode of corresponding high-pressure depletion transistor npn npn is expected in electric welding, and the second conductive solder corresponds to the grid of low-voltage enhancement-mode transistor, third Conductive solder corresponds to the drain electrode of low-voltage enhancement-mode transistor, and the 4th conductive solder corresponds to the source electrode of high-pressure depletion transistor npn npn, the The upper end of six conductive solder corresponding voltage adjustment circuits；Each base island same operation；
Step 5 applies conductive solder, the 5th conductive solder pair in the first, second, third, fourth base island front corresponding position Answer the grid of high-pressure depletion transistor npn npn, the lower end of the 7th conductive solder corresponding voltage adjustment circuit；Simultaneously the 5th Ji Dao just Face applies solder layer；
Step 6 leads to the counter electrode of high-pressure depletion transistor npn npn, low-voltage enhancement-mode transistor and voltage-regulating circuit It crosses conductive solder to be electrically connected with electrically-conductive backing plate front, full-bridge gate drive circuit chip back is being attached to the 5th Ji Dao just Face；
The device that previous step is completed is put into baking oven, is filled with nitrogen as protective gas, really by step 7, baking process The oxygen content protected in baking oven is maintained at 100ppm or less；After the completion of baking, it is reduced to room temperature to the temperature in baking oven, takes out device Part；
Step 8, bond technology are sent into press welder material track after the completion of baking, according to the image recognition and cloth debugged Line scheme carries out routing, and pressure welding is detected after completing；
Step 9, the packaging body frame qualified to step 8 detection are packaged body injection molding and fix.
Further, the thickness of conductive solder used in insulating cement and step 4 used in step 2 be 20 μm- 40 μm, the used conductive solder of step 5 with a thickness of 100 μm -110 μm, and the temperature-resistance characteristic of two kinds of materials must be suitable.
The invention has the advantages that the structure of provided GaN power module integration packaging, realizes internal any cascade and increases Strong type GaN HEMT device, which passes through, will bind the optimization that body inductance is posted in line length minimum realization；In addition, increasing voltage adjustment Circuit guarantees the work of high voltage depletion mode GaN device in safety zone state；Finally, this integrated encapsulation structure realizes volume most Smallization reduces parasitic inductance to the full extent while improving reliability, guarantees that the HF switch of GaN full bridge power module is special Property.
Detailed description of the invention
Fig. 1 a is the schematic diagram of the existing enhanced GaN HEMT device of cascade.
Fig. 1 b is the typical package way of realization of the existing enhanced GaN HEMT device of cascade.
Fig. 2 is the parasitic inductance schematic diagram of the existing enhanced GaN HEMT device of cascade.
Fig. 3 is a kind of schematic diagram of highly reliable enhanced GaN HEMT device of cascade.
Fig. 4 a is the schematic diagram that the present invention cascades enhanced GaN HEMT full bridge power module.
Fig. 4 b is a kind of way of realization of the invention.Wherein: P00-- package casing, first Ji Dao, J01-- of J00-- second The 4th the 5th first inner lead bonding area Ji Dao, J06-- Ji Dao, J10-- of Ji Dao, J02-- third Ji Dao, J03--, J07-- Two inner lead bonding areas, J08-- third inner lead bonding area, the 4th inner lead bonding area J09--, the first pin of J21--, J22-- second pin, J23-- third pin, the 4th pin of J24--, 351-- first cascade enhanced GaN HEMT device, 352-- second cascades enhanced GaN HEMT device, 353-- third cascades enhanced GaN HEMT device, 354-- fourth stage connection Enhanced GaN HEMT device, 350-- full-bridge gate drive circuit, the first binding line of B1--, the second binding line of B2--, B3-- third Binding line, the 4th binding line of B4--, the 5th binding line of B5--, the 6th binding line of B6--, the 7th binding line of B7--, B8-- the 8th are tied up Alignment, the 9th binding line of B9--, the tenth binding line of B10--, the 11st binding line of B11--, the 12nd binding line of B12--, B13-- 13rd binding line, the 14th binding line of B14--, the 15th binding line of B15--, the 16th binding line of B16--, B17-- the tenth Seven binding lines, the 18th binding line of B18--, the 19th binding line of B19--, the 20th binding line of B20--.
Fig. 4 c is a kind of complete way of realization of an enhanced GaN HEMT device of cascade in Fig. 4 b.Wherein: J31-- One electrically-conductive backing plate, the second electrically-conductive backing plate of J32--, J33-- third electrically-conductive backing plate, 10-- high voltage depletion mode GaN transistor, 11-- are low Press enhancement transistor, 30-- voltage-regulating circuit.
Fig. 5 is packaging method flow chart of the present invention.
Fig. 6 a-6h is the schematic diagram of integrated encapsulation method step 1~step 9 of the present invention.Wherein: Jh31-- first insulate Glue, the second insulating cement of Jh32--, Jh33-- third insulating cement.
Specific embodiment
The present invention is described in more detail with reference to the accompanying drawings and examples.
Fig. 4 a is the schematic diagram that the present invention cascades enhanced GaN HEMT power module, including the first enhanced GaN of cascade HEMT device 351, second cascades enhanced GaN HEMT device 352, third cascades enhanced GaN HEMT device the 353, the 4th Cascade enhanced GaN HEMT device 354 and full-bridge gate drive circuit 350, the 4 enhanced GaN HEMT device knots of cascade Structure is identical with Fig. 3 circuit.
Full-bridge gate drive circuit 350 receives PWH the and PWL pulse-width signal from peripheral control unit in Fig. 4 a, generates 4 full-bridge switch signals with dead time protection, wherein first switch signal G0 is output to the enhanced GaN of the first cascade HEMT device 351, second switch signal G1 are output to the enhanced GaN HEMT device 352 of the second cascade, third switching signal G2 It is output to the enhanced GaN HEMT device 353 of third cascade, the 4th switching signal G3 is output to the fourth stage and joins enhanced GaN HEMT device 354.The drain D 0 and third of the first enhanced GaN HEMT device 351 of cascade cascade enhanced GaN HEMT device 353 drain D 2 is connected to high voltage bus VSS, the source S 0 and second of the first enhanced GaN HEMT device 351 of cascade simultaneously It cascades the drain D 1 of enhanced GaN HEMT device 352 while being connected to the first bridge arm output SW0, third cascades enhanced GaN The source S 2 and the fourth stage of HEMT device 353 join the drain D 3 of enhanced GaN HEMT device 354 while being connected to the second bridge arm SW1 is exported, the source S 1 and the fourth stage of the second enhanced GaN HEMT device 352 of cascade join enhanced GaN HEMT device 354 Source S 3 be connected to low-voltage bus bar GND simultaneously.
Fig. 4 b is a kind of way of realization of power module complete package structure of the present invention.The enhanced GaN HEMT of cascade Power module includes: package casing P00, metal lead wire frame, the first base island J00, the second base island J01, third base island J02, Four base island J03, the 5th base island J10, the first inner lead bonding area J06, the second inner lead bonding area J07, third inner lead bonding Area J08, the 4th inner lead bonding area J09, the first pin J21, second pin J22, third pin J23, the 4th pin J24, Five pin J25, the 6th pin J26, the first enhanced GaN HEMT device 351, second of cascade cascade enhanced GaN HEMT device Part 352, third cascade enhanced GaN HEMT device 353, the fourth stage joins enhanced GaN HEMT device 354, the driving of full-bridge grid Circuit 350 and binding line.
The inside connection relationship of the enhanced GaN HEMT power module of the cascade are as follows: the of full-bridge gate drive circuit 350 One input terminal connects the 5th pin J25 by the 19th binding line, and the second input terminal of full-bridge gate drive circuit 350 passes through second Ten binding lines connect the 6th pin J26；The first switch signal G0 output of full-bridge gate drive circuit 350 passes through the first binding line B1 It is connected to the left end of the first inner lead bonding area J06, the right end of the first inner lead bonding area J06 passes through the second binding line B2 connection To the grid end input point of the first enhanced GaN HEMT device 351 of cascade；The second switch signal G1 of full-bridge gate drive circuit 350 Output is connected to the left end of the second inner lead bonding area J07, the right end of the second inner lead bonding area J07 by third binding line B3 The grid end input point of the enhanced GaN HEMT device 352 of the second cascade is connected to by the 4th binding line B4；Full-bridge grid driving electricity The third switching signal G2 output on road 350 is connected to the left end of third inner lead bonding area J08, third by the 5th binding line B5 The right end of inner lead bonding area J08 is connected to the grid that third cascades enhanced GaN HEMT device 353 by the 6th binding line B6 Hold input point；The 4th switching signal G3 output of full-bridge gate drive circuit 350 is connected in the 4th by the 7th binding line B7 draws The right end of the left end of foot bonding region J09, the 4th inner lead bonding area J09 is connected to fourth stage connection enhancing by the 8th binding line B8 The grid end input point of type GaN HEMT device 354.
The drain D 0 of the first enhanced GaN HEMT device 351 of cascade is connected to third pin by the 9th binding line B9 The source S 0 of J23, the first enhanced GaN HEMT device 351 of cascade are connected to the first pin J21；The second enhanced GaN of cascade The drain D 1 of HEMT device 352 is connected to the first pin J21, the second enhanced GaN of cascade by the 11st binding line B11 The source S 1 of HEMT device 352 is connected to the 4th pin J24 by the 12nd binding line B12；Third cascades enhanced GaN The drain D 2 of HEMT device 353 is connected to third pin J23 by the 14th binding line B14, and third cascades enhanced GaN The source S 2 of HEMT device 353 is connected to second pin J22 by the 16th binding line B16；The fourth stage joins enhanced GaN The drain D 3 of HEMT device 354 is connected to second pin J22 by the 17th binding line B17, and the fourth stage joins enhanced GaN The source S 3 of HEMT device 354 is connected to the 4th pin J24；The output of first pin J21 be the first bridge arm export SW0, second The output of pin J22 is that the second bridge arm exports SW1, and the output of third pin J23 is high voltage bus VSS, and the 4th pin J24's is defeated It is out low-voltage bus bar GND, the input of the 5th pin J25 is the first driving signal PWH, and the input of the 6th pin J26 is the second drive Dynamic signal PHL.
Full-bridge is connected using the first binding line B1, the first inner lead bonding area J06 and the second binding line B2 in the present invention The grid of the first switch signal G0 output of gate drive circuit 350 and the first enhanced GaN HEMT device 351 of cascade, be in order to The use length for reducing binding line, to reduce the influence of parasitic inductance.Third pin J23 in the present invention, the 4th pin J24, The use of second inner lead bonding area J07, third inner lead bonding area J08 and the 4th inner lead bonding area J09, is completely used for subtracting The use length of few binding line, to minimize the influence of parasitic inductance.To realize optimal signal conformance, first Binding line B1, third binding line B3, the 5th binding line B5 and the 7th binding line B7 length must be stringent equal；Second binding line B2, the 4th binding line B4, the 6th binding line B6 and the 8th binding line B8 length must be stringent equal；First inner lead bonding area J06, the second inner lead bonding area J07, third inner lead bonding area J08 and the 4th inner lead bonding area J09 geometric dimension must Must be stringent equal, and use the material of high thermal conductivity.
Fig. 4 c is the way of realization of an enhanced GaN HEMT device of cascade of the invention, comprising: insulating cement, conductive weldering Material, high voltage depletion mode GaN transistor 10, low-voltage enhancement-mode transistor 11, voltage-regulating circuit 30, the first base island J00, first are led Electric substrate J31, the second electrically-conductive backing plate J32, third electrically-conductive backing plate J33, the tenth binding line.Wherein, the first electrically-conductive backing plate J31, The front that insulating cement is bonded in the first base island J00 is respectively adopted in the back side of two electrically-conductive backing plate J32 and third electrically-conductive backing plate J33；It is low The grid G 11 of pressure enhancement transistor 11 is connected to the front of the first electrically-conductive backing plate J31, and the front of the first electrically-conductive backing plate J31 is even Connect the grid G 0 of the enhanced GaN HEMT device of the first cascade；The drain D 11 of low-voltage enhancement-mode transistor 11 is connected to third and leads The front in the front of electric substrate J33, third electrically-conductive backing plate J33 is also connected to upper end and the high voltage depletion mode of voltage-regulating circuit 30 The source S 10 of transistor 10；The grid G 10 of high-pressure depletion transistor npn npn 10 is connected to front in the first base island J00, voltage tune The source S 0 of the lower end of whole circuit 30 and the first enhanced GaN HEMT device of cascade；The drain electrode of high-pressure depletion transistor npn npn 10 D10 is connected to the front of the second electrically-conductive backing plate J32；The source S 11 of low-voltage enhancement-mode transistor 11 is connected by the tenth binding line B10 It is connected to the front of the first base island J00.
Implementation of the present invention in Fig. 4 c, compared with the prior art in Fig. 2, improvements have at 2 points.First is that increasing voltage Adjustment circuit 30, for improving the reliability of high-pressure depletion transistor npn npn 10；Second is that high-pressure depletion transistor npn npn 10, low pressure are increased Strong type transistor 11 and voltage-regulating circuit 30 are electrically connected using flip chip bonding form, by high conductivity board transport telecommunications Number, to reduce the quantity and length of binding line, parasitic inductance is reduced, to improve switching frequency.Using high conductivity After lead frame carries out signal transmission, compared with the prior art in Fig. 2, binding line used in Fig. 4 c shortens very much, quantity Also it reduces, therefore posts body inductive effect and be greatly lowered.30 implementation of voltage-regulating circuit, can be using zener diode, simultaneously Join resistance or is realized using parallel resistance and zener diode series connection.
In implementation of the present invention described in Fig. 4 c, low-voltage enhancement-mode transistor 11 uses VDMOS device, using flip chip bonding Later, grid G 11 and drain D 11 are directly welded on the first front electrically-conductive backing plate J31 by conductive solder respectively and third is led The front electric substrate J33.GaN HEMT high-pressure depletion transistor npn npn 10 is planar device, and grid G 10 directly passes through conductive solder It is welded on the front the first base island J00, source S 10 is welded on the front third electrically-conductive backing plate J33, drain electrode by conductive solder D10 is welded on the second front electrically-conductive backing plate J32 by conductive solder.
As shown in figure 5, the packaging method of the above embodiment of the present invention the following steps are included:
Step 1, designs metal lead wire frame, and each unit should have 5 islands Chu Ji to be used to place grid driving chip and power device Part, die-attach area frame peripheral are furnished with pin, and the corresponding technological effect of this step is as shown in Figure 6 a.
Step 2 applies insulating cement in the first, second, third, fourth base island front corresponding position.It is with the first base island J00 First insulating cement Jh31, the second insulating cement Jh32 and third insulating cement Jh33 are respectively corresponded the first, second and third conduction by example Substrate front side corresponding position, with a thickness of 20 μm -40 μm, the corresponding technological effect of this step is as shown in Figure 6 b.
The reverse side of first, second and third electrically-conductive backing plate is passed through insulating cement respectively and is fixed on base island front by step 3.With For first base island J00, the reverse side of the first, second and third electrically-conductive backing plate passes through the first insulating cement Jh31, the second insulation respectively Glue Jh32 and third insulating cement Jh33 is fixed in the front the first base island J00.Second, third and the 4th Ji Dao are completed at the same time phase Same step two and step 3 operation, as fig. 6 c, it is viscous that all Ji Dao complete electrically-conductive backing plates to the corresponding technological effect of this step Patch.
Step 4, first, second, third and the 4th the front of electrically-conductive backing plate of Ji Dao need the position of interface unit electrode Set painting conductive solder.By taking the first base island J00 as an example, the drain electrode of the corresponding high-pressure depletion transistor npn npn 10 of the first conductive solder 501, the The grid of the corresponding low-voltage enhancement-mode transistor 11 of two conductive solders 511, the corresponding low-voltage enhancement-mode transistor of third conductive solder 531 11 drain electrode, the source electrode of the corresponding high-pressure depletion transistor npn npn 10 of the 4th conductive solder 530,532 corresponding voltage of the 6th conductive solder The upper end of adjustment circuit 30, with a thickness of 20 μm -40 μm.Second, third and the 4th Ji Dao are completed at the same time same operation, this step pair The technological effect answered is as shown in fig 6d.
Step 5 applies conductive solder in the first, second, third, fourth base island front corresponding position.With the first base island J00 For, in the grid of the corresponding high-pressure depletion transistor npn npn 10 of the 5th conductive solder 534,533 corresponding voltage tune of the 7th conductive solder The lower end of whole circuit 30；The 8th conductive solder is applied in the 5th base island front corresponding position simultaneously, with a thickness of 100 μm -110 μm, this The corresponding technological effect of step is as shown in fig 6e.
The counter electrode of step 6, high-pressure depletion transistor npn npn, low-voltage enhancement-mode transistor and voltage-regulating circuit 30 is logical It crosses conductive solder to be electrically connected with electrically-conductive backing plate front, GaN full-bridge grid driving chip 350 is attached to the 5th base island front.This step Rapid corresponding technological effect is as shown in Figure 6 f, completes device and pastes.
The device that previous step is completed is put into baking oven by step 7, baking process, and baking condition is joined with reference to common process Number, such as baking time 2.5-3.5 hours, temperature is set as 150-200 DEG C, after vacuumizing in baking oven, is filled with nitrogen as guarantor Protect gas, it is ensured that the oxygen content in baking oven is maintained at 100ppm or less.After the completion of baking, it need to be reduced to and connect to the temperature in case Nearly room temperature can just be taken out, and prevent chip residual temperature excessively high, and exposure will easily lead to GaN device electrode in air after taking out too early It is oxidized.
Step 8, bond technology are sent into press welder material track after the completion of baking.Set pressure, ultrasonic power, pressure welding Then the key parameters such as time allow machine to carry out routing according to the image recognition and cabling scenario debugged.After pressure welding is completed It must be detected, by test equipment, test chip thrust, whether lead pulling force can reach the range of requirement.This step Corresponding technological effect is as shown in figure 6g.
Step 9, packaging body injection molding are fixed.After the clear mould of injection molding machine, the packaging body frame that step 8 is completed is put into injection molding machine Mold in, select compatible with packaging body frame plastic packaging material, mold, formation Plastic Package shell injected after hot melt.It is fixed It is taken out after molding, is put into the heat ageing that heat ageing baking oven carries out 5-10 hour (different according to device parameter), sufficiently discharge modeling Intracorporal residual steam is sealed, the corresponding technological effect of this step is as shown in figure 6h to get encapsulating structure of the present invention.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (8)

1. enhanced GaN HEMT power module package structure, including package casing, metal lead wire frame and pin are cascaded, it is special Sign is, in package casing further include: the enhanced GaN HEMT device (351) of the first cascade, the second enhanced GaN HEMT of cascade Device (352), third cascade enhanced GaN HEMT device (353), the fourth stage joins enhanced GaN HEMT device (354), complete Bridge gate drive circuit (350)；The first input end of full-bridge gate drive circuit (350) connects the 5th pin by the 19th binding line (J25), the second input terminal of full-bridge gate drive circuit (350) connects the 6th pin (J26) by the 20th binding line；Full-bridge grid The first switch signal G0 of driving circuit (350), which is exported, is connected to the first inner lead bonding area (J06) by the first binding line The right end of left end, the first inner lead bonding area (J06) is connected to the enhanced GaN HEMT device of the first cascade by the second binding line The grid end input point of part (351)；The second switch signal G1 output of full-bridge gate drive circuit (350) is connected by third binding line Right end to the left end in the second inner lead bonding area (J07), the second inner lead bonding area (J07) is connected to by the 4th binding line The grid end input point of the second enhanced GaN HEMT device (352) of cascade；The third switching signal of full-bridge gate drive circuit (350) G2 exports the left end that third inner lead bonding area (J08) is connected to by the 5th binding line, third inner lead bonding area (J08) Right end is connected to the grid end input point that third cascades enhanced GaN HEMT device (353) by the 6th binding line；Full-bridge grid drive The 4th switching signal G3 output of dynamic circuit (350) is connected to the left side in the 4th inner lead bonding area (J09) by the 7th binding line End, the right end in the 4th inner lead bonding area (J09) are connected to the fourth stage by the 8th binding line and join enhanced GaN HEMT device (354) grid end input point；
The drain electrode (D0) of the first enhanced GaN HEMT device (351) of cascade is connected to third pin by the 9th binding line (J23), the source electrode (S0) of the first enhanced GaN HEMT device (351) of cascade is connected to the first pin (J21)；Second cascade increases The drain electrode (D1) of strong type GaN HEMT device (352) is connected to the first pin (J21) by the 11st binding line, and the second cascade increases The source electrode (S1) of strong type GaN HEMT device (352) is connected to the 4th pin (J24) by the 12nd binding line；Third cascade increases The drain electrode (D2) of strong type GaN HEMT device (353) is connected to third pin (J23) by the 14th binding line, and third cascade increases The source electrode (S2) of strong type GaN HEMT device (353) is connected to second pin (J22) by the 16th binding line；Fourth stage connection increases The drain electrode (D3) of strong type GaN HEMT device (354) is connected to second pin (J22) by the 17th binding line, and fourth stage connection increases The source electrode (S3) of strong type GaN HEMT device (354) is connected to the 4th pin (J24)；The output of first pin (J21) is first Bridge arm exports SW0, and the output of second pin (J22) is that the second bridge arm exports SW1, and the output of third pin (J23) is that high pressure is female Line VSS, the output of the 4th pin (J24) are low-voltage bus bar GND, and the input of the 5th pin (J25) is the first driving signal PWH, The input of 6th pin (J26) is the second driving signal PWL.
2. the enhanced GaN HEMT power module package structure of cascade according to claim 1, it is characterized in that: described first Cascade enhanced GaN HEMT device (351), the enhanced GaN HEMT device (352) of the second cascade, the enhanced GaN of third cascade The structure that HEMT device (353) joins enhanced GaN HEMT device (354) with the fourth stage is identical with implementation.
3. the enhanced GaN HEMT power module package structure of cascade according to claim 2, characterized in that described first Binding line, third binding line, the length of the 5th binding line and the 7th binding line are strictly equal；Second binding line, the 4th tie up The length of alignment, the 6th binding line and the 8th binding line is strictly equal；First inner lead bonding area (J06) draws in second The geometric dimension of foot bonding region (J07), third inner lead bonding area (J08) and the 4th inner lead bonding area (J09) is strictly equal.
4. the enhanced GaN HEMT power module package structure of cascade according to claim 2, it is characterized in that: each grade Join enhanced GaN HEMT device include: high-pressure depletion transistor npn npn, low-voltage enhancement-mode transistor, voltage-regulating circuit, Ji Dao, First electrically-conductive backing plate, the second electrically-conductive backing plate, third electrically-conductive backing plate, the first electrically-conductive backing plate, the second electrically-conductive backing plate and third conductive base The front that insulating cement is bonded in Ji Dao is respectively adopted in the back side of plate；The grid of low-voltage enhancement-mode transistor is connected to the first conductive base The front of plate, the front of the first electrically-conductive backing plate are connected to the grid of the affiliated enhanced GaN HEMT device of cascade；Low pressure is enhanced The drain electrode of transistor is connected to the front of third electrically-conductive backing plate, and the front of third electrically-conductive backing plate is also connected to voltage-regulating circuit The source electrode of upper end and high-pressure depletion transistor npn npn；The grid of high-pressure depletion transistor npn npn is connected to front in Ji Dao, voltage tune The source electrode of the lower end of whole circuit and the affiliated enhanced GaN HEMT device of cascade；The drain electrode of high-pressure depletion transistor npn npn is connected to The front of two electrically-conductive backing plates, the front of the second electrically-conductive backing plate are connected to the drain electrode of the affiliated enhanced GaN HEMT device of cascade；It is low The source electrode of pressure enhancement transistor is connected to the front of Ji Dao by binding line.
5. the enhanced GaN HEMT power module package structure of cascade according to claim 4, it is characterized in that: the low pressure Enhancement transistor uses VDMOS device, and after flip chip bonding, grid is directly welded at the first conduction by conductive solder Substrate front side, drain electrode are directly welded at third electrically-conductive backing plate front by conductive solder.
6. the enhanced GaN HEMT power module package structure of cascade according to claim 4, it is characterized in that: the high pressure Depletion mode transistor is planar device, and using flip-chip method, grid directly passes through conductive solder and is being welded on the first Ji Dao just Face, source electrode are welded on third electrically-conductive backing plate front by conductive solder, and drain electrode is welded on the second conduction by conductive solder Substrate front side.
7. the packaging method of the enhanced GaN HEMT power module package structure of cascade described in claim 4, which is characterized in that packet Include following steps:
Step 1, designs and produces metal lead wire frame, and the island each unit You Wuchuji is used to place grid driving chip and power device Part；
Step 2 applies insulating cement, the glue sites of each Ji Dao in the first, second, third and fourth base island front corresponding position Respectively correspond the position of its first, second and third electrically-conductive backing plate；
The reverse side of first, second and third electrically-conductive backing plate is fixed on base island front by insulating cement by step 3, until first, Second, third, the 4th Ji Dao be fully completed electrically-conductive backing plate stickup；
Step 4 needs the position of interface unit electrode to apply conductive solder, the first conductive weldering on the front of all electrically-conductive backing plates Expect the drain electrode of corresponding high-pressure depletion transistor npn npn, the second conductive solder corresponds to the grid of low-voltage enhancement-mode transistor, and third is conductive Solder corresponds to the drain electrode of low-voltage enhancement-mode transistor, and the 4th conductive solder corresponds to the source electrode of high-pressure depletion transistor npn npn, and the 6th leads The upper end of electric welding material corresponding voltage adjustment circuit；Each base island same operation；
Step 5 applies conductive solder in the first, second, third, fourth base island front corresponding position, and the 5th conductive solder is corresponding high Press the grid of depletion mode transistor, the lower end of the 7th conductive solder corresponding voltage adjustment circuit；It is applied simultaneously in the 5th base island front Solder layer；
Step 6, by the counter electrode of high-pressure depletion transistor npn npn, low-voltage enhancement-mode transistor and voltage-regulating circuit by leading Electric welding material is electrically connected with electrically-conductive backing plate front, and full-bridge gate drive circuit chip back is attached to the front of the 5th Ji Dao；
The device that previous step is completed is put into baking oven, is filled with nitrogen as protective gas, it is ensured that dried by step 7, baking process Oxygen content in case is maintained at 100ppm or less；After the completion of baking, it is reduced to room temperature to the temperature in baking oven, takes out device；
Step 8, bond technology are sent into press welder material track after the completion of baking, according to the image recognition and wiring side debugged Case carries out routing, and pressure welding is detected after completing；
Step 9, the packaging body frame qualified to step 8 detection are packaged body injection molding and fix.
8. packaging method according to claim 7, it is characterised in that: insulating cement and step 4 used in step 2 are made The thickness of conductive solder is 20 μm -40 μm, the used conductive solder of step 5 with a thickness of 100 μm -110 μm, and The temperature-resistance characteristic of two kinds of materials must be suitable.
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