CN110473910A - The horizontal dual pervasion field effect pipe of low gate charge - Google Patents
The horizontal dual pervasion field effect pipe of low gate charge Download PDFInfo
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- CN110473910A CN110473910A CN201910810132.3A CN201910810132A CN110473910A CN 110473910 A CN110473910 A CN 110473910A CN 201910810132 A CN201910810132 A CN 201910810132A CN 110473910 A CN110473910 A CN 110473910A
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- doped polysilicon
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- 230000005669 field effect Effects 0.000 title claims abstract description 26
- 230000009977 dual effect Effects 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The present invention provides a kind of horizontal dual pervasion field effect transistor of low gate charge, including the first conduction type doped substrate, first conduction type well region, first conduction type heavily doped region, the one the second conduction type heavily doped regions, second conduction type drift region, the two the second conduction type heavily doped regions, first oxide layer and the heavily doped polysilicon electrode wrapped up by the first oxide layer, second conduction type channel region upper surface is covered by gate oxide and heavily doped polysilicon grid, internal electrode of the present invention is connected with source electrode, gate leakage capacitance is decomposed into gate-source capacitance and drain source capacitance, substantially reduce the length of Miller platform, grid amount of charge needed for reducing unlatching, shorten the charging time, by adjusting buried structure, that is, internal electrode length, width, the depth adjustable charging time, and then it adjusts between grid charge and conducting resistance Equilibrium relation reduces drift region electric field since internal electrode connects low potential, to slow down hot carrier's effect.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of horizontal dual pervasion field effect crystal of low gate charge
Pipe.
Background technique
In recent years, in order to meet the needs of integrated circuit, power device technology constantly advances, with lateral double diffusion field
Effect Guan Wei represent can integrated power device there is increasingly consequence, meanwhile, as device operating frequencies constantly mention
Height, influence more important of the grid charge for device, and have become the important indicator of assessment device switch performance.Grid charge
It is the important parameter for measuring power MOSFET dynamic characteristic, which directly affects the overall performance of device, in power MOSFET
In device development, production and use process, to the grid charge as key parameter, more stringent requirements are proposed.In order to adapt to increasingly
The market demand of enhancing, it is increasing to the research of low gate charge power MOSFET device structure.It is added and covers in the body of drift region
Shielded gate structures are buried, and the structure is connected with source electrode, significantly reduce the charging time of grid charge.
Summary of the invention
It is connected the purpose of the present invention is in the drift region of horizontal dual pervasion field effect pipe, increasing a current potential with source electrode
A shielding construction i.e. internal electrode is buried, this electrode can shield most of gate leakage capacitance, and then make grid charge and charging
Time decline.
For achieving the above object, technical solution of the present invention is as follows:
A kind of horizontal dual pervasion field effect transistor of low gate charge, including the first conduction type doped substrate 11, first
11 the first conduction type of upper left well region 12 of conduction type doped substrate, positioned at 12 upper left of the first conduction type well region
First conduction type heavily doped region 14, the one the second conduction type heavy doping positioned at the right side of the first conduction type heavily doped region 14
Area 15 is located at the second conduction type drift region positioned at the second conduction type drift region 13 on 12 right side of the first conduction type well region
The two the second conduction type heavily doped regions 18 in 13 upper right side, the first oxide layer inside the second conduction type drift region 13
17 with the heavily doped polysilicon electrode 16 that is wrapped up by the first oxide layer 17, the second conduction type channel region upper surface is by gate oxide
110 cover with heavily doped polysilicon grid 19.
It is preferred that heavily doped polysilicon electrode 16 is more for being connected with source electrode of being separated from each other in the height direction
Layer structure, respectively the first heavily doped polysilicon electrode 1, second heavily doped polysilicon electrode 2 ... the n-th heavily doped polysilicon electricity
Pole n.
It is preferred that heavily doped polysilicon electrode 16 is the multilayer being connected with source electrode being separated from each other in width direction
Structure, respectively the first heavily doped polysilicon electrode 1, second heavily doped polysilicon electrode 2 ... the n-th heavily doped polysilicon electrode
n。
It is preferred that the current potential of heavily doped polysilicon electrode 16 draws in short transverse and is connected with source electrode.
It is preferred that in the punching of 16 surface of heavily doped polysilicon electrode or cutting to draw electricity in the height direction
Position, and be connected with source electrode.
It is preferred that the first conduction type is p-type, the second conduction type is N-type；Or first conduction type be N
Type, the second conduction type are p-type.
It is preferred that the horizontal dual pervasion field effect pipe structure of the low gate charge is plane or groove profile.
The invention has the benefit that
1, internal electrode is connected with source electrode, and gate leakage capacitance is decomposed into gate-source capacitance and drain source capacitance, substantially reduces close
The length for strangling platform, grid amount of charge, shortens the charging time needed for reducing unlatching.
2, it by adjusting buried structure, that is, internal electrode length, width, depth adjustable charging time, and then adjusts
Equilibrium relation between grid charge and conducting resistance.
3, since internal electrode connects low potential, drift region electric field is reduced, to slow down hot carrier's effect.
4, relevant parameter of the present invention can be adjusted as needed, considerably increase the flexibility of device design.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the horizontal dual pervasion field effect pipe of low gate charge of the invention.
Fig. 2 is horizontal dual pervasion field effect tube device structural schematic diagram in the prior art.
Fig. 3 is that grid charge tests circuit；
Fig. 4 is a kind of horizontal dual pervasion field effect pipe of low gate charge of the invention and the grid charge curve pair of parametric device
Compare schematic diagram；
Fig. 5 is the schematic diagram of the embodiment of the present invention 1；
Fig. 6 is the schematic diagram of the embodiment of the present invention 2.
Wherein, 1 is the first heavily doped polysilicon electrode, and 2 be the second heavily doped polysilicon electrode, and n is the n-th heavy doping polycrystalline
Silicon electrode；11 be the first conductivity type substrate, and 12 be the first conduction type well region, and 13 be the second conduction type drift region, and 14 are
First conduction type heavily doped region, 15 be the one the second conduction type heavily doped regions, and 16 be heavily doped polysilicon electrode, and 17 be the
One oxide layer, 18 be the two the second conduction type heavily doped regions, and 19 attach most importance to doped polysilicon gate, and 110 be gate oxide；
21 be the first conductivity type substrate, and 22 be the first conduction type well region, and 23 be the second conduction type drift region, and 24 are
First conduction type heavily doped region, 25 be the one the second conduction type heavily doped regions, and 28 be the two the second conduction type heavy doping
Area, 29 attach most importance to doped polysilicon gate, and 210 be gate oxide.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
As shown in Figure 1, a kind of horizontal dual pervasion field effect pipe of low gate charge, including the first conduction type doped substrate
11,11 the first conduction type of upper left well region 12 of the first conduction type doped substrate is located on the first conduction type well region 12
The first conduction type heavily doped region 14 in side left side, the one the second conductive-types positioned at the right side of the first conduction type heavily doped region 14
Type heavily doped region 15 is located at the second conductive-type positioned at the second conduction type drift region 13 on 12 right side of the first conduction type well region
The two the second conduction type heavily doped regions 18 in 13 upper right side of type drift region, inside the second conduction type drift region 13
One oxide layer 17 and the heavily doped polysilicon electrode 16 that is wrapped up by the first oxide layer 17, the second conduction type channel region upper surface quilt
Gate oxide 110 and heavily doped polysilicon grid 19 cover.
Preferably, the current potential of heavily doped polysilicon electrode 16 draws in short transverse and is connected with source electrode.
Preferably, in the punching of 16 surface of heavily doped polysilicon electrode or cutting to extraction potential in the height direction, and
It is connected with source electrode.
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second
Conduction type is p-type.
Preferably, the horizontal dual pervasion field effect pipe structure of the low gate charge is plane or groove profile.
The length of intracorporal heavily doped polysilicon electrode 16, width can be adjusted according to the needs with height.
The operation principle of the present invention is that:
A kind of horizontal dual pervasion field effect pipe of low gate charge, the Buried body electrode in drift region, the electrode and source
Extremely it is connected, constitutes shielded layer, gate leakage capacitance is decomposed into gate-source capacitance and gate leakage capacitance, greatly reduces grid leak in charging process
The influence of capacitor shortens Miller platform, and then shortens the charging time.Moreover, the transverse direction of a kind of low gate charge
The burial shielding construction namely internal electrode of double diffused field effect pipe connect low potential, thus reduce drift region electric field, so as to
To slow down the hot carrier's effect in drift region.
By MEDICI simulation software to the horizontal dual pervasion field effect pipe of a kind of low gate charge as shown in Figure 1 and identical
Under the conditions of Fig. 2 shown in the lateral double-diffused transistor of tradition carry out process simulation and compare.
Fig. 4 is Fig. 2 institute under a kind of horizontal dual pervasion field effect pipe of low gate charge provided by the invention and the same terms
Show the Vg-t curve comparison schematic diagram of traditional horizontal dual pervasion field effect pipe.Figure 4, it can be seen that Miller platform is obviously shortened,
Total charging time decline is obvious.
Embodiment 2
As shown in figure 5, the difference of the present embodiment and embodiment 1 is: heavily doped polysilicon electrode 16 is in the height direction
For the multilayered structure being connected with source electrode being separated from each other, respectively the first heavily doped polysilicon electrode 1, the second heavily doped polysilicon
Electrode 2 ... the n-th heavily doped polysilicon electrode n.To reach better shield effectiveness.
Embodiment 3
Fig. 6 is the top view with the lateral double-diffused transistor for burying shielding construction of the present embodiment.The present embodiment and
The difference of embodiment 1 is: heavily doped polysilicon electrode 16 is the multilayer knot being connected with source electrode being separated from each other in width direction
Structure, respectively the first heavily doped polysilicon electrode 1, second heavily doped polysilicon electrode 2 ... the n-th heavily doped polysilicon electrode n,
To reach better shield effectiveness.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (7)
1. a kind of horizontal dual pervasion field effect transistor of low gate charge, it is characterised in that: adulterate and serve as a contrast including the first conduction type
Bottom (11), first conduction type doped substrate (11) upper left the first conduction type well region (12) are located at the first conduction type
The first conduction type heavily doped region (14) of well region (12) upper left is located on the right side of the first conduction type heavily doped region (14)
The one the second conduction type heavily doped regions (15) are located at the second conduction type drift region on the right side of the first conduction type well region (12)
(13), positioned at the two the second conduction type heavily doped regions (18) in second conduction type drift region (13) upper right side, it is located at second
Internal the first oxide layer (17) in conduction type drift region (13) and the heavily doped polysilicon electricity wrapped up by the first oxide layer (17)
Pole (16), the second conduction type channel region upper surface are covered by gate oxide (110) and heavily doped polysilicon grid (19).
2. a kind of horizontal dual pervasion field effect pipe of low gate charge according to claim 1, it is characterised in that: heavy doping is more
Crystal silicon electrode (16) is in the height direction the multilayered structure being connected with source electrode being separated from each other, respectively the first heavy doping polycrystalline
Silicon electrode (1), second the n-th heavily doped polysilicon electrode of heavily doped polysilicon electrode (2) ... n.
3. a kind of horizontal dual pervasion field effect pipe of low gate charge according to claim 1, it is characterised in that: heavy doping is more
Crystal silicon electrode (16) is the multilayered structure being connected with source electrode being separated from each other, respectively the first heavily doped polysilicon in width direction
Electrode (1), second the n-th heavily doped polysilicon electrode of heavily doped polysilicon electrode (2) ... n.
4. a kind of horizontal dual pervasion field effect pipe of low gate charge according to claim 1, it is characterised in that: heavy doping is more
The current potential of crystal silicon electrode (16) draws in short transverse and is connected with source electrode.
5. a kind of horizontal dual pervasion field effect pipe of low gate charge according to claim 4, it is characterised in that: in heavy doping
The punching of polysilicon electrode (16) surface or cutting are connected to extraction potential in the height direction with source electrode.
6. according to claim 1 to a kind of horizontal dual pervasion field effect pipe of low gate charge described in 5 any one, feature exists
In: the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, the second conduction type be P
Type.
7. a kind of horizontal dual pervasion field effect pipe of low gate charge according to claim 1, it is characterised in that: the low grid
The horizontal dual pervasion field effect pipe structure of charge is plane or groove profile.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910810132.3A CN110473910A (en) | 2019-08-29 | 2019-08-29 | The horizontal dual pervasion field effect pipe of low gate charge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910810132.3A CN110473910A (en) | 2019-08-29 | 2019-08-29 | The horizontal dual pervasion field effect pipe of low gate charge |
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| CN110473910A true CN110473910A (en) | 2019-11-19 |
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ID=68514136
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| CN201910810132.3A Pending CN110473910A (en) | 2019-08-29 | 2019-08-29 | The horizontal dual pervasion field effect pipe of low gate charge |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070284659A1 (en) * | 2003-05-06 | 2007-12-13 | Abadeer Wagdi W | Method of forming high voltage n-ldmos transistors having shallow trench isolation region with drain extensions |
| CN102169903A (en) * | 2011-03-22 | 2011-08-31 | 成都芯源系统有限公司 | LDMOS device |
| CN107564965A (en) * | 2017-08-22 | 2018-01-09 | 电子科技大学 | A kind of lateral direction bilateral diffusion MOS device |
-
2019
- 2019-08-29 CN CN201910810132.3A patent/CN110473910A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070284659A1 (en) * | 2003-05-06 | 2007-12-13 | Abadeer Wagdi W | Method of forming high voltage n-ldmos transistors having shallow trench isolation region with drain extensions |
| CN102169903A (en) * | 2011-03-22 | 2011-08-31 | 成都芯源系统有限公司 | LDMOS device |
| CN107564965A (en) * | 2017-08-22 | 2018-01-09 | 电子科技大学 | A kind of lateral direction bilateral diffusion MOS device |
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Application publication date: 20191119 |
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