CN110473491A - Source electrode driver and its method - Google Patents
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- CN110473491A CN110473491A CN201910844244.0A CN201910844244A CN110473491A CN 110473491 A CN110473491 A CN 110473491A CN 201910844244 A CN201910844244 A CN 201910844244A CN 110473491 A CN110473491 A CN 110473491A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
A kind of source electrode driver and its method, wherein source electrode driver has a D/A conversion circuit and a line latch circuit.Line latch circuit couples D/A conversion circuit.D/A conversion circuit is used to receive the data-signal with multiple numerical datas and converts multiple numerical datas into multiple analog drive signals.Line latch circuit exports multiple analog drive signals for the multiple analog drive signals of latch and according to the rising edge of a clock signal.
Description
Technical field
This disclosure relates to a kind of display actuation techniques, especially a kind of source electrode driver and its method.
Background technique
Display device has been widely used in TV (TV), lithographic plate computer (tablet PC), mobile phone (mobile at present
Phone), the various electronic devices such as wisdom wrist-watch (smart watch) and intelligent appliance (smart home appliances).
Display device has the function of showing image.General display device includes source electrode driver (source
) and gate drivers (gate driver) driver.Wherein, the driving method of display device is by source electrode driver and grid
Driver transmits signal to drive the pixel in display device.When the pixel in display device is driven, display device
Show corresponding image.
However, the number of pixels of display device and frame per second (frame per second, FPS) are gradually increased now.Signal
But the driving framework being limited in source electrode driver, signal may cause the display efficiency of display device because of driving delay
Decline.
Summary of the invention
In view of above-mentioned, the disclosure proposes a kind of source electrode driver.Source electrode driver include a D/A conversion circuit and
One line latch circuit.Line latch circuit couples D/A conversion circuit.In this, D/A conversion circuit has for receiving
One data-signal of multiple numerical datas simultaneously converts multiple numerical datas into multiple analog drive signals.Line latch circuit is for fastening with a bolt or latch
It locks multiple analog drive signals and exports multiple analog drive signals according to the rising edge of a clock signal.
The disclosure discloses a kind of source driving method in another embodiment.The method includes: to receive to have multiple numbers
One data-signal of data；Multiple numerical datas are converted into multiple analog drive signals；And it is more according to a clock signal latch
A analog drive signal.
In conclusion advanced row digital simulation is converted into program, then holds according to the source electrode driver and its method of the disclosure
Row latch output program, thus signal can be made not postpone during source drive, the display effect of display device is maintained whereby
Energy.
Detailed description of the invention
Fig. 1 is the schematic diagram according to the source electrode driver of one embodiment of the disclosure.
Fig. 2 is the signal graph according to the source drive of one embodiment of the disclosure.
Fig. 3 is the schematic diagram according to the source electrode driver of another embodiment of the disclosure.
Fig. 4 is the schematic diagram according to the D/A conversion circuit of one embodiment of the disclosure.
Fig. 5 is the schematic diagram according to the numerical data transmission path of one embodiment of the disclosure.
Fig. 6 is the signal graph according to the numerical data order of one embodiment of the disclosure.
Fig. 7 is the flow chart according to the source driving method of one embodiment of the disclosure.
Description of symbols:
10 source electrode driver, 20 sequence controller
100 data interface circuits 200 are displaced buffering circuit
300 data buffering circuit, 310 data keep in sub-circuit
400 position quasi displacement circuit, 500 D/A conversion circuit
510 input terminal, 520 output end
530 switch terminals, 540 first switch circuit
550 second switch circuits 600 convert latch circuit
700 line latch circuit, 800 output buffer
D1 data-signal D2 clock signal
D3 clock signal W square wave
WRRising edge WFFalling edge
Y numerical data Y1~Y960 numerical data
Y ' analog drive signal M transistor
Data S10~S18 step of BK horizontal sweep interregnum
When T1 square wave away from
T2 " finishing touch data from data interface circuit receive " is to the time interval of " rising edge of clock signal "
The corresponding passing time of T3 shorter transmission path
The corresponding passing time of the longer transmission path of T4
T5 " the first stroke of data-signal numerical data starts " to " the finishing touch numerical data of data-signal terminates "
Between time interval
T6 " terminating from the finishing touch numerical data of data-signal " is to " the first stroke numerical data of next data-signal is opened
Time interval between beginning "
Specific embodiment
Fig. 1 is please referred to, in one embodiment, source electrode driver 10 includes a data interface circuit (data interface)
100,300, one number of displacement buffering circuit (shift register) 200, one data buffering circuit (data register)
Analog conversion circuit (digital to analog converter, DAC) 500, one line latch circuit (line latch) 700
An and output buffer (output buffer) 800.
Referring to Fig. 7, according to an embodiment, source electrode driver 10 is used to receive one with multiple numerical data Y in this
Data-signal D1 (step S10), and multiple numerical data Y are converted into multiple analog drive signal Y ' (step S12) and foundation
The multiple analog drive signal Y ' (step S14) of clock signal D2 latch.And in one embodiment, source electrode driver 10 buffers latch
Rear multiple analog drive signal Y ' (step S16) and according to multiple analog drive signal Y ' after clock signal D2 output buffering
(step S18).
In an embodiment, preceding data signals D1 receives in source electrode driver 10, the process converting, export sequentially is passed through
Data interface circuit 100, data buffering circuit 300, D/A conversion circuit 500, line latch circuit 700 and output buffering electricity
Road 800.In other words, it in this, is displaced buffering circuit 200 and data buffering circuit 300 Ou Jie not data interface circuit 100.Number
Displacement buffering circuit 200 is coupled according to buffering circuit 300.D/A conversion circuit 500 couples data buffering circuit 300.Line door bolt
Lock circuit 700 couples D/A conversion circuit 500.Output buffer 800 couples line latch circuit 700.
In an embodiment, data interface circuit 100 is for handling data-signal D1 and exporting clock signal D3.It is specific and
Speech, data interface circuit 100 is the receiving end of source electrode driver 10, therefore data interface circuit 100 is for receiving with multiple
The data-signal D1 of numerical data Y.Wherein, multiple numerical data Y are in data-signal D1 with arranged in series.Data-interface
Circuit 100 can convert multiple numerical data Y that multiple numerical data Y of arranged in series arrange into parallel form.Data connect
Mouthful circuit 100 exports the data-signal D1 of multiple numerical data Y with parallel form arrangement to data buffering circuit 300 again.
And data buffering circuit 300 is used for according to clock signal D3 temporal data signal D1.In an embodiment, it is displaced buffering circuit
200 according to clock signal D3 it is periodical generate one in proper order signal (not shown) to data buffering circuit 300.Displacement is temporary
Circuit 200 according to signal control data buffering circuit 300 in proper order, believe by the temporal data in a manner of one stroke count digital data Y of primary sample
Number D1.According to an embodiment, sequence controller 20 is used for output timing signal D2, it is, sequence controller 20 passes through timing
Signal D2 controls the action sequence in source electrode driver 10.
In an embodiment, D/A conversion circuit 500 is used to receive the data-signal D1 with multiple numerical data Y,
And multiple numerical data Y can be converted into multiple analog drive signal Y ', and export multiple analog drive signal Y ' to line latch
Circuit 700.In an embodiment, D/A conversion circuit 500 is to receive data-signal D1 by data buffering circuit 300,
Namely one stroke count digital data Y of the every reception of data buffering circuit 300, data buffering circuit 300 export stroke count digital data Y extremely
D/A conversion circuit 500.
According to an embodiment, line latch circuit 700 is used for the multiple analog drive signal Y ' of latch, and according to clock signal D2
Rising edge WRExport multiple analog drive signal Y '.Specifically, working as the rising edge W of clock signal D2RWhen starting to be enabled,
Line latch circuit 700 can multiple analog drive signals of the latch from the output of D/A conversion circuit 500 to line latch circuit 700
Y'.Wherein, the process of 700 latch analog drive signal Y ' of line latch circuit, line latch circuit 700 only can latch same group of data
Analog drive signal Y ' in signal D1.Therefore the data that the data-signal D1 of 700 latch of line latch circuit will not be organized by other
Signal D1 covering.When line latch circuit 700 receives the rising edge W of clock signal D2RWhen, line latch circuit 700 is exported by line
Multiple analog drive signal Y ' (that is, one group of data-signal D1) of 700 latch of latch circuit.When line latch circuit 700 has exported
After one group of data-signal D1, line latch circuit 700 restarts the lower one group of data-signal D1 of latch again.
In an embodiment, output buffer 800 buffers multiple analog drive signal Y ' after latch and believes according to timing
Multiple analog drive signal Y ' after number D2 output buffering.Specifically, what the reception of output buffer 800 was exported from line latch
Multiple analog drive signal Y ', and buffer multiple analog drive signal Y '.When output buffer 800 receives clock signal D2's
Falling edge WFWhen, output buffer 800 exports the multiple analog drive signal Y ' buffered by output buffer 800.It is logical
Multiple analog drive signal Y ' that normal output buffer 800 exports each time are one group of data-signal D1.
In one embodiment, source electrode driver 10 further includes 400 (level of a level (level) shift circuit
shifter).Position quasi displacement circuit 400 is coupled between data buffering circuit 300 and D/A conversion circuit 500.Level is moved
Position circuit 400 is used to for the data-signal D1 that suitable data buffering circuit 300 operates being converted into be suitble to D/A conversion circuit
The data-signal D1 of 500 operations.The voltage for generally being suitable for the data-signal D1 of the operation of D/A conversion circuit 500 is higher than data
The voltage of the data-signal D1 of buffering circuit 300.
In one embodiment, source electrode driver 10 more couples time schedule controller (timing controller, TCON) 20
To receive the data-signal D1 and clock signal D2 of the output of sequence controller 20.Sequence controller 20 is controlled by clock signal D2
Action sequence in source electrode driver 10.Also, a video signal can be converted into 10 energy of source electrode driver by sequence controller 20
The data-signal D1 used.Sequence controller 20 keeps 10 output driving of source electrode driver aobvious by outputting data signals D1 again
The analog drive signal Y ' of showing device.According to an embodiment, sequence controller 20 is for exporting clock signal D3 to data-interface
Circuit 100.It is, sequence controller 20 is temporary electric to being displaced to export clock signal D3 by data interface circuit 100
Road 200.
Referring to figure 2., to clearly illustrate, in some embodiments, the numerical data Y of different pens is respectively with Y1 to Y960 mark
Show.In some embodiments, data-signal D1 can be respectively with grayscale L0 to L255 mark.
It please continue referring to Fig. 2, in an embodiment, one group of data-signal D1 has multiple numerical data Y and a horizontal sweep
The data BK of interregnum (horizontal blanking period).When data-signal D1 is during source drive,
Multiple numerical data Y can be converted into multiple analog drive signal Y '.Therefore, the process of source drive is first to receive one group with more
The data-signal D1 of a numerical data Y, then export one group of data-signal D1 with multiple analog drive signal Y '.Clock signal
D2 is a periodic square wave W, and square wave W has a rising edge WRAn and falling edge WF, therefore clock signal D2 has rising
Edge WRAnd falling edge WF.Wherein, the rising edge W of clock signal D2RAnd falling edge WFIt is acted respectively as control source electrode driver 10
Signal.The corresponding one group of data-signal D1 of a square wave W of usual clock signal D2, that is, the rising edge W of a square wave WR
And falling edge WFIt controls source electrode driver 10 and handles one group of data-signal D1.
According to an embodiment, display device is output display image to be carried out by multiple horizontal scanning lines, and show dress
Set once one horizontal scanning line of output.Wherein, multiple numerical data Y1 to Y960 in one group of data-signal D1 are one
The signal that horizontal scanning line need to export.The data BK of horizontal sweep interregnum is adjacent two water exported as display device
Buffering signals between scan lines.And in one group of data-signal D1, the data BK of horizontal sweep interregnum is set to
Before multiple numerical data Y1 to Y960.According to an embodiment, in one group of data-signal D1, the number of horizontal sweep interregnum
It is set to after multiple numerical data Y1 to Y960 according to BK.
According in an embodiment, data interface circuit 100 is used to differentiate multiple numerical data Y1 in data-signal D1 extremely
The data BK of Y960 and horizontal sweep interregnum.In other words, data interface circuit 100, which can differentiate, need to export in level
Buffering signals between the digital signal Y of scan line and adjacent two horizontal scanning lines.
Referring to figure 3., in one embodiment, D/A conversion circuit 500 and line latch circuit 700 are integrated into one and turn
Change latch circuit 600.Specifically, conversion latch circuit 600 has D/A conversion circuit 500 and line latch circuit 700
Function.Conversion latch circuit 600 is used to receive the data-signal D1 with multiple numerical data Y, and can convert multiple numbers
Digital data Y is at multiple analog drive signal Y ' and the multiple analog drive signal Y ' of latch.And convert 600 foundation of latch circuit
The rising edge W of clock signal D2RExport multiple analog drive signal Y '.
It please continue refering to Fig. 3, in an embodiment, output buffer 800 is coupled to conversion latch circuit 600.Output buffering
Circuit 800 can be according to the falling edge W of clock signal D2FExport corresponding multiple analog drive signal Y '.
Referring to Fig. 4, in one embodiment, set of number analog conversion circuit 500 includes multiple switch end 530, multiple
Input terminal 510, an output end 520 and multiple transistor M.Multiple input terminals 510 are the multiple transistor M arranged by multi-level
It is coupled to output end 520.Each switch terminals 530 then respectively correspond transistor M (such as the R in figure of a stratumA0 to RA7、RA0’
To RA7’、RB0 to RB7、RB0 ' to RB7').When D/A conversion circuit 500 is run, input terminal 510 is in a manner of one-to-one
Corresponding to output end 520.Namely at most only one input terminal 510 and output end 520 are the states be connected, remaining input
End 510 is to disconnect with output end 520.And switch terminals 530 be controlled in a manner of dichotomy each stratum transistor M (for example,
RA0 and RAOnly one can allow corresponding transistor M to be connected among 0 '), thus only one input terminal 510 and output end 520 it
Between each transistor M be connected, must there is at least one transistor M to be between remaining input terminal 510 and output end 520
Open circuit.When between input terminal 510 and output end 520 to be connected, input terminal 510 of the D/A conversion circuit 500 from conducting
Input digital data Y, and corresponding analog drive signal Y ' is exported from output end 520.Wherein, analog conversion circuit 500 will count
Digital data Y is converted into analog drive signal Y '.In an embodiment, each input terminal 510 is respectively used to transmit different groups of number
It is believed that number D1 (such as L0 to L255 in figure).
According to an embodiment, as shown in figure 4, source electrode driver 10 includes two groups of D/A conversion circuits 500.Digital mould
Quasi- conversion circuit 500 further includes a first switch circuit 540 and a second switch circuit 550.Every group has multiple numerical data Y
Data-signal D1 have corresponding input terminal 510 in each group D/A conversion circuit 500.And each group digital-to-analogue conversion electricity
Switch terminals 530 in road 500 are all coupled to first switch circuit 540.And the output end in each group D/A conversion circuit 500
520 coupling second switch circuits 550.Wherein, control wherein set of number simulation turn of the first switch circuit 540 for selectivity
The switch terminals 530 in circuit 500 are changed, one of input terminal 510 and output end in this group of D/A conversion circuit 500 are made
520 conductings.The output end 520 of 550 selectivity of second switch circuit controlled in wherein set of number analog conversion circuit 500,
Make the output end 520 controlled output that there is the data-signal D1 of multiple analog drive signal Y '.
Continue refering to Fig. 4, in one embodiment, when in the control of first switch circuit 540 wherein one group of conversion latch circuit 600
Switch terminals 530 input terminal 510 and output end 520 is connected, conversion latch circuit 600 converts multiple numerical data Y at multiple
Analog drive signal Y ', and the multiple analog drive signal Y ' of latch.Wherein one group of conversion latch is electric for the control of second switch circuit 550
Output end 520 in road 600 makes the output end controlled 520 export the multiple analog drive signal Y ' being latched.
Referring to Fig. 1, Fig. 5 and Fig. 6, according to some embodiments, during source drive, receive with multiple
The program of the data-signal D1 of numerical data Y is the multiple numerical data Y of path length decision according to multiple numerical data Y transmitting
Reception order.Specifically, data buffering circuit 300 includes that multiple data keep in sub-circuit 310.When source electrode driver 10 exists
When handling one group of data-signal D1, each data keep in sub-circuit 310 and respectively correspond one stroke count digital data Y of processing.Therefore, digital
Data Y can be variant because of different numerical data Y from the distance that data interface circuit 100 is transferred to line latch circuit 700.
It is first received, is received after the closer numerical data Y in the path of transmitting, source drive by the farther away numerical data Y in the path of transmitting
Device 10 can be reduced the difference of the passing time of each numerical data Y.Therefore the present embodiment be avoided that source drive process because
The output Time Inconsistency of each analog drive signal Y ' and the voltage output rate of change for causing each analog drive signal Y '
(slew rate) different situations.What the voltage output rate of change referred to is the slope of analog drive signal Y '.It please be same
When referring to Fig. 3, Fig. 5 and Fig. 6, according to an embodiment, numerical data Y is transferred to conversion latch circuit from data interface circuit 100
600 distance can be variant because of different numerical data Y.It is first received, is passed by the farther away numerical data Y in the path of transmitting
It is received after the closer numerical data Y in the path passed, source electrode driver 10 can be reduced the difference of the passing time of each numerical data Y
It is different.
It please continue refering to Fig. 5 and Fig. 6, it is according to multiple numbers that receiving, which has the program of the data-signal D1 of multiple numerical data Y,
The path length of digital data Y transmitting determines that an embodiment of the reception order of multiple numerical data Y is as follows.One group of data letter
Number D1 includes numerical data Y1 to numerical data Y960.Numerical data Y1, Y960 has shorter transmission path, numerical data
Y480, Y481 have longer transmission path.Therefore data interface circuit 100 first receives numerical data Y480, Y481, and number
According to reception numerical data Y1, Y960 after interface circuit 100.Wherein, the corresponding passing time T3 of shorter transmission path be less than compared with
The corresponding passing time T4 of long transmission path.
In one embodiment, the rising edge W of clock signal D2RThe time point of corresponding multiple analog drive signal Y ' latches
It is not later than the rising edge W of aforementioned clock signal D2R.Also that is, the time of the multiple analog drive signal Y ' of latch need to believe by timing
The rising edge W of number D2RDuring complete.Specifically, the rising edge W of clock signal D2RFor driving line latch circuit 700 defeated
Multiple analog drive signal Y ' out, therefore line latch circuit 700 must be in the rising edge W for receiving clock signal D2RIt completes before
Latch aforementioned analog driving signal Y ' (that is, one group of data-signal D1).
Referring to Fig. 2, in an embodiment, the rising edge W of the same square wave W in clock signal D2RWith falling edge WFBetween
Away from T1 when time interval is a square wave.Have to be larger than that " line latch circuit 700 exports multiple analog-drivens letters when aforementioned square wave away from T1
Number Y ' " is to the time interval of " output buffer 800 receives multiple analog drive signal Y ' above-mentioned ".Therefore, when output is slow
Rush falling edge W of the circuit 800 according to square wave WFWhen exporting multiple analog drive signal Y ' above-mentioned, multiple analog-drivens above-mentioned
Signal Y ' has been transferred to output buffer 800.
In some embodiments, source electrode driver 10 and its method are able to satisfy the rising edge W of clock signal D2RIt is corresponding multiple
The time point of analog drive signal Y ' latch is not later than the rising edge W of aforementioned clock signal D2R, therefore it is avoided that source drive
Process causes the voltage output of each analog drive signal Y ' because of the output Time Inconsistency of each analog drive signal Y '
The different situation of rate of change.
Referring to Fig. 6, reducing " the first stroke of data-signal D1 numerical data Y starts " according to an embodiment and arriving " data
The finishing touch numerical data Y of signal D1 terminates " between time interval T5, to meet the rising edge W of clock signal D2RIt is corresponding
Time points of multiple analog drive signal Y ' latches be not later than the rising edge W of aforementioned clock signal D2R。
In an embodiment, by improving the transmission rate of data-signal D1 among source drive, to meet clock signal D2
Rising edge WRThe time point of corresponding multiple analog drive signal Y ' latches is not later than the rising edge W of aforementioned clock signal D2R。
In one embodiment, source electrode driver 10 is set in a display device (not shown), and source electrode driver 10 is used for
Drive the pixel in display device to show image.
In one embodiment, when the resolution ratio of display device be " 3840*2160 ", then represent the pixel number of display device as
3840 column (row) imply that the scan line of display device is 3840, and data line has 2160.Each pixel includes 3 sons
Pixel.At least one or more source electrode drivers 10 can be used in display device, and (this embodiment uses 12 with display device
Source electrode driver 10 is illustrated), wherein each source electrode driver 10 using two to (pair) type transmission mode, therefore every source
Driver 10 can all handle two packages simultaneously.Front end transmission time is (that is, source electrode driver handles one group of data-signal
In, " the first stroke numerical data Y is received from data interface circuit 100 " is to " finishing touch analog drive signal Y ' output to line is fastened with a bolt or latch
Time interval between lock circuit 700 ") it is 300 nanoseconds (ns).In the present embodiment, referred to as a stroke count digital data Y and corresponding one
Analog drive signal Y ' is a data." finishing touch data Y from data interface circuit 100 receive " is to " clock signal D2
Rising edge WR" time interval T2 be 181.25ns.The bit number of one data and a package is all 9 bits (bit).It is former
Beginning transmission rate can be as the speed rates of 1.44 gigabits (Gbps) per second.
It holds, therefore the package number of a processing needed for a horizontal scanning line of source electrode driver 10 is 960
(3840*3/12=960, Horizontal number of pixels * number of sub-pixels/source electrode driver number).It converts in a pair of (pair) type transmission mode,
The package number of one processing needed for a horizontal scanning line of source electrode driver 10 is 480 (960/2).When therefore in order to meet
The rising edge W of sequential signal D1RThe time point of corresponding multiple analog drive signal Y ' latches is not later than aforementioned clock signal D1's
Rising edge WR.Finishing touch data still lack 118.75ns (300-181.25=118.75).The original biography of each data
The defeated time is 6.25ns (1*9/1.44=6.25, bit number/original transmitted rate of a data).Each data it is original
Transmission time must reduce 0.2474ns (118.75/480 ≈ 0.2474).The amendment transmission time of each data is 6.0026ns
(6.25-0.2474=6.0026).And the amendment transmission time for being converted into a bit is 0.66696ns (6.0026/9 ≈
0.66696).Finally, it is 1.5Gbps that amendment transmission time, which is converted into amendment transmission rate,.Therefore, by improving each stroke count
According to transmission rate be 1.5Gbps, reduce " the first stroke numerical data of data-signal D1 starts Y " and arrive that " data-signal D1 is most
Latter stroke count digital data Y terminates " between time interval T5, to meet the rising edge W of clock signal D2RCorresponding multiple simulations
The time point of driving signal Y ' latch is not later than the rising edge W of aforementioned clock signal D2R。
In one embodiment, increase " terminating from the finishing touch numerical data Y of data-signal D1 " to " next data-signal
The first stroke numerical data Y of D1 starts " between time interval T6, to meet the rising edge W of clock signal D2RIt is corresponding multiple
The time point of analog drive signal Y ' latch is not later than the rising edge W of aforementioned clock signal D2R。
In one embodiment, pass through the data of reduction vertical scanning interregnum (vertical blanking period)
Package number can increase horizontal sweep interregnum data BK time span.Make that " finishing touch numerical data Y connects from data
Mouth circuit 100 receives " arrive " the rising edge W of clock signal D2R" time interval T2 increase, therefore increase " from data-signal D1
Finishing touch numerical data Y terminate " to the time interval between " the first stroke numerical data Y of next data-signal D1 starts "
T6, to meet the rising edge W of clock signal D2RWhen the time point of corresponding multiple analog drive signal Y ' latches is not later than aforementioned
The rising edge W of sequential signal D2R。
In conclusion advanced row digital simulation is converted into program, then holds according to the source electrode driver and its method of the disclosure
Row latch output program, thus signal can be made not postpone during source drive, the display effect of display device is maintained whereby
Energy.According to some embodiments, the disclosure be avoided that source drive process because each analog drive signal the output time not
The situation for unanimously causing each analog drive signal voltage output rate of change different further promotes the charging of display panel
Efficiency.
Claims (11)
1. a kind of source electrode driver, comprising:
One D/A conversion circuit, for receiving the data-signal with multiple numerical datas and converting the multiple number
Data are at multiple analog drive signals；And
One line latch circuit, couples the D/A conversion circuit, for the multiple analog drive signal of latch and according to one
One rising edge of clock signal exports the multiple analog drive signal.
2. source electrode driver as described in claim 1, wherein the D/A conversion circuit is integrated into the line latch circuit
One conversion latch circuit.
3. source electrode driver as claimed in claim 2 further includes an output buffer, the conversion latch circuit is coupled, is used
Corresponding the multiple analog drive signal is exported in the falling edge according to the clock signal.
4. source electrode driver as described in claim 1 further includes an output buffer, the line latch circuit is coupled, is used for
Falling edge according to the clock signal exports the multiple analog drive signal.
5. source electrode driver as described in claim 1, further includes:
One data interface circuit, for handling the data-signal and exporting a clock signal；And
One data buffering circuit is coupled between the data interface circuit and the D/A conversion circuit, when for according to this
Arteries and veins signal keeps in the data-signal.
6. the source electrode driver as described in any one of claims 1 to 5, the wherein corresponding institute of the rising edge of the clock signal
The time point for stating multiple analog drive signal latches is not later than the rising edge of the clock signal.
7. a kind of source driving method, comprising:
Receive a data-signal with multiple numerical datas；
The multiple numerical data is converted into multiple analog drive signals；And
According to a multiple analog drive signal of clock signal latch.
8. the source driving method as described in claim 7, further includes:
The multiple analog drive signal after buffering latch；And
According to the multiple analog drive signal after clock signal output buffering.
9. the source driving method as described in claim 7 or 8, wherein receiving the data with the multiple numerical data
The step of signal is the reception order that the multiple numerical data is determined according to the path length of the multiple numerical data transmitting.
10. the source driving method as described in claim 7 or 8, further includes:
Reducing the first stroke of data-signal numerical data and starting to the finishing touch of the data-signal numerical data terminates
Between time interval, the time of the corresponding the multiple analog drive signal latch of a rising edge to meet the clock signal
Point is not later than the rising edge of the clock signal.
11. the source driving method as described in claim 7 or 8, further includes:
From the finishing touch of the data-signal, the numerical data terminates to the first stroke of next data-signal numerical data for increase
Time interval between beginning, the corresponding the multiple analog drive signal latch of a rising edge to meet the clock signal
Time point is not later than the rising edge of the clock signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108101715 | 2019-01-16 | ||
| TW108101715A TWI706389B (en) | 2019-01-16 | 2019-01-16 | Source driver and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110473491A true CN110473491A (en) | 2019-11-19 |
| CN110473491B CN110473491B (en) | 2023-01-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910844244.0A Active CN110473491B (en) | 2019-01-16 | 2019-09-06 | Source driver and method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110473491B (en) |
| TW (1) | TWI706389B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4591902A (en) * | 1983-01-28 | 1986-05-27 | Citizen Watch Co., Ltd. | Matrix type color television panel driver circuit |
| CN101022006A (en) * | 2007-02-16 | 2007-08-22 | 友达光电股份有限公司 | Source electrode drive circuit and display panel equiped with the same circuit |
| CN101083061A (en) * | 2006-05-30 | 2007-12-05 | 中华映管股份有限公司 | Thin film Liquid crystal display board driving mchanism and method |
| CN101221729A (en) * | 2006-01-24 | 2008-07-16 | 友达光电股份有限公司 | Active matrix organic LED display |
| TW201005718A (en) * | 2008-07-30 | 2010-02-01 | Raydium Semiconductor Corp | Source driving apparatus and driving method thereof |
| TW201025254A (en) * | 2008-12-24 | 2010-07-01 | Au Optronics Corp | LCD devices and driving methods thereof |
| CN102915694A (en) * | 2012-07-23 | 2013-02-06 | 友达光电股份有限公司 | Source driver, operation method thereof and display device thereof |
| US20160055803A1 (en) * | 2014-08-19 | 2016-02-25 | Lg Display Co., Ltd. | Data Driver and Display Device Including the Same |
-
2019
- 2019-01-16 TW TW108101715A patent/TWI706389B/en active
- 2019-09-06 CN CN201910844244.0A patent/CN110473491B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4591902A (en) * | 1983-01-28 | 1986-05-27 | Citizen Watch Co., Ltd. | Matrix type color television panel driver circuit |
| CN101221729A (en) * | 2006-01-24 | 2008-07-16 | 友达光电股份有限公司 | Active matrix organic LED display |
| CN101083061A (en) * | 2006-05-30 | 2007-12-05 | 中华映管股份有限公司 | Thin film Liquid crystal display board driving mchanism and method |
| CN101022006A (en) * | 2007-02-16 | 2007-08-22 | 友达光电股份有限公司 | Source electrode drive circuit and display panel equiped with the same circuit |
| TW201005718A (en) * | 2008-07-30 | 2010-02-01 | Raydium Semiconductor Corp | Source driving apparatus and driving method thereof |
| TW201025254A (en) * | 2008-12-24 | 2010-07-01 | Au Optronics Corp | LCD devices and driving methods thereof |
| CN102915694A (en) * | 2012-07-23 | 2013-02-06 | 友达光电股份有限公司 | Source driver, operation method thereof and display device thereof |
| US20160055803A1 (en) * | 2014-08-19 | 2016-02-25 | Lg Display Co., Ltd. | Data Driver and Display Device Including the Same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202029158A (en) | 2020-08-01 |
| CN110473491B (en) | 2023-01-03 |
| TWI706389B (en) | 2020-10-01 |
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