CN102915694A - Source driver, operation method thereof and display device thereof - Google Patents
Source driver, operation method thereof and display device thereof Download PDFInfo
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Abstract
The invention relates to a source driver, an operation method thereof and a display device thereof. The source driver includes an interface circuit, a digital-to-analog converter, and a buffer unit. The interface circuit outputs the latched display data to the digital-to-analog converter according to the timing signal to convert the display data into a data voltage. The buffer unit receives a reference voltage and a data voltage and has an operational amplifier. The buffer unit provides the data voltage and the reference voltage to the first input end or the second input end of the operational amplifier according to the first latch signal and the second latch signal. The buffer unit alternately receives the reference voltage and the data voltage from the first input terminal and the second input terminal of the operational amplifier according to the second latch signal, and alternately couples the second input terminal and the first input terminal to the output terminal of the operational amplifier. The invention can reduce the influence of the offset voltage of the operational amplifier on the display quality of the display panel.
Description
Technical field
The invention relates to a kind of source electrode driver, its How It Works and display device thereof, and particularly relevant for a kind of source electrode driver, its How It Works and display device thereof with operational amplifier.
Background technology
Progress along with manufacturing technology, have that high image quality, space utilization efficient are good, the flat-panel screens of low consumpting power, the advantageous characteristic such as radiationless, such as liquid crystal display (LCD), organic light emitting diode display (OLED), replace gradually old cathode-ray tube (CRT), and become the main flow in market.In the drive system of display device, source electrode driver is pixel voltage in order to the turnover number bit data, and pixel voltage provides to the pixel that is enabled, and wherein source electrode driver can utilize output buffer to increase the driving force of pixel voltage.
Generally speaking, the output buffer of source electrode driver can utilize operational amplifier to realize, and operational amplifier is differential input.Yet the characteristic of the operational amplifier that is comprised of electronic component is unsatisfactory, so that the voltage of the input end of operation amplifier can be different and forms offset voltage, and then affects the voltage of the output terminal of operational amplifier.According to above-mentioned, be subjected under the impact of offset voltage at the voltage of the output terminal of operational amplifier, the optical effect that pixel presents can be different from the optical effect of expection, so that affected the display quality of display panel.
Summary of the invention
The invention provides a kind of source electrode driver, its How It Works and display device thereof, the input end of operational amplifier alternately receives reference voltage and data voltage, and the input end of operational amplifier alternately is coupled to an output terminal of operational amplifier, the offset voltage that can reduce by this operational amplifier affect to display panel display quality.
The present invention proposes a kind of source electrode driver, comprises an interface circuit, a digital analog converter and a buffer cell.Interface circuit receives the demonstration data that show data and export institute's breech lock according to a clock signal.Digital analog converter couples interface circuit, will show that data are converted to a data voltage.Buffer cell receives one first latch-up signal, one second latch-up signal and a reference voltage, couples digital analog converter with receive data voltage, and has an operational amplifier.Buffer cell provides a first input end or one second input end to operational amplifier according to the first latch-up signal with data voltage, and buffer cell provides first input end or the second input end to operational amplifier according to the second latch-up signal with reference to voltage.Buffer cell alternately receives reference voltage and data voltage according to the second latch-up signal with first input end and second input end of operational amplifier, and the second input end and first input end alternately is coupled to an output terminal of operational amplifier.
The present invention also proposes a kind of display device, comprises a display panel, a gate drivers and a source electrode driver as mentioned above.Gate drivers couples display panel, in order to provide a plurality of gate drive signals to display panel.Above-mentioned source electrode driver couples display panel, and in order to provide a plurality of pixel voltages to display panel, wherein the output terminal of operational amplifier provides these pixel voltages.
In one embodiment of this invention, buffer cell comprises a multiplexer, a DCU data control unit and a switching control module.Multiplexer couples digital analog converter with receive data voltage and reference voltage, and selects logarithmic output signal according to voltage or reference voltage according to one.DCU data control unit couples multiplexer and receives the first latch-up signal and the second latch-up signal, and the selection signal is provided, and DCU data control unit determines to select the voltage level of signal according to the first latch-up signal and the second latch-up signal.Switch control unit receives the second latch-up signal, in order to the inversion signal of an end points switching signal and end points switching signal to be provided, and switches the voltage level of end points switching signal according to the second latch-up signal.Wherein, buffer cell alternately receives to reference voltage and data voltage according to end points switching signal and inversion signal thereof first input end and the second input end with operational amplifier, and first input end and the second input end alternately is coupled to the output terminal of operational amplifier.
In one embodiment of this invention, operational amplifier is one section ripple operational amplifier.
In one embodiment of this invention, cut the ripple operational amplifier and comprise a first transistor, a transistor seconds, one the 3rd transistor, one the 4th transistor, one the 5th transistor, one first current source, one second current source, one first switch, a second switch, one the 3rd switch, one the 4th switch, one the 5th switch, one the 6th switch, minion pass and one the 8th switch.The first end of the first transistor receives a system voltage.The first end receiving system voltage of transistor seconds, the control end of transistor seconds couples the control end of the first transistor.The 3rd transistorized first end receiving system voltage, the output terminal that the 3rd transistorized the second end is operational amplifier.The 4th transistorized first end couples the second end of the first transistor, and the 4th transistorized control end is the first input end of operational amplifier.The 5th transistorized first end couples the second end of transistor seconds, and the 5th transistorized the second end couples the 4th transistorized the second end, and the 5th transistorized control end is the second input end of operational amplifier.The first current source is coupled between the 4th transistorized the second end and the ground voltage.The second current source is coupled between the 3rd transistorized the second end and the ground voltage.The first switch is coupled between the second end of the control end of the first transistor and the first transistor.Second switch is coupled between the second end of the control end of transistor seconds and transistor seconds.The 3rd switch is coupled between second end and the 3rd transistorized control end of transistor seconds.The 4th switch is coupled between second end and the 3rd transistorized control end of the first transistor.The 5th switch is coupled between the output terminal and the 4th transistorized control end of multiplexer.The 6th switch is coupled between the output terminal and the 5th transistorized control end of multiplexer.Minion is closed and is coupled between the 5th transistorized control end and the 3rd transistorized the second end.The 8th switch is coupled between the 4th transistorized control end and the 3rd transistorized the second end.Wherein, the first switch, the 3rd switch, the 6th switch and the 8th switch are controlled by the end points switching signal and conducting, and second switch, the 4th switch, the 5th switch and minion are closed the inversion signal that is controlled by the end points switching signal and conducting.
In one embodiment of this invention, buffer cell also comprises one the 9th switch, 1 the tenth switch, 1 the 11 switch and twelvemo pass.The 9th switch is coupled between the first input end of the output terminal of multiplexer and operational amplifier.The tenth switch is coupled between the second input end of the output terminal of multiplexer and operational amplifier.The 11 switch is coupled between the first input end and output terminal of operational amplifier.Twelvemo is closed and is coupled between second input end and output terminal of operational amplifier.Wherein, the 9th switch and twelvemo are closed and are controlled by the end points switching signal and conducting, and the tenth switch and the 11 switch are controlled by the inversion signal of end points switching signal and conducting.
In one embodiment of this invention, switch control unit comprises a JK flip-flop.The first input end of JK flip-flop and the second input end receive a high level voltage, the trigger end of JK flip-flop receives the second latch-up signal, the first output terminal exit point switching signal of JK flip-flop, the inversion signal of the second output terminal exit point switching signal of JK flip-flop.
In one embodiment of this invention, DCU data control unit comprises a latch unit.The set input of latch unit receives the first latch-up signal, and the replacement input end of latch unit receives the second latch-up signal, and signal is selected in the output terminal output of latch unit.
The present invention proposes a kind of How It Works of source electrode driver, comprises the following steps.Show that with one data are converted to a data voltage according to a clock signal.Provide a first input end or one second input end to operational amplifier according to one first latch-up signal with data voltage.Provide first input end or the second input end to operational amplifier according to the second latch-up signal with reference to voltage.The first input end of operational amplifier and the second input end be according to the second latch-up signal alternately receive data voltage and reference voltage, and the second input end and first input end alternately are coupled to an output terminal of operational amplifier according to the second latch-up signal.
In one embodiment of this invention, " first input end of operational amplifier and the second input end are according to the second latch-up signal alternately receive data voltage and reference voltage; and the second input end and first input end alternately are coupled to the output terminal of operational amplifier according to the second latch-up signal " step comprise: produce end points switching signal and an inversion signal thereof according to the second latch-up signal, wherein the voltage level of end points switching signal is controlled by the second latch-up signal and switches; The first input end of operational amplifier and the second input end be according to end points switching signal and inversion signal thereof alternately receive data voltage and reference voltage, and the second input end and first input end alternately are coupled to the output terminal of operational amplifier according to the end points switching signal.
In one embodiment of this invention, a plurality of activation times of the second latch-up signal laid respectively between a plurality of activation times of the first latch-up signal.
Based on above-mentioned, the source electrode driver of the embodiment of the invention, its How It Works and display device thereof, buffer cell foundation the second latch-up signal alternately receives reference voltage and data voltage with positive input terminal and the negative input end of operational amplifier, and alternately is coupled to the output terminal of operational amplifier in the positive input terminal of operational amplifier and the negative input end.By this, can reduce the offset voltage of operational amplifier to the impact of the display quality of display panel.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the system schematic according to the display device of one embodiment of the invention;
Fig. 2 is that Fig. 1 is according to the system schematic of the source electrode driver of one embodiment of the invention;
Fig. 3 is that Fig. 2 is according to the waveform synoptic diagram of the driving signal of the source electrode driver of one embodiment of the invention;
Fig. 4 is that Fig. 2 is according to the circuit diagram of the buffer cell of one embodiment of the invention;
Fig. 5 is that Fig. 2 is according to the circuit diagram of the buffer cell of another embodiment of the present invention;
Fig. 6 is the process flow diagram according to the How It Works of the source electrode driver of one embodiment of the invention.
Wherein, Reference numeral:
/ Q: negative output terminal
0: low voltage level
1: high-voltage level
100: display device
110: time schedule controller
120: gate drivers
130,130 ': source electrode driver
140: display panel
210: data channel
211: interface circuit
213: digital analog converter
215,215 ', 215 ": buffer cell
410,510:JK trigger
420,520: latch unit
C1: electric capacity
CHOP: end points switching signal
CHOP ': inversion signal
CLK: trigger end
COP: cut the ripple operational amplifier
Ddisp: show data
I1, I2: current source
J, K: input end
L1, L2: solid line
L3, L4: dotted line
MX1, MX2: multiplexer
OP: operational amplifier
P1, P2: activation time
Q: positive output end
R1: resistance
RST: replacement input end
SC: sweep signal
SEL: select signal
SET: set input
STB1: the first latch-up signal
STB2: the second latch-up signal
STI: clock signal
SW1 ~ SW12: switch
T1 ~ T5: transistor
Vdata, Vdata1, Vdata2: data voltage
VDD: system voltage
VP: pixel voltage
Vref, Vref1, Vref2: reference voltage
VSS: ground voltage
S610, S620, S630, S640: step
Embodiment
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Fig. 1 is the system schematic according to the display device of one embodiment of the invention.Please refer to Fig. 1, in the present embodiment, display device 100 comprises time schedule controller 110, gate drivers 120, source electrode driver 130 and display panel 140, and wherein take organic electroluminescence display panel as example, but the embodiment of the invention is not as limit at this for display panel 140.Gate drivers 120 couples time schedule controller 110 and display panel 140, be controlled by time schedule controller 110 will sequentially transmit a plurality of to display panel 140, open to drive by column the pixel (not illustrating) of display panel 140.Source electrode driver 130 couples time schedule controller 110 and display panel 140, the pixel (not illustrating) that provides a plurality of pixel voltage VP to open to the display panel 140 to be controlled by time schedule controller 110, by this display panel 140 show image accordingly.
Fig. 2 is that Fig. 1 is according to the system schematic of the source electrode driver of one embodiment of the invention.Please refer to Fig. 1 and Fig. 2, in the present embodiment, source electrode driver 130 ' comprises a plurality of data channel 210, provide these pixel voltages VP after wherein these data channel 210 receive a plurality of demonstration data Ddisp, and show that data Ddisp is provided by time schedule controller 110, but the embodiment of the invention is not as limit.Each data channel 210 comprises interface circuit 211, digital analog converter 213 and buffer cell 215.Interface circuit 211 receives and shows data Ddisp and clock signal STI, in order to demonstration data Ddisp corresponding to breech lock, and according to the demonstration data Ddisp of clock signal STI output institute breech lock.Digital analog converter 213 couples interface circuit 211, is converted to data voltage Vdata in order to the demonstration data Ddisp that interface circuit 211 is exported.
Furthermore, buffer cell 215 can determine to provide data voltage Vdata or reference voltage Vref to operational amplifier OP according to the first latch-up signal STB1 and the second latch-up signal STB2, that is buffer cell 215 can provide data voltage Vdata to operational amplifier OP when triggered by the first latch-up signal STB1, and buffer cell 215 can provide to operational amplifier OP with reference to voltage Vref when triggered by the second latch-up signal STB2.
And buffer cell 215 can determine to bring in reception reference voltage Vref and data voltage Vdata by positive input terminal or the negative input of operational amplifier OP according to the second latch-up signal STB2.When buffer cell 215 determines that according to the second latch-up signal STB2 positive input terminal by operational amplifier OP is used for receiving reference voltage Vref and data voltage Vdata, buffer cell 215 can couple the negative input end of operational amplifier OP the output terminal of operational amplifier OP, above-mentioned can be with reference in the buffer cell 215 shown in solid line L1 and the L2.When buffer cell 215 determines that according to the second latch-up signal STB2 negative input end by operational amplifier OP is used for receiving reference voltage Vref and data voltage Vdata, buffer cell 215 can couple the positive input terminal of operational amplifier OP the output terminal of operational amplifier OP, above-mentioned can be with reference in the buffer cell 215 shown in dotted line L3 and the L4.
In other words, buffer cell 215 provides positive input terminal or negative input end to operational amplifier OP according to the first latch-up signal STB1 with data voltage Vdata, buffer cell 215 provides positive input terminal or negative input end to operational amplifier OP according to the second latch-up signal STB2 with reference to voltage Vref, buffer cell 215 alternately receives reference voltage Vref and data voltage Vdata according to the second latch-up signal STB with positive input terminal and the negative input end of operational amplifier OP, and the output terminal that negative input end and the positive input terminal of operational amplifier OP alternately is coupled to operational amplifier OP.
According to organic electroluminescence display panel, each pixel (not illustrating) can receive first reference voltage Vref and carry out the replacement of picture (that is the corresponding reference voltage Vref of pixel voltage VP elder generation), then receive data voltage Vdata(that is pixel voltage VP follow corresponding data voltage Vdata), the wherein brightness that should show in order to each pixel in the control display panel of the pressure reduction between data voltage Vdata and the reference voltage Vref.Therefore, buffer cell 215 foundations the second latch-up signal STB2 alternately receives reference voltage Vref and data voltage Vdata with positive input terminal and the negative input end of operational amplifier OP, can cause the display effect of each row pixel (not illustrating) in the display panel 140 to present complementation with the display effect of adjacent column pixel (not illustrating), can reduce by this positive input terminal of operational amplifier OP and the offset voltage between negative input end to the impact of the display quality of display panel.
In addition, in one embodiment of this invention, the initial order that positive input terminal by adjusting operational amplifier OP and negative input end receive reference voltage Vref and data voltage Vdata, that is begin to receive reference voltage Vref and data voltage Vdata by the positive input terminal of operational amplifier OP in during a picture, negative input end by operational amplifier OP in during next picture begins to receive reference voltage Vref and data voltage Vdata, then during the picture in each row pixel (not illustrating) display effect can with during next picture in the display effect of same row pixel (not illustrating) present complementation.
Fig. 3 is that Fig. 2 is according to the waveform synoptic diagram of the driving signal of the source electrode driver of one embodiment of the invention.Please refer to Fig. 2 and Fig. 3, according to above-mentioned, reference voltage Vref and data voltage Vdata can alternately provide to operational amplifier OP, and therefore a plurality of activation time P2 of the second latch-up signal STB2 lay respectively between a plurality of activation time P1 of the first latch-up signal STB1.
In the present embodiment, buffer cell 215 alternately receives reference voltage Vref and data voltage Vdata according to the second latch-up signal STB with positive input terminal and the negative input end of operational amplifier OP, and the output terminal that negative input end and the positive input terminal of operational amplifier OP alternately is coupled to operational amplifier OP.According to above-mentioned, pixel voltage VP with the single pixel of correspondence, one group of voltage that buffer cell 215 is exported (such as reference voltage Vref 1 and data voltage Vdata1) may add for reference voltage Vref reference voltage Vref and the data voltage Vdata of offset voltage, perhaps for deducting reference voltage Vref and the data voltage Vdata of offset voltage.Because the brightness (being the GTG value) of each pixel is decided by the pressure reduction of the data voltage Vdata of corresponding reference voltage Vref and correspondence, so the display effect of each pixel (not illustrating) is subjected to the impact of offset voltage lower in the display panel 140.
Similarly, pixel voltage VP with the same data channel 210 of correspondence, one of them is for adding offset voltage reference voltage Vref and data voltage Vdata for two groups of voltages that buffer cell 215 is sequentially exported (such as reference voltage Vref 1 and data voltage Vdata1 and reference voltage Vref 2 and data voltage Vdata2), above-mentioned two groups of voltages wherein another is reference voltage Vref and the data voltage Vdata that deducts offset voltage, therefore the reference voltage (such as Vref1 and Vref2) that two adjacent column pixels (not illustrating) receive in the display panel 140 can be complementary with the pressure reduction of data voltage (such as Vdata1 and Vdata2), with the positive input terminal of reduction operational amplifier OP and the impact of the offset voltage between negative input end.
Fig. 4 is that Fig. 2 is according to the circuit diagram of the buffer cell of one embodiment of the invention.Please refer to Fig. 2, Fig. 3 and Fig. 4, in the present embodiment, buffer cell 215 ' comprises switch control unit (at this take JK flip-flop 410 as example), DCU data control unit (at this take latch unit 420 as example), multiplexer MX1 and cuts a ripple operational amplifier COP.
The corresponding first input end of the input end J of JK flip-flop 410 and K(and the second input end) receive high level voltage " 1 ", and the trigger end CLK of JK flip-flop 410 receives the second latch-up signal STB2, and wherein JK flip-flop 410 is to trigger as example take positive edge.Corresponding the first output terminal of the positive output end Q(of JK flip-flop 410) exit point switching signal CHOP, corresponding the second output terminal of the negative output terminal of JK flip-flop 410/Q() the inversion signal CHOP ' of exit point switching signal CHOP.According to above-mentioned, switch control unit can receive the second latch-up signal STB2, so that the inversion signal CHOP ' of end points switching signal CHOP and end points switching signal to be provided, and switch the voltage level of end points switching signal CHOP and inversion signal CHOP ' thereof according to the second latch-up signal STB2.That is, when switch control unit (be JK flip-flop 410 at this) triggers at the positive edge that is subjected to the second latch-up signal STB2, can switch to high-voltage level " 1 " or switch to low voltage level " 0 " by high-voltage level " 1 " by low voltage level " 0 ".
The set input SET of latch unit 420 receives the first latch-up signal STB1, and the replacement input end RST of latch unit 420 receives the second latch-up signal STB, and signal SEL is selected in the output terminal output of latch unit 420, and wherein latch unit 420 is to trigger as example take positive edge.According to above-mentioned, DCU data control unit (be JK flip-flop 410 at this) receives the first latch-up signal STB1 and the second latch-up signal STB2, and selection signal SEL is provided.And DCU data control unit (be JK flip-flop 410 at this) determines to select the voltage level of signal SEL according to the first latch-up signal STB1 and the second latch-up signal STB2.That is, when DCU data control unit (be JK flip-flop 410 at this) triggers at the positive edge that is subjected to the second latch-up signal STB2, can switch to high-voltage level " 1 " or switch to low voltage level " 0 " by high-voltage level " 1 " by low voltage level " 0 ".
Multiplexer MX1 couples latch unit 420 and selects signal SEL to receive, couple digital analog converter 213 with receive data voltage Vdata, and receive reference voltage Vref, and multiplexer MX1 is according to selecting signal SEL output data voltage Vdata or reference voltage Vref.In the present embodiment, when selecting signal SEL to be low voltage level " 0 ", therefore multiplexer MX1 meeting output reference voltage Vref cuts ripple operational amplifier COP and can receive reference voltage Vref by corresponding second a latch-up signal STB2; When selecting signal SEL to be high-voltage level " 1 ", multiplexer MX1 can export data voltage Vdata, therefore cuts ripple operational amplifier COP and can receive data voltage Vdata by corresponding the first latch-up signal STB1.
Cut ripple operational amplifier COP and comprise corresponding the first transistor to the five transistors of transistor T 1 ~ T5(), current source I1 and corresponding the first current source of I2(and the second current source), corresponding the first switch to the eight switches of interrupteur SW 1 ~ SW8().The source electrode of transistor T 1 (corresponding first end) receiving system voltage VDD.The source electrode of transistor T 2 (corresponding first end) receiving system voltage VDD, the grid of transistor T 2 (corresponding control end) couples the grid (control end) of transistor T 1.The source electrode of transistor T 3 (corresponding first end) receiving system voltage VDD, the drain electrode of transistor T 3 (corresponding the second end) is output pixel voltage VP.The drain electrode of transistor T 4 (corresponding first end) couples the drain electrode (corresponding the second end) of transistor T 1.The drain electrode of transistor T 5 (corresponding first end) couples the drain electrode (corresponding the second end) of transistor T 2, and the source electrode of transistor T 5 (corresponding the second end) couples the source electrode (corresponding the second end) of transistor T 4.Current source I1 is coupled between the source electrode and ground voltage VSS of transistor T 4.Current source I2 is coupled between the source electrode and ground voltage VSS of transistor T 3.
In the present embodiment, interrupteur SW 1, SW3, SW6 and SW8 are controlled by end points switching signal CHOP and conducting, and interrupteur SW 2, SW4, SW5 and SW7 are controlled by the inversion signal CHOP ' of end points switching signal CHOP and conducting.When interrupteur SW 1, SW3, SW6 and SW8 are controlled by end points switching signal CHOP and conducting, interrupteur SW 2, SW4, SW5 and SW7 can not conductings.At this moment, the running identity of operation amplifier OP of transistor T 1 ~ T5, the grid of the grid of transistor T 4 and transistor T 5 is equal to positive input terminal and the negative input end of operational amplifier OP, and the drain electrode of transistor T 3 is equal to the output terminal of operational amplifier OP.And the grid of transistor T 5 receives reference voltage Vref and data voltage Vdata, and the grid of transistor T 4 is coupled to the drain electrode of transistor T 3.
When interrupteur SW 2, SW4, SW5 and SW7 are controlled by the inversion signal CHOP ' of end points switching signal CHOP and conducting, interrupteur SW 1, SW3, SW6 and SW8 can not conductings.At this moment, the running of transistor T 1 ~ T5 is identity of operation amplifier OP still, and the grid of transistor T 4 reception reference voltage Vref and data voltage Vdata, and the grid of transistor T 5 is coupled to the drain electrode of transistor T 3.
According to the action that cuts ripple operational amplifier COP, two input ends (being the grid of transistor T 4 and T5) that cut ripple operational amplifier COP can alternately receive reference voltage Vref and data voltage Vdata according to end points switching signal CHOP, and alternately are coupled to output terminal (being the drain electrode of transistor T 3).According to above-mentioned, buffer cell 215 ' can alternately receive positive input terminal and the negative input end of operational amplifier OP to reference voltage Vref and data voltage Vdata according to end points switching signal CHOP and inversion signal CHOP thereof, and the output terminal that positive input terminal and the negative input end of operational amplifier OP alternately is coupled to operational amplifier OP.
In the present embodiment, cut ripple operational amplifier COP and also comprise resistance R 1 and capacitor C 1, wherein resistance R 1 and capacitor C 1 are that coupled in series is in grid and the drain electrode of transistor T 3.By resistance R 1 and capacitor C 1, the voltage of the drain electrode of transistor T 3 can exchange the grid that feeds back to transistor T 3, can significantly reduce so that the voltage of the drain electrode of transistor T 3 is affected by noise.Different based on the requirement of circuit, resistance R 1 and capacitor C 1 optionally dispose, and also can omit resistance R 1 and capacitor C 1 but in other embodiments.
Fig. 5 is that Fig. 2 is according to the circuit diagram of the buffer cell of another embodiment of the present invention.Please refer to Fig. 3, Fig. 4 and Fig. 5, in the present embodiment, buffer cell 215 " comprise that switch control unit (at this take JK flip-flop 510 as example), DCU data control unit (at this take latch unit 520 as example), operational amplifier OP and corresponding the 9th switch to the twelvemo of interrupteur SW 9 ~ SW12(close).Wherein, the action of JK flip-flop 510, latch unit 520 and multiplexer MX2 does not then repeat superfluous similar in appearance to the described JK flip-flop 410 of Fig. 4 embodiment, latch unit 420 and multiplexer MX1 at this.
Interrupteur SW 9 is coupled between the positive input terminal of the output terminal of multiplexer MX2 and operational amplifier OP.Interrupteur SW 10 is coupled between the negative input end of the output terminal of multiplexer MX2 and operational amplifier OP.Interrupteur SW 11 is coupled between the positive input terminal and output terminal of operational amplifier OP.Interrupteur SW 12 is coupled between the negative input end and output terminal of operational amplifier OP.
In the present embodiment, interrupteur SW 9 and SW12 are controlled by end points switching signal CHOP and conducting, and interrupteur SW 10 and interrupteur SW 11 are controlled by the inversion signal CHOP ' of end points switching signal CHOP and conducting.When interrupteur SW 9 and SW12 are controlled by end points switching signal CHOP and conducting, interrupteur SW 10 and interrupteur SW 11 can not conductings.At this moment, the positive input terminal of operational amplifier OP receives reference voltage Vref and data voltage Vdata, and the negative input end of operational amplifier OP is coupled to the output terminal of operational amplifier OP.When interrupteur SW 10 and interrupteur SW 11 are controlled by the inversion signal CHOP ' of end points switching signal CHOP and conducting, interrupteur SW 9 and SW12 can not conductings.At this moment, the negative input end of operational amplifier OP receives reference voltage Vref and data voltage Vdata, and the positive input terminal of operational amplifier OP is coupled to the output terminal of operational amplifier OP.
Action according to interrupteur SW 9 ~ SW12, two input ends of operational amplifier OP can alternately receive reference voltage Vref and data voltage Vdata according to end points switching signal CHOP, and two input ends of operational amplifier OP can alternately be coupled to according to end points switching signal CHOP the output terminal of operational amplifier OP.According to above-mentioned, buffer cell 215 " can positive input terminal and the negative input end of operational amplifier OP alternately be received to reference voltage Vref and data voltage Vdata according to end points switching signal CHOP and inversion signal CHOP thereof, and the output terminal that positive input terminal and the negative input end of operational amplifier OP alternately is coupled to operational amplifier OP.
Fig. 6 is the process flow diagram according to the How It Works of the source electrode driver of one embodiment of the invention.Please refer to Fig. 6, in the present embodiment, the How It Works of source electrode driver comprises the following steps.To show that according to a clock signal data are converted to data voltage (step S610).Then, provide positive input terminal or negative input end (step S620) to operational amplifier according to the first latch-up signal with data voltage, and provide positive input terminal or negative input end (step S630) to operational amplifier according to the second latch-up signal with reference to voltage.At last, the positive input terminal of operational amplifier and negative input end be according to the second latch-up signal alternately receive data voltage and reference voltage, and the positive input terminal of operational amplifier and negative input end alternately are coupled to the output terminal (step S640) of operational amplifier according to the second latch-up signal.Wherein, the voltage level of the output terminal of operational amplifier is corresponding reference voltage first, then the voltage level corresponding data voltage of the output terminal of operational amplifier.At this, the order of above-mentioned steps is that the embodiment of the invention is not as limit in order to explanation.And the details of above-mentioned steps can with reference to the embodiment of Fig. 2 to Fig. 5, then repeat no more at this.
In sum, the source electrode driver of the embodiment of the invention, its How It Works and display device thereof, buffer cell alternately receives reference voltage and data voltage according to the second latch-up signal with positive input terminal and the negative input end of operational amplifier, and an end that does not receive reference voltage and data voltage in the positive input terminal of operational amplifier and the negative input end is coupled to the output terminal of operational amplifier.The offset voltage that by this, can reduce operational amplifier on display panel the impact of display quality.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (19)
1. a source electrode driver is characterized in that, comprising:
One interface circuit, reception one show data and export these demonstration data of institute's breech lock according to a clock signal;
One digital analog converter couples this interface circuit, should show that data were converted to a data voltage; And
One buffer cell, receive one first latch-up signal, one second latch-up signal and a reference voltage, couple this digital analog converter to receive this data voltage, and has an operational amplifier, this buffer cell provides a first input end or one second input end to this operational amplifier according to this first latch-up signal with this data voltage, this buffer cell provides this first input end or this second input end to this operational amplifier according to this second latch-up signal with this reference voltage, this buffer cell alternately receives this reference voltage and this data voltage according to this second latch-up signal with this first input end of this operational amplifier and this second input end, and this second input end and this first input end alternately are coupled to an output terminal of this operational amplifier, wherein the voltage level of this output terminal is first to should reference voltage, and then the voltage level of this output terminal is to should data voltage.
2. source electrode driver according to claim 1 is characterized in that, this buffer cell comprises:
One multiplexer couples this digital analog converter receiving this data voltage and to receive this reference voltage, and selects signal to export this data voltage or this reference voltage according to one;
One DCU data control unit couples this multiplexer and receives this first latch-up signal and this second latch-up signal, and this selection signal is provided, and this DCU data control unit determines the voltage level of this selection signal according to this first latch-up signal and this second latch-up signal; And
One switches control module, receives this second latch-up signal, in order to the inversion signal of an end points switching signal and this end points switching signal to be provided, and switches the voltage level of this end points switching signal according to this second latch-up signal;
Wherein this buffer cell alternately receives to this reference voltage and this data voltage according to this end points switching signal and inversion signal thereof this first input end and this second input end with this operational amplifier, and this first input end and this second input end alternately is coupled to this output terminal of this operational amplifier.
3. source electrode driver according to claim 2 is characterized in that, this operational amplifier is one section ripple operational amplifier.
4. source electrode driver according to claim 3 is characterized in that, this section ripple operational amplifier comprises:
One the first transistor, the first end of this first transistor receives a system voltage;
One transistor seconds, the first end of this transistor seconds receives this system voltage, and the control end of this transistor seconds couples the control end of this first transistor;
One the 3rd transistor, the 3rd transistorized first end receives this system voltage, this output terminal that the 3rd transistorized the second end is this operational amplifier;
One the 4th transistor, the 4th transistorized first end couples the second end of this first transistor, and the 4th transistorized control end is this first input end of this operational amplifier;
One the 5th transistor, the 5th transistorized first end couples the second end of this transistor seconds, and the 5th transistorized the second end couples the 4th transistorized the second end, and the 5th transistorized control end is this second input end of this operational amplifier;
One first current source is coupled between the 4th transistorized the second end and the ground voltage;
One second current source is coupled between the 3rd transistorized the second end and this ground voltage;
One first switch is coupled between the second end of the control end of this first transistor and this first transistor;
One second switch is coupled between the second end of the control end of this transistor seconds and this transistor seconds;
One the 3rd switch is coupled between second end and the 3rd transistorized control end of this transistor seconds;
One the 4th switch is coupled between second end and the 3rd transistorized control end of this first transistor;
One the 5th switch is coupled between the output terminal and the 4th transistorized control end of this multiplexer;
One the 6th switch is coupled between the output terminal and the 5th transistorized control end of this multiplexer;
One minion is closed, and is coupled between the 5th transistorized control end and the 3rd transistorized the second end; And
One the 8th switch is coupled between the 4th transistorized control end and the 3rd transistorized the second end;
Wherein, this first switch, the 3rd switch, the 6th switch and the 8th switch are controlled by this end points switching signal and conducting, and this second switch, the 4th switch, the 5th switch and this minion are closed the inversion signal that is controlled by this end points switching signal and conducting.
5. source electrode driver according to claim 2 is characterized in that, this buffer cell also comprises:
One the 9th switch is coupled between this first input end of the output terminal of this multiplexer and this operational amplifier;
The tenth switch is coupled between this second input end of the output terminal of this multiplexer and this operational amplifier;
The 11 switch is coupled between this first input end and this output terminal of this operational amplifier;
One twelvemo is closed, and is coupled between this second input end and this output terminal of this operational amplifier;
Wherein, the 9th switch and this twelvemo are closed and are controlled by this end points switching signal and conducting, and the tenth switch and the 11 switch are controlled by the inversion signal of this end points switching signal and conducting.
6. source electrode driver according to claim 2, it is characterized in that, this switch control unit comprises a JK flip-flop, the first input end of this JK flip-flop and the second input end receive a high level voltage, the trigger end of this JK flip-flop receives this second latch-up signal, the first output terminal of this JK flip-flop is exported this end points switching signal, and the second output terminal of this JK flip-flop is exported the inversion signal of this end points switching signal.
7. source electrode driver according to claim 2, it is characterized in that, this DCU data control unit also comprises a latch unit, the set input of this latch unit receives this first latch-up signal, the replacement input end of this latch unit receives this second latch-up signal, and the output terminal of this latch unit is exported this selection signal.
8. source electrode driver according to claim 1 is characterized in that, a plurality of activation times of this second latch-up signal laid respectively between a plurality of activation times of this first latch-up signal.
9. a display device is characterized in that, comprising:
One display panel;
One gate drivers couples this display panel, in order to provide a plurality of gate drive signals to this display panel; And
The one source pole driver couples this display panel, in order to provide a plurality of pixel voltages to this display panel, comprising:
One interface circuit, reception one show data and export these demonstration data of institute's breech lock according to a clock signal;
One digital analog converter couples this interface circuit, should show that data were converted to a data voltage; And
One buffer cell, receive one first latch-up signal, one second latch-up signal and a reference voltage, couple this digital analog converter to receive this data voltage, and has an operational amplifier, this buffer cell provides a first input end or one second input end to this operational amplifier according to this first latch-up signal with this data voltage, this buffer cell provides this first input end or this second input end to this operational amplifier according to this second latch-up signal with this reference voltage, this buffer cell alternately receives this first input end of this operational amplifier and this second input end to this reference voltage and this data voltage according to this second latch-up signal, and this second input end and this first input end alternately are coupled to an output terminal of this operational amplifier, this output terminal of this operational amplifier provides those pixel voltages, wherein those pixel voltages are first to should reference voltage, and then those pixel voltages are to should data voltage.
10. display device according to claim 9 is characterized in that, this buffer cell comprises:
One multiplexer couples this digital analog converter receiving this data voltage and this reference voltage, and selects signal to export this data voltage or this reference voltage according to one;
One DCU data control unit couples this multiplexer and receives this first latch-up signal and this second latch-up signal, and this selection signal is provided, and this DCU data control unit determines the voltage level of this selection signal according to this first latch-up signal and this second latch-up signal; And
One switches control module, receives this second latch-up signal, in order to the inversion signal of an end points switching signal and this end points switching signal to be provided, and switches the voltage level of this end points switching signal according to this second latch-up signal;
Wherein this buffer cell alternately receives to this reference voltage and this data voltage according to this end points switching signal and inversion signal thereof this first input end and this second input end with this operational amplifier, and this first input end and this second input end alternately is coupled to this output terminal of this operational amplifier.
11. display device according to claim 10 is characterized in that, this operational amplifier is one section ripple operational amplifier.
12. display device according to claim 11 is characterized in that, this section ripple operational amplifier comprises:
One the first transistor, the first end of this first transistor receives a system voltage;
One transistor seconds, the first end of this transistor seconds receives this system voltage, and the control end of this transistor seconds couples the control end of this first transistor;
One the 3rd transistor, the 3rd transistorized first end receives this system voltage, this output terminal that the 3rd transistorized the second end is this operational amplifier;
One the 4th transistor, the 4th transistorized first end couples the second end of this first transistor, and the 4th transistorized control end is this first input end of this operational amplifier;
One the 5th transistor, the 5th transistorized first end couples the second end of this transistor seconds, and the 5th transistorized the second end couples the 4th transistorized the second end, and the 5th transistorized control end is this second input end of this operational amplifier;
One first current source is coupled between the 4th transistorized the second end and the ground voltage;
One second current source is coupled between the 3rd transistorized the second end and this ground voltage;
One first switch is coupled between the second end of the control end of this first transistor and this first transistor;
One second switch is coupled between the second end of the control end of this transistor seconds and this transistor seconds;
One the 3rd switch is coupled between second end and the 3rd transistorized control end of this transistor seconds;
One the 4th switch is coupled between second end and the 3rd transistorized control end of this first transistor;
One the 5th switch is coupled between the output terminal and the 4th transistorized control end of this multiplexer;
One the 6th switch is coupled between the output terminal and the 5th transistorized control end of this multiplexer;
One minion is closed, and is coupled between the 5th transistorized control end and the 3rd transistorized the second end; And
One the 8th switch is coupled between the 4th transistorized control end and the 3rd transistorized the second end;
Wherein, this first switch, the 3rd switch, the 6th switch and the 8th switch are controlled by this end points switching signal and conducting, and this second switch, the 4th switch, the 5th switch and this minion are closed the inversion signal that is controlled by this end points switching signal and conducting.
13. display device according to claim 10 is characterized in that, this buffer cell also comprises:
One the 9th switch is coupled between this first input end of the output terminal of this multiplexer and this operational amplifier;
The tenth switch is coupled between this second input end of the output terminal of this multiplexer and this operational amplifier;
The 11 switch is coupled between this first input end and this output terminal of this operational amplifier;
One twelvemo is closed, and is coupled between this second input end and this output terminal of this operational amplifier;
Wherein, the 9th switch and this twelvemo are closed and are controlled by this end points switching signal and conducting, and the tenth switch and the 11 switch are controlled by the inversion signal of this end points switching signal and conducting.
14. display device according to claim 10, it is characterized in that, this switch control unit comprises a JK flip-flop, the first input end of this JK flip-flop and the second input end receive a high level voltage, the trigger end of this JK flip-flop receives this second latch-up signal, the first output terminal of this JK flip-flop is exported this end points switching signal, and the second output terminal of this JK flip-flop is exported the inversion signal of this end points switching signal.
15. display device according to claim 10, it is characterized in that, this DCU data control unit comprises a latch unit, the set input of this latch unit receives this first latch-up signal, the replacement input end of this latch unit receives this second latch-up signal, and the output terminal of this latch unit is exported this selection signal.
16. display device according to claim 9 is characterized in that, a plurality of activation times of this second latch-up signal laid respectively between a plurality of activation times of this first latch-up signal.
17. the How It Works of a source electrode driver is characterized in that, comprising:
Show that with one data are converted to a data voltage according to a clock signal;
Provide a first input end or one second input end to this operational amplifier according to one first latch-up signal with this data voltage;
Provide this first input end or this second input end to this operational amplifier according to this second latch-up signal with this reference voltage; And
This first input end of this operational amplifier and this second input end alternately receive this data voltage and this reference voltage according to this second latch-up signal, and this second input end and this first input end alternately are coupled to an output terminal of this operational amplifier according to this second latch-up signal, wherein the voltage level of this output terminal is first to should reference voltage, and then the voltage level of this output terminal is to should data voltage.
18. the How It Works of source electrode driver according to claim 17, it is characterized in that, this first input end of this operational amplifier and this second input end alternately receive this data voltage and this reference voltage according to this second latch-up signal, and this second input end and this first input end alternately are coupled to this output terminal of this operational amplifier according to this second latch-up signal " step comprise:
Produce end points switching signal and an inversion signal thereof according to this second latch-up signal, wherein the voltage level of this end points switching signal is controlled by this second latch-up signal and switches; And
This first input end of this operational amplifier and this second input end alternately receive this data voltage and this reference voltage according to this end points switching signal and inversion signal thereof, and this second input end and this first input end alternately are coupled to this output terminal of this operational amplifier according to this end points switching signal.
19. the How It Works of source electrode driver according to claim 17 is characterized in that, a plurality of activation times of this second latch-up signal laid respectively between a plurality of activation times of this first latch-up signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101126503 | 2012-07-23 | ||
| TW101126503A TWI474301B (en) | 2012-07-23 | 2012-07-23 | Source driver, operating method thereof and display apparatus using the same |
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| CN102915694A true CN102915694A (en) | 2013-02-06 |
| CN102915694B CN102915694B (en) | 2015-06-17 |
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| CN201210384323.6A Active CN102915694B (en) | 2012-07-23 | 2012-10-11 | Source driver, operation method thereof and display device thereof |
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Also Published As
| Publication number | Publication date |
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| TWI474301B (en) | 2015-02-21 |
| TW201405510A (en) | 2014-02-01 |
| CN102915694B (en) | 2015-06-17 |
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