CN110429985A - A kind of fully integrated inexpensive high-speed, high precision Outphasing modulator - Google Patents
A kind of fully integrated inexpensive high-speed, high precision Outphasing modulator Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/516—Details of coding or modulation
- H04B10/54—Intensity modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/516—Details of coding or modulation
- H04B10/548—Phase or frequency modulation
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Abstract
The invention discloses a kind of fully integrated inexpensive high-speed, high precision Outphasing modulators, high speed (sample frequency > 1GHz) digital baseband signal of amplitude modulation and phase modulation all the way (such as QAM, OFDM) can be decomposed into two-way perseverance envelope phase-modulated signal by the high speed Outphasing modulator, in the case where guaranteeing the linearity, the power efficiency and output power of millimeter wave power amplification system are greatly improved.The high speed Outphasing modulator is made of input stage width phase computing module, intergrade out-phase angle computing module and two-way output stage I, Q computing module.The high speed Outphasing modulator is realized based on cordic algorithm, precision can improve by adjusting the number of iterations, operation is realized since cordic algorithm only uses adder, without using multiplier, it does not need to table look-up, so that throughput rate is promoted, and chip area is reduced, and manufacturing cost can be greatly reduced based on chip manufacturing process such as CMOS.
Description
Technical field
The present invention relates to a kind of fully integrated inexpensive high-speed, high precision Outphasing modulators, belong to design of electronic circuits technology neck
Domain, especially suitable for Super-high-speed digital circuits design and the design of millimeter-wave systems intermediate power amplifier.
Background technique
The 5G epoch are coming up, and due to the plurality of advantages of millimeter wave, millimeter wave wireless system, which is becoming more to have, to be inhaled
Gravitation.In millimeter wave high speed data transfer, millimeter wave Linear Power Amplifier is indispensable.However, millimeter wave power amplifier design is just
Face a huge challenge --- big power consumption and low efficiency problem.
Chireix modulation technology (Outphasing) is that one for promoting millimeter-wave power amplifiers efficiency very has prospect
Technology.The core of its technology is all continually changing signal of amplitude, a phase (as QAM, OFDM modulation generate
Baseband digital signal) it is decomposed into the phase-modulated signal of two constant-envelopes, phase change, and power is carried out to two paths of signals respectively and is put
Greatly, original signal is finally synthesized again.The linearity to two-way power amplifier can be reduced in this way, keep its workspace indirect
Smectic body pipe saturation region, to reach high-output power and high power efficiency.The existing function using using Chireix modulation technology
About 10% improved efficiency may be implemented in rate amplifier.
However, needing high-speed, high precision Outphasing modulator using the technology, the super of millimeter-wave communication system application will be used for
(GSample/s) baseband digital signal is decomposed into the out-of-phase signal that two-way amplitude is equal, phase is different at a high speed, this is the technology
One difficult point.
Summary of the invention
In recent years, with the development of millimetre-wave attenuator technology, the requirement to millimeter-wave power amplifiers efficiency is also increasingly
Height, meanwhile, the big bandwidth characteristic of millimeter wave requires high speed (sample frequency > 1GHz) digital processing rate, and the present invention needs to solve
The two technical problems.
Existing millimeter wave linear power amplifier is difficult to realize efficient bottleneck and is, according to linear power amplifier
Characteristic, power amplifier works just has high efficiency near transistor saturation region, however the poor linearity near saturation region, from
And output signal is caused to be distorted.So the dynamic range of existing millimeter-wave power amplifiers carries out centainly from 1dB compression point
It retracts, to guarantee the good linearity.However, retracting brings the reduction of output signal papr (PAPR), from
And cause the reduction of output power and power efficiency.
Amplitude, the input signal of phase change are resolved into that two-way amplitude is constant, branch of phase change by Chireix modulation technology
Road signal allows two-way millimeter wave power amplifier to continue working near saturation region, the delivery efficiency of power amplifier is made to be improved significantly (about
10%), output power substantially improves, while guaranteeing the good linearity.
To achieve the goals above, the present invention adopts the following technical scheme:
A kind of fully integrated inexpensive high-speed, high precision Outphasing modulator, based on cordic algorithm, including input stage width
Phase computing module, intergrade out-phase angle computing module and two-way output stage I, Q computing module, the input stage width mutually calculate mould
Block includes I, Q input terminal, quadrant judging unit and arctangent computation unit；The intergrade out-phase angle computing module includes just
Beginning position judging unit, arc cosine computing unit and phase calculation unit；Output stage I, the Q computing module is divided into structure phase
With two-way, every road include just, cosine computing module and I, Q output.The program uses cordic algorithm as design guidance
Thought only realizes operation by adder, does not use multiplier.The shift unit moves to right fixed digit in each stage, directly
It is realized and is shifted by cabling, do not use logical device.
Wherein, the input stage width phase computing module includes I, Q input terminal, quadrant judging unit and arctangent computation list
Member.The arctangent computation unit is cordic algorithm circuit of the work under vector pattern, mono- by N grades of typical CORDIC
Iteration unit cascade is constituted.Wherein N is related with required output data precision.
Wherein, the intergrade out-phase angle computing module include initial position judging unit, arc cosine computing unit and
Phase calculation unit.The arc cosine computing unit is cordic algorithm electricity improved, that work is under vector pattern
Road is made of the N grades of improved bis- iteration unit cascades of CORDIC.Wherein N is related with required output data precision.
Wherein, two-way output stage I, the Q computing module include completely identical in structure two-way just, sinus computation units
And I1,2、Q1,2Output end.Every road just, sinus computation units be cordic algorithm circuit of the work under rotary mode.Described
The CORDIC processing unit to work under rotary mode is made of the N grades of typical mono- iteration unit cascades of CORDIC.Wherein N and institute
Need output data precision related.
Further, the mono- iteration unit of typical CORDIC, including 3 input, 3 output, 3 adder-subtracters and 2 displacements
Device, 3 inputs are respectively N homophase input xi, N orthogonal input yiAnd N parallactic angle degree inputs ωi, 3 outputs are respectively xiWith
By the y of displacementiThe value x for being added or subtracting each other by adder-subtractero, yiWith the x by displacementiPass through adder-subtracter addition or phase
The value y subtractedoAnd ωiWith the value ω for being added or subtracting each other of known N parallactic angle degreeo, add and subtract and pass through a control code control
System, control code are determined by input；The bis- iteration units of improved CORDIC (502), by the mono- iteration unit grade of two CORDIC
Join and simplify composition, including 4 input, 4 output, 1 comparator, 1 adder, 5 adder-subtracters and 5 shift units, 4 inputs
Respectively N homophase input xi, N orthogonal input yi, N reference value tiAnd N parallactic angle degree inputs ωi；xiWith the y by displacementi
It is added by adder-subtracter or subtracts each other to obtain intermediate result xt, yiWith the x by displacementiIn being added or subtract each other to obtain by adder-subtracter
Between result yt, 4 outputs are respectively xtWith the y by displacementtThe value x for being added or subtracting each other by adder-subtractero, ytIt is moved with passing through
The x of positiontThe value y for being added or subtracting each other by adder-subtractero, tiThe t of itself and process displacementiIt is added or subtracts each other by adder-subtracter
Obtained value toAnd ωtWith the value ω for being added or subtracting each other of known N parallactic angle degreeo, it adds and subtracts through a control code control,
Control code is by inputting xiAnd tiIt is determined by the output of comparator.
Further, the shift unit moves to right fixed digit in each stage, is directly realized and is shifted by cabling, not made
With logical device, resource is not consumed additionally.
Further, it is adopted between the mono- iteration unit of typical CORDIC, the bis- iteration units of improved CORDIC
With the pipeline design, system operational speed is maximized.
A kind of implementation method of fully integrated inexpensive high-speed, high precision Outphasing modulator, the modulator is with cordic algorithm
Based on, including input stage width phase computing module, intergrade out-phase angle computing module and two-way output stage I, Q computing module, tool
Body realizes that steps are as follows:
The first step, input stage width phase computing module calculate the amplitude A and phase angle θ of I, Q road signal S (t) of input: will
(I, Q) transforms to the 1st, 4 quadrants as (I ', Q '), and CORDIC vector pattern is recycled to calculate amplitude(k is
Puppet rotation bring real coefficient) and phase angle
Second step, intergrade out-phase angle computing module (calculate and decompose latter two component S1(t) and S2(t) out-phase angle First with the two-way amount mode computation of CORDIC(R is amplitude output signal, is real coefficient),
Then the quadrant for judging initial (I, Q), if initial position is exported in 1,4 quadrantsIf
Initial position is in the 2nd, 3 quadrants, then
Third step, two-way output stage I, Q computing module calculate separately out S1(t) corresponding I1, Q1And S2(t) corresponding I2,
Q2: it is calculated using CORDIC rotary modeFor
The real coefficient of improving operational speed, above-mentioned all formulas is not involved in practical calculating, in the unified progress of subsequent artificial circuit part
Normalization.Characteristic of the invention is that all operations only use adder, therefore only needs to optimize adder delay
Optimize critical path delay, to reach Millimeter Wave Applications requirement.
Further, the first step input stage width phase computing module calculate I, Q road signal S (t) of input amplitude A and
Phase angle θ, the specific implementation process is as follows: step 11) judges quadrant belonging to (I, Q), if belonging to for the road I, Q signal of input
1,4 quadrant then exports q=0, I '=I, Q '=Q, if belonging to 2,3 quadrants, exports q=1, I '=- I, Q '=- Q, wherein q is
Quadrant mark, logical value are equal to the symbol place value of I；Step 12), it is anti-using I ', Q ', 0 as initial x, y and ω input
In tangent computing unit (401), in each iteration, if yiIt is positive, then xi+1=xi-(yi> > i), yi+1=yi+(xi> > i), quite
In (I ', Q ') around origin pseudo- rotation counterclockwiseAngle, if yiIt is negative, then xi+1=xi+(yi> > i), yi+1=
yi-(xi> > i), (I ', Q ') is equivalent to around origin pseudo- rotation clockwiseAngle, while ωiIn addition rotation angle
Degree, to be positive counterclockwise；After n times iteration, final yNIt is intended to 0, the x of outputNIt is pseudo- rotation band for pseudo- range value kA, k
The real coefficient come, k is intended to 1.646, ω when N > 6NFor phase theta；The pseudo- rotation refers to the amplitude after rotating by a certain angle
With the rotation not waited before rotation.
Further, in the second step, intergrade out-phase angle computing module (calculates and decomposes latter two component S1(t)
And S2(t) out-phase angle The specific implementation process is as follows step 21), seeks the A of inputt0
=A inputs arc cosine computing unit as starting input, and determines initial position, if t0It is greater thanThen first unit vector
It is rotated since x-axis, if t0It is less thanThen first unit vector is rotated since y-axis；It is bis- to carry out N grades of CORDIC for step 22)
Iteration unit operation, if xi<ti, then 2 operations, the 1st x are continuously performedt=xi-(yi> > i), yt=yi+(xi> > i), the 2nd time
xi+1=xt-(yt> > i), yi+1=yt+(xt> > i), first unit vector is equivalent to around origin pseudo- rotation counterclockwiseAngle, if xi≥ti, then 2 operations, the 1st x are continuously performedt=xi+(yi> > i), yt=yi-(xi>>
I), the 2nd xi+1=xt+(yt> > i), yi+1=yt-(xt> > i), first unit vector is equivalent to around origin pseudo- rotation clockwiseAngle；T simultaneouslyi+1=ti+(ti> > 2), ωiIn addition rotation angle, defeated after n times iteration to be positive counterclockwise
ω outNAsStep 23) reads quadrant mark q, if initial position is exported in 1,4 quadrantsIf initial position in the 2nd, 3 quadrants,
Further, in the third step the specific implementation process is as follows, inputFrom the first unit vector in x-axis
Start, carry out the CORDIC iteration 602 of n times rotary mode, the direction of rotation of i-th by i-th iteration ωiIt determines, if ωi
It is positive, then xi+1=xi-(yi> > i), yi+1=yi+(xi> > i), first unit vector is equivalent to around origin pseudo- rotation counterclockwiseAngle, ifIt is negative, then xi+1=xi+(yi> > i), yi+1=yi-(xi> > i), be equivalent to first unit to
Amount is around origin pseudo- rotation clockwiseAngle, while ωiIn addition rotation angle, to be positive counterclockwise.It is final defeated
X outN, yNRespectivelyWithAs corresponding I1,2,Q1,2。
Compared with the prior art, significant effect is the present invention: first, the Outphasing modulator designed through the invention
It is particularly suitable for the millimeter-wave communication system of big baseband bandwidth, the power efficiency of millimeter-wave power amplifiers can be significantly improved.
Second, since cordic algorithm has only used adder, the multiplier for bringing big power consumption, big delay, large area is not used, so
The structure of the Outphasing modulator is more simple, to significantly improve the processing speed of Outphasing modulator, keeps its handling capacity reachable
Sample frequency > 1GHz, while reducing power consumption；Third due to not using lookup table mode to calculate nonlinear function, and calculated
Journey only 3 step, calculation method is simple, any buffer memory is not needed, so that chip area is greatly saved, according to preliminary
Shown in simulation result, area of the invention is that similar device is the smallest, to significantly save production cost；4th, due to
The versatility of cordic algorithm, the present invention program versatility is more preferable, portable more preferable；5th, output data precision and
CORDIC series N is related, and output data error is not more than 2-N+1, high precision may be implemented by increasing N；6th, this hair
It is bright that there are a variety of application methods, it is suitable for a variety of Chireix modulation systems, is produced in addition to connecting I, Q modulator after the third level exports
Outside the application method of raw two-way FM signal, two out-phase angles output that the second level also can be used directly is connected with phase-modulator
The application method for generating two-way FM signal, to omit the third level and two I, Q modulators；7th, compared to traditional mould
Quasi- circuit implementing scheme, the present invention is more flexible due to using digital scheme, and operational precision is higher.In Outphasing modulator
In design, the stationary problem between two-way decomposed signal is even more important, and the synchronizing characteristics of digital circuit is opposite traditional analog again
The big advantage of the one of circuit.Secondly, the dynamic range of digital circuit is bigger compared to analog circuit.The dynamic range of digital operation is by word
It is long to determine, and the dynamic range of analog circuit is then determined by supply voltage.As CMOS technology more refines, supply voltage is not
Disconnected decline, this advantage are further obvious.
Detailed description of the invention
Fig. 1 is the typical performance curve schematic diagram of millimeter wave Linear Power Amplifier.
Fig. 2 is present invention position view in out-phase power amplifying system.
Fig. 3 is each module of the present invention and its functional schematic.
Fig. 4 is input stage width phase computing module schematic diagram of the invention.
Fig. 5 is intergrade out-phase angle computing module structural schematic diagram of the invention.
Fig. 6 is output stage I, Q computing module structural schematic diagram of the invention.
Specific embodiment
For further instruction technical solution disclosed by the invention, make with reference to the accompanying drawings of the specification with specific embodiment
Detailed elaboration.Those skilled in the art should learn, made under the premise of without prejudice to spirit of that invention preferably and improve
Protection scope of the present invention is each fallen within, the conventional means and conventional techniques for this field are not done in detail in this embodiment
Record and explanation.
Embodiment 1: it is suitable for using the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind of the present invention each
Kind electronic device and equipment, including but not limited to, radio frequency sending set, millimeter-wave transmitter, (millimeter wave is wireless for various communication protocols
Communication, 5G wireless communication, orthogonal frequency division multiplex OFDM, wideband code division multiple access CDMA) modulator, digital circuit, Partial Power
Consumable products, electronic test equipment etc..Electronic device includes various integrated circuits, programmable logic device, circuit board, optics
Lattice network or other communication networks, power consumption product include mobile communication terminal, smart phone, computer, Intelligent flat
Computer, video camera, camera, digital camera, portable storage chip, network interface card, wireless network card, multifunction peripheral etc..In addition,
Electronic device further includes the application such as industry, automation equipment.
It is promoted to more specifically describe the technology bring power amplification efficiency, Fig. 1 gives a typical millimeter wave
The output characteristic curve and efficiency curve of Linear Power Amplifier, and tradition I, Q modulate the probability density function curve of input signal.It adopts
With traditional I, in the system of Q modulation scheme, due to the probability density function PDF curve as shown in figure 1 of the modulated signal power of I, Q
Shown, to guarantee output signal, serious distortion, input signal dynamic range are not retracted from saturation interval, lead to output
Mean power is PAVG, efficiency is average efficiency PAEAVG；In system using Outphasing technology, due to input signal amplitude
Constant, the input power of two-way power amplifier may be configured as saturation input power, and output power is saturation output power P at this timeSAT,
Efficiency is maximal efficiency PAESAT.It is not difficult to find out in Fig. 1, whether output power or efficiency, using Outphasing technology
System is better than using tradition I, the system of Q modulation scheme.
Fig. 2 show the out-phase power amplifying system that the present invention is applicable in, and within the system, the present invention will high speed (Gbps)
Baseband I, Q railway digital signal S (t) be decomposed into the signal S of two-way constant amplitude1(t) and S2(t), subsequent IQ modulation module by its
Millimeter-wave frequency is upconverted to, two-way is generated and is carried out with amplitude millimeter-wave signal, then by two-way high efficiency linear power amplifiers
Amplification is synthesized later, is sent.And the difficult point of the technology is setting for ultrahigh speed (Gbps) and high-precision out-of-phase signal modulator
Meter, it is specific as follows, referring to Fig. 3, a kind of fully integrated inexpensive high-speed, high precision Outphasing modulator, based on cordic algorithm,
Including input stage width phase computing module 301, intergrade out-phase angle computing module 302 and two-way output stage I, Q computing module 303,
304, the input stage width phase computing module includes I, Q input terminal, quadrant judging unit and arctangent computation unit 401；Institute
The intergrade out-phase angle computing module stated includes initial position judging unit, arc cosine computing unit 501 and phase calculation unit；
Output stage I, the Q computing module is divided into the identical two-way of structure, every road include just, cosine computing module and I, Q output.
The program uses cordic algorithm as design phiolosophy, only realizes operation by adder, does not use multiplier.Described
Shift unit moves to right fixed digit in each stage, is directly realized and is shifted by cabling, does not use logical device.
Wherein, the input stage width phase computing module includes I, Q input terminal, quadrant judging unit and arctangent computation list
Member.The arctangent computation unit is cordic algorithm circuit of the work under vector pattern, mono- by N grades of typical CORDIC
Iteration unit cascade is constituted.Wherein N is related with required output data precision.
Wherein, the intergrade out-phase angle computing module include initial position judging unit, arc cosine computing unit and
Phase calculation unit.The arc cosine computing unit is cordic algorithm electricity improved, that work is under vector pattern
Road is made of the N grades of improved bis- iteration unit cascades of CORDIC.Wherein N is related with required output data precision.
Wherein, two-way output stage I, the Q computing module include completely identical in structure two-way just, sinus computation units
And I1,2、Q1,2Output end.Every road just, sinus computation units be cordic algorithm circuit of the work under rotary mode.Described
The CORDIC processing unit to work under rotary mode is made of the N grades of typical mono- iteration unit cascades of CORDIC.Wherein N and institute
Need output data precision related.
The mono- iteration unit 402,602 of typical CORDIC, including 3 input, 3 output, 3 adder-subtracters and 2 displacements
Device, 3 inputs are respectively x, N orthogonal input y of N homophase inputs and N parallactic angle degree inputs ω, and 3 outputs are respectively by moving
The value that the x of position is added or is subtracted each other by adder-subtracter with y, what the y by displacement was added or was subtracted each other by adder-subtracter with x
The value for being added or subtracting each other of value and ω and known N parallactic angle degree, plus-minus is by a control code control, and control code is by defeated
Enter to determine；The bis- iteration units 502 of improved CORDIC, are cascaded and are simplified by two mono- iteration units of CORDIC and constitute, and are wrapped
4 inputs 4 output, 1 comparator, 1 adder, 5 adder-subtracters and 5 shift units are included, 4 inputs are respectively N with mutually defeated
Enter x, N orthogonal input y, N reference value t and N parallactic angle degree input ω.X by displacement is added with y by adder-subtracter or phase
Subtract to obtain intermediate result xt, the y by displacement is added by adder-subtracter with x or subtracts each other to obtain intermediate result yt, 4 output difference
To pass through the value that the x of displacement is added or is subtracted each other by adder-subtracter with y, by the y of displacementtAnd xtBy adder-subtracter be added or
The value subtracted each other, the value and ω that the t by displacement is added or is subtracted each other self by adder-subtracter with ttWith it is N known
The addition of angle or the value subtracted each other, plus-minus are determined by a control code control, control code by inputting x and t size.It is described
Shift unit move to right fixed digit in each stage, directly by cabling realize shift, do not use logical device, not additionally consumption money
Source.The pipeline design is used between the mono- iteration unit of typical CORDIC, the bis- iteration units of improved CORDIC, it is maximum
Change system operational speed；Radix-minus-one complement can be used that complement code is replaced to carry out operation in design, is promoted at circuit in the case where sacrificing precision
Manage speed.
Embodiment 2: refering to what is shown in Fig. 2, a kind of fully integrated inexpensive high-speed, high precision Outphasing modulator.It is illustrated in figure 2
The out-phase power amplifying system that the present invention is applicable in, within the system, the present invention baseband I of (Gbps), Q railway digital will be believed at a high speed
Number S (t) is decomposed into the signal S of two-way constant amplitude1(t) and S2(t), subsequent IQ modulation module upconverts it to a millimeter wave frequency
Rate generates two-way and amplifies with amplitude millimeter-wave signal, then by two-way high efficiency linear power amplifiers, synthesizes, sends out later
It send.
Fig. 3 shows internal structure of the invention.The present invention is based on cordic algorithm, including input stage width mutually calculates
Module 301, intergrade out-phase angle computing module 302 and two-way output stage I, Q computing module 303,304, in terms of algorithm level, this
Invention function is divided into three steps: the first step, and input stage width phase computing module (301) calculates I, Q road signal S's (t) of input
Amplitude A and phase angle θ: (I, Q) is transformed into the 1st, 4 quadrants as (I ', Q '), CORDIC vector pattern is recycled to calculate amplitude(k is pseudo- rotation bring real coefficient) and phase angleSecond step, intergrade are different
Phase calculation module (302), which calculates, decomposes latter two component S1(t) and S2(t) out-phase angle First with CORDIC
Two-way amount mode computation(R is amplitude output signal, is real coefficient), then judge initial (I, Q) as
Limit, if initial position is exported in 1,4 quadrantsIf initial position in the 2nd, 3 quadrants,
ThenThird step, two-way output stage I, Q computing module (303,304) are counted respectively
Calculate S1(t) corresponding I1, Q1And S2(t) corresponding I2, Q2: it is calculated using CORDIC rotary modeFor improving operational speed, above-mentioned all formulas
Real coefficient be not involved in practical calculating, be uniformly normalized in subsequent artificial circuit part.Characteristic of the invention is, institute
Some operations only use adder, thus only need to optimize adder delay can optimize critical path delay, with reach milli
Metric wave application requirement.
Input stage width phase computing module structure 301 of the invention is as shown in figure 4, the function that the structure is realized is divided into following 2
A step: the first step judges that quadrant belonging to (I, Q) exports q=0 if belonging to 1,4 quadrants for the road I, Q signal of input,
I '=I, Q '=Q export q=1, I '=- I, Q '=- Q if belonging to 2,3 quadrants, and wherein q is quadrant mark, logical value etc.
In the symbol place value of I.Second step inputs I ', Q ', 0 in arctangent computation unit (401) as initial x, y and ω,
Every grade of single iteration unit CiCircuit structure as indicated at 402, in each iteration, if yiIt is positive, then xi+1=xi-(yi> > i), yi+1
=yi+(xi> > i), (I ', Q ') is equivalent to around origin pseudo- rotation counterclockwiseAngle, if yiIt is negative, then xi+1=
xi+(yi> > i), yi+1=yi-(xi> > i), (I ', Q ') is equivalent to around origin pseudo- rotation clockwiseAngle.Together
When ωiIn addition rotation angle, to be positive counterclockwise.After n times iteration, final yNIt is intended to 0, the x of outputNFor pseudo- amplitude
(k is pseudo- rotation bring real coefficient to value kA, and 1.646) k is intended to when N > 6, ωNFor phase theta.The pseudo- rotation refers to rotation one
Determine the amplitude and the preceding not equal rotation of rotation after angle.
Intergrade out-phase angle 302 structures of computing module of the invention are as shown in Figure 5.The function that the structure is realized is divided into as follows
3 steps: the first step seeks the A of inputt0=A inputs arc cosine computing list as starting input
First (501), and determine initial position, if t0It is greater thanThen first unit vector is rotated since x-axis, if t0It is less thanThen
First unit vector is rotated since y-axis；Second step carries out the bis- iteration unit operations of N grades of CORDIC, every grade of double iteration unit
DCiCircuit structure as shown in Figure 50 2, if xi<ti, then 2 operations, the 1st x are continuously performedt=xi-(yi> > i), yt=yi+
(xi> > i), the 2nd xi+1=xt-(yt> > i), yi+1=yt+(xt> > i), it is pseudo- counterclockwise around origin to be equivalent to first unit vector
RotationAngle, if xi≥ti, then 2 operations, the 1st x are continuously performedt=xi+(yi> > i), yt=yi-(xi
> > i), the 2nd xi+1=xt+(yt> > i), yi+1=yt-(xt> > i), first unit vector is equivalent to around origin pseudo- rotation clockwise
TurnAngle.T simultaneouslyi+1=ti+(ti> > 2), ωiIn addition rotation angle, to be positive counterclockwise, after n times iteration
The ω of outputNAsThird step reads quadrant mark q, if initial position is exported in 1,4 quadrantsIf initial position in the 2nd, 3 quadrants,
Output stage I, Q computing module 303 of the invention, 304 structures are as shown in Figure 6.The module implements function such as: inputSince the first unit vector in x-axis, the CORDIC iteration 602 of n times rotary mode, the direction of rotation of i-th are carried out
By the ω of i-th iterationiIt determines, if ωiIt is positive, then xi+1=xi-(yi> > i), yi+1=yi+(xi> > i), it is equivalent to first unit
Vector is around origin pseudo- rotation counterclockwiseAngle, ifIt is negative, then xi+1=xi+(yi> > i), yi+1=yi-
(xi> > i), first unit vector is equivalent to around origin pseudo- rotation clockwiseAngle, while ωiIn addition rotation
Angle, to be positive counterclockwise.The x of final outputN, yNRespectivelyWithAs corresponding I1,2,Q1,2。
It should be noted that above-described embodiment is only presently preferred embodiments of the present invention, there is no for the purpose of limiting the invention
Protection scope, the equivalent substitution or substitution made based on the above technical solution all belong to the scope of protection of the present invention.
Claims (9)
1. a kind of fully integrated inexpensive high-speed, high precision Outphasing modulator, it is characterised in that: high-speed, high precision Outphasing modulator packet
Include input stage width phase computing module (301), intergrade out-phase angle computing module (302) and two-way output stage I, Q computing module
(303,304), intergrade out-phase angle computing module (302) setting are defeated in input stage width phase computing module (301) and two-way
Out between grade I, Q computing module (303,304), the input stage width phase computing module includes I, Q input terminal, quadrant judging unit
With arctangent computation unit (401), intergrade out-phase angle computing module includes initial position judging unit, arc cosine computing
Unit (501) and phase calculation unit, two-way output stage I, the Q computing unit include completely identical in structure two-way just,
Sinus computation units (601) and I1,2、Q1,2Output end.
2. the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 1, it is characterised in that: described
Input stage width phase computing module (301) includes I, Q input terminal, quadrant judging unit and arctangent computation unit (401), described anti-
Tangent computing unit is cordic algorithm circuit of the work under vector pattern, by the N grades of mono- iteration units of typical CORDIC
(402) cascade is constituted, and wherein N is related with required output data precision.
3. the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 2, it is characterised in that: described
Intergrade out-phase angle computing module (302) includes initial position judging unit, arc cosine computing unit (501) and phase calculation list
Member；The arc cosine computing unit is cordic algorithm circuit improved, that work is under vector pattern, is improved by N grades
The bis- iteration units of CORDIC (502) cascade constitute, wherein N is related with required output data precision.
4. the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 3, it is characterised in that: described
Two-way output stage I, Q computing module (303,304) include completely identical in structure two-way just, sinus computation units (601) and
I1,2、Q1,2Output end, every road just, sinus computation units be cordic algorithm circuit of the work under rotary mode, the work
CORDIC processing unit under rotary mode is made of the N grades of mono- iteration units of typical CORDIC (602) cascades, wherein N and
Required output data precision is related.
5. the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 3 or 4, it is characterised in that:
The mono- iteration unit of typical CORDIC (402,602), including 3 input, 3 output, 3 adder-subtracters and 2 shift units, 3 defeated
Enter respectively N homophase input xi, N orthogonal input yiAnd N parallactic angle degree inputs ωi, 3 outputs are respectively xiIt is shifted with passing through
YiThe value x for being added or subtracting each other by adder-subtractero, yiWith the x by displacementiIt is added or subtracts each other by adder-subtracter
Value yoAnd ωiWith the value ω for being added or subtracting each other of known N parallactic angle degreeo, add and subtract through a control code control, control code
It is determined by input；The bis- iteration units of improved CORDIC (502) are cascaded by two mono- iteration units of CORDIC and simplify structure
At, including 4 input, 4 output, 1 comparator, 1 adder, 5 adder-subtracters and 5 shift units, 4 inputs are respectively N same
Mutually input xi, N orthogonal input yi, N reference value tiAnd N parallactic angle degree inputs ωi；xiWith the y by displacementiPass through adder-subtracter
It is added or subtracts each other to obtain intermediate result xt, yiWith the x by displacementiIt is added by adder-subtracter or subtracts each other to obtain intermediate result yt, 4
A output is respectively xtWith the y by displacementtThe value x for being added or subtracting each other by adder-subtractero, ytWith the x by displacementtPass through
The value y that adder-subtracter is added or subtracts each othero, tiThe t of itself and process displacementiThe value t for being added or subtracting each other by adder-subtractero,
And ωtWith the value ω for being added or subtracting each other of known N parallactic angle degreeo, plus-minus is by a control code control, and control code is by defeated
Enter xiAnd tiIt is determined by the output of comparator.
6. using the realization of the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind described in claim 1-5 any one
Method, based on the modulator cordic algorithm, including input stage width phase computing module 301, the different phase calculation mould of intergrade
Block and two-way output stage I, Q computing module, the specific implementation steps are as follows:
The first step, input stage width phase computing module (301) calculate the amplitude A and phase angle θ of I, Q road signal S (t) of input: will
(I, Q) transforms to the 1st, 4 quadrants as (I ', Q '), and CORDIC vector pattern is recycled to calculate amplitude(k is
Puppet rotation bring real coefficient) and phase angle
Second step, intergrade out-phase angle computing module (302), which calculates, decomposes latter two component S1(t) and S2(t) out-phase angleFirst with the two-way amount mode computation of CORDIC(R is amplitude output signal, is real coefficient),
Then the quadrant for judging initial (I, Q), if initial position is exported in 1,4 quadrants If
Initial position is in the 2nd, 3 quadrants, then
Third step, two-way output stage I, Q computing module (303,304) calculate separately out S1(t) corresponding I1, Q1And S2(t) corresponding
I2, Q2: it is calculated using CORDIC rotary mode
7. the implementation method of the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 6, special
Sign is that the first step input stage width phase computing module (301) calculates the amplitude A and phase of I, Q road signal S (t) of input
Angle θ, the specific implementation process is as follows: step 11) judges quadrant belonging to (I, Q), if belonging to 1,4 for the road I, Q signal of input
Quadrant then exports q=0, I '=I, Q '=Q, if belonging to 2,3 quadrants, exports q=1, I '=- I, Q '=- Q, wherein q be as
Limit mark, logical value are equal to the symbol place value of I；Step 12), anyway using I ', Q ', 0 as initial x, y and ω input
It cuts in computing unit (401), in each iteration, if yiIt is positive, then xi+1=xi-(yi> > i), yi+1=yi+(xi> > i), it is equivalent to
(I ', Q ') is around origin pseudo- rotation counterclockwiseAngle, if yiIt is negative, then xi+1=xi+(yi> > i), yi+1=yi-
(xi> > i), (I ', Q ') is equivalent to around origin pseudo- rotation clockwiseAngle, while ωiIn addition rotation angle,
To be positive counterclockwise；After n times iteration, final yNIt is intended to 0, the x of outputNIt is that pseudo- rotation is brought for pseudo- range value kA, k
Real coefficient, k is intended to 1.646, ω when N > 6NFor phase theta.
8. the implementation method of the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 7, special
Sign is, in the second step, intergrade out-phase angle computing module (302), which calculates, decomposes latter two component S1(t) and S2(t)
Out-phase angleThe specific implementation process is as follows step 21), seeks the A of inputt0=A makees
It for starting input, inputs arc cosine computing unit (501), and determines initial position, if t0It is greater thanThen first unit vector
It is rotated since x-axis, if t0It is less thanThen first unit vector is rotated since y-axis；It is bis- to carry out N grades of CORDIC for step 22)
Iteration unit operation, if xi<ti, then 2 operations, the 1st x are continuously performedt=xi-(yi> > i), yt=yi+(xi> > i), the 2nd time
xi+1=xt-(yt> > i), yi+1=yt+(xt> > i), first unit vector is equivalent to around origin pseudo- rotation counterclockwiseAngle, if xi≥ti, then 2 operations, the 1st x are continuously performedt=xi+(yi> > i), yt=yi-(xi> > i), the 2nd
Secondary xi+1=xt+(yt> > i), yi+1=yt-(xt> > i), first unit vector is equivalent to around origin pseudo- rotation clockwiseAngle；T simultaneouslyi+1=ti+(ti> > 2), ωiIn addition rotation angle is exported after n times iteration with being positive counterclockwise
ωNAsStep 23) reads quadrant mark q, if initial position is exported in 1,4 quadrants
If initial position in the 2nd, 3 quadrants,
9. the implementation method of the fully integrated inexpensive high-speed, high precision Outphasing modulator of one kind according to claim 8, special
Sign is, the specific implementation process is as follows, inputs in the third stepSince the first unit vector in x-axis, N is carried out
The CORDIC iteration 602 of secondary rotary mode, the direction of rotation of i-th by i-th iteration ωiIt determines, if ωiIt is positive, then xi+1
=xi-(yi> > i), yi+1=yi+(xi> > i), first unit vector is equivalent to around origin pseudo- rotation counterclockwise
Angle, ifIt is negative, then xi+1=xi+(yi> > i), yi+1=yi-(xi> > i), first unit vector is equivalent to around origin
Pseudo- rotation clockwiseAngle, while ωiIn addition rotation angle, to be positive counterclockwise.The x of final outputN, yNPoint
It is notWithAs corresponding I1,2,Q1,2。
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| CN1883110A (en) * | 2003-11-25 | 2006-12-20 | 英特尔公司 | Outphasing modulator |
| CN101977176A (en) * | 2010-10-12 | 2011-02-16 | 浙江大学 | Method for realizing general demodulation of different modulating signals |
| CN106506014A (en) * | 2015-09-06 | 2017-03-15 | 中兴通讯股份有限公司 | Transmitter and signal output method |
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| CN1883110A (en) * | 2003-11-25 | 2006-12-20 | 英特尔公司 | Outphasing modulator |
| CN101977176A (en) * | 2010-10-12 | 2011-02-16 | 浙江大学 | Method for realizing general demodulation of different modulating signals |
| CN106506014A (en) * | 2015-09-06 | 2017-03-15 | 中兴通讯股份有限公司 | Transmitter and signal output method |
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| CN113595681A (en) * | 2021-06-28 | 2021-11-02 | 展讯半导体(南京)有限公司 | QR decomposition method, system, circuit, equipment and medium based on Givens rotation |
| CN113595681B (en) * | 2021-06-28 | 2022-10-04 | 展讯半导体(南京)有限公司 | QR decomposition method, system, circuit, equipment and medium based on Givens rotation |
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