CN104348772A - Parameter separation predistorter - Google Patents

Abstract

The invention provides a parameter separation predistorter, and belongs to the technical field of wireless communication. The parameter separation predistorter comprises an amplitude value extraction module, a core finding table obtaining and calling unit, a complex multiplication module, a complex addition module and a DSP (digital signal processor), wherein the core finding table obtaining and calling unit is an RAM (random access memory), the amplitude value extraction module, the core finding table obtaining and calling unit, the complex multiplication module and the complex addition module are all integrated on an FPGA (field programmable gate array), finding table data is written into the DSP, the DSP inputs the finding table data into the RAM on the FPGA through a data bus, and the finding table data in the RAM is read in real time through amplitude values indexes obtained by the amplitude value extraction module. The parameter separation predistorter has the advantages that the traditional digital predistorter is subjected to parameter and structure separation, so the development process of the predistorter is simplified, and the development efficiency and the practicability are improved.

Description

A kind of predistorter of parameters separated

Technical field

The invention belongs to wireless communication technology field, particularly the linearization technique of power amplifier, be specially a kind of predistorter of parameters separated.

Background technology

In a wireless communication system, the effect of transmitter intermediate power amplifier is more and more important, and wireless communication system requires more and more higher to the signal to noise ratio of signal, and the nonlinear characteristic of power amplifier is the key factor affecting signal transmission signal to noise ratio.Due to the impact of non-linearity of power amplifier characteristic, band-limited signal is by producing the phenomenon of spread spectrum during power amplifier, i.e. generating strap external spectrum, the signal to noise ratio of influence zone external signal, the Adjacent Channel Power Ratio (ACPR) of various wireless communication standard to Signal transmissions all has concrete requirement, in order to make wireless communication system meet requirement for ACPR in radio communication, need to do nonlinear compensation to power amplifier, with the requirement making it meet linear work.Only improve the linear index of power amplifier, the noise Bizet of wireless signal transmission can improve, thus realizes the requirement meeting each wireless communication standard.

Digital pre-distortion technology is one of major technique improving power amplifier linearity at present, particularly for the wireless communication signals in future, due to the popularization of non-constant envelope modulation schemes, the peak-to-average force ratio of signal increases, and just has higher requirement to the linearity index of power amplifier.Digital pre-distortion technology in the linearization technique of various power amplifier, because the advantages such as its good stability, bandwidth are unrestricted, easy realization are widely used.Traditional digital pre-distortion FPGA implementation structure for memory polynomial algorithm as shown in Figure 1, baseband signal enters predistorter by I paths and Q paths, cordic algorithm (Coordinate Rotation Digital computational methods) is used to obtain the amplitude of input signal, by the corresponding pre-distortion parameters of amplitude index search, after loop time delay alignment and summation, export base-band pre-distorted signal by after each time memory term signal transacting, be then mixed to radiofrequency signal and input power amplifier thus the linearisation object realizing power amplifier.Predefine parameter required for conventional digital predistorter and implementation structure all realize in FPGA, the implementation structure of predistorter solidifies at FPGA, and predistorter corresponding to different power amplifiers is different, even the power amplifier of identical type, the predistorter of its correspondence also can be had any different because parameter is slightly different, therefore different power amplifiers needs the program of each change FPGA with the linear optimization effect of adjustment System, and the compiling debugging flow process of FPGA program is loaded down with trivial details, very consuming time, and only realize in FPGA pre-distorter structure and parameter be separated can not improve digital predistorter can development process, this just makes the process realizing pre-distorter structure more complicated, add R&D costs and hardware cost.Therefore, how to improve the practicality of predistorter and development efficiency, the R&D costs of reduction predistorter become problem demanding prompt solution.

Summary of the invention

The present invention is directed to the defect that background technology exists, propose a kind of predistorter of parameters separated, by traditional digital predistorter being carried out being separated of parameter and structure, thus simplifying the development process of predistorter, improve development efficiency and practicality.

A kind of predistorter of parameters separated, comprise magnitude extraction module, core look-up table obtains and call unit, complex multiplication module, complex addition module and the DSP for store look-up tables data, it is RAM memory that described core look-up table obtains with call unit, described magnitude extraction module, core look-up table obtains and call unit, complex multiplication module and complex addition module are all integrated on FPGA, look-up table data writes in described DSP, look-up table data to be injected the RAM memory on FPGA by described DSP by data/address bus, according to the amplitude index that described magnitude extraction module obtains, the look-up table data in RAM memory is read in real time.

A pre-distortion method for parameters separated, comprises the following steps:

Step 1: first obtain with call unit, complex multiplication module and complex addition module integration on FPGA by magnitude extraction module, core look-up table, it is RAM memory that wherein said core look-up table obtains with call unit;

Step 2: look-up table data write in DSP, then injects the core look-up table acquisition of FPGA and the RAM memory of call unit by data/address bus by the look-up table data in DSP in real time;

Step 3: input signal U (n) obtains amplitude after magnitude extraction module | U (n) |, utilize the look-up table data in RAM memory in amplitude index search step 2, and after complex multiplication module, obtain U (n) G with input signal U (n) ₀(| U (n) |), wherein n is the moment that signal is corresponding;

Step 4: input signal U (n) time delay obtains U (n-1), U (n-2), U (n-M+1), | U (n) | time delay obtains | U (n-1) |, | U (n-2) |, | U (n-M+1) |, utilize the look-up table data in RAM memory in amplitude index search step 2, and with U (n-1), U (n-2) ... U (n-M+1) obtains U (n-1) G after complex multiplication module ₁(| U (n-1) |), U (n-2) G ₂(| U (n-2) |) ... U (n-M+1) G _m-1(| U (n-M+1) |), wherein, n=1,2,3..., and n is the moment that signal is corresponding, M is model memory depth, M=1,2,3 ...

Step 5: U (n) G that step 3 is obtained ₀all signals that (| U (n) |) signal and step 4 obtain after complex multiplication module are by obtaining pre-distorted signals X (n) exported after complex addition module.

Beneficial effect of the present invention is: the present invention is by being separated traditional digital predistorter parameter with structure, Structured cured in FPGA by predistorter, the storage of the process of identified parameters and parameter, transfer function are placed in DSP, fundamentally change predistorter poor practicability, construction cycle long problem.Structured cured in FPGA by predistorter of the present invention, reduces the resource occupation of pre-distorter structure, makes this predistorter be applicable to use this type of pre-distorter structure to carry out linearizing nearly all power amplifier; Simultaneously, parameters separated makes to improve predistorter practicality becomes possibility, the pre-distortion parameters picked out (look-up table data) is write in DSP program, during system works, pre-distortion parameters is injected predistorter by the high speed data bus passage between FPGA by DSP, complete the combination of structure and parameter, thus realize the function of predistorter; The present invention can realize the renewal of predistorter to the renewal of parameter, greatly simplifies development process, improves development efficiency, improves the practicality of predistorter; Look-up table data writes in DSP program by the present invention, and because DSP development process is simple, C language is transplanted convenient, further increases the development efficiency of predistorter

Accompanying drawing explanation

Fig. 1 is traditional predistortion FPGA implementation structure for memory polynomial algorithm;

Fig. 2 be the present invention propose realize the suitable topology diagram of the digital predistorter of pre-distorter structure and parameters separated based on FPGA+DSP platform;

A kind of Wireless Telecom Equipment implementation structure figure be applied under certain occasion that Fig. 3 is that technical scheme that application the present invention of providing of the embodiment of the present invention proposes is improved.

Embodiment

In order to make object, the technical scheme of the embodiment of the present invention clearly understand, with reference to the embodiment of the present invention and accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously; embodiment described herein is a part of embodiment of the present invention, instead of whole embodiments, based on the embodiment in the present invention; those skilled in the art, not making the every other embodiment obtained under creative work prerequisite, belongs to the scope of protection of the invention.

Be illustrated in figure 2 and provided by the inventionly realize predistorter knot hook based on FPGA+DSP platform and parameters separated improves the topology diagram of the digital predistorter of power amplifier.As shown in Figure 2, pre-distorter structure provided by the invention mainly comprises:

Magnitude extraction module, carries out magnitude extraction to the baseband signal of input, sets up with this index that predistorter searches table (LUT).Magnitude extraction module realizes by cordic algorithm the amplitude extracting base band I/Q signal in FPGA.Magnitude extraction module is made up of three parts: 1) pretreatment module, forwards the complex signal at 2 and 3 quadrants to 1,4 quadrants by preliminary treatment; 2) cordic algoritic module, by the rotation of n time, by signal rotation in x-axis, and now x coordinate is the amplitude of signal, and y coordinate is zero, and in actual applications, n is generally 14, can ensure the precision of signal amplitude; 3) gain compensation block, the result obtained due to Rotation Algorithm and actual result have the gain relationship of 1.6468 times, therefore carry out gain compensation by this module, make Output rusults equal with actual margin.Wherein, in FPGA, ask the amplitude of complex signal to adopt cordic algorithm, the thinking of cordic algorithm is: the anglec of rotation obtaining plane vector θ if want, this angle θ is just needed to decompose, then a basic angle is specified, go to approach vector by this basic angle by the method for linear approximation, its advantage only needs simply to be shifted and to add reducing to complete cartesian coordinate to polar conversion, and FPGA is the most applicable is shifted and plus and minus calculation.

Core look-up table obtains and call unit, comprise RAM memory, high speed data bus is adopted the look-up table data in the write DSP of renewal to be injected in real time the RAM memory of FPGA, by amplitude index, the look-up table in RAM memory is read in real time during predistorter work, realize the linearisation object of predistortion.Described core look-up table obtains with call unit as pre-distorted signals process provides gain factor, look-up table addressing is carried out by amplitude module, make its signal and factor one_to_one corresponding, this module comprises 4 asynchronous RAM of twoport, the real part of difference control signal, memory term and imaginary part; Holder is synchronoused working by the control signal of a 64K with DSP, the data of corresponding address in DSP periodic refreshing RAM memory.Compared with the look-up table of traditional structure, look-up table data of the present invention leaves in RAM memory, not only save a large amount of ROM resources, achieve being separated of pre-distorter structure and parameter simultaneously, predistorter parameter is upgraded and becomes simple, avoid the complicated and loaded down with trivial details compiling of FPGA, the step such as comprehensive, improve the applicability of predistorter.

Complex multiplication module, is multiplied non-delayed item, each time delay item with corresponding pre-distortion parameters and obtains the pre-distorted signals of non-delayed item and each time delay item.Described complex multiplication module is by the corresponding fac-tor of multiplier by signal and look-up table, and by real part and imaginary part correspondence separately, multiplier remains all bit wides that multiplier exports, and prevents the inaccuracy of Output rusults; High-order sign bit retains by the final stage of multiplier, under the counting prerequisite of complement code, do not affect the accurate of data.Because non-delayed item, each time delay item and pre-distortion parameters are all plural number, use this complex multiplication module can realize the function of complex multiplication.

Complex addition module, carries out being added non-delayed item can obtain base-band pre-distorted signal with the pre-distorted signals of each time delay item.The real part of signal and its memory term and imaginary part correspondence are added up by described complex addition module, the result completing memory polynomial exports, and adder considers the spilling of signal, therefore is all added by 32 signals, when in conjunction with actual signal amplitude size, retain suitable symbol figure place; The end of adder is an interception module, and signal is carried out process of condensing, and under the prerequisite of suitably losing certain precision, stick signal polarity, intercepts suitable bit wide and exports.

Concrete, during predistorter work of the present invention, pre-distortion parameters is injected the RAM memory of FPGA by DSP by high speed data bus.Baseband signal is by I paths and Q paths is wide enters predistorter, FPGA obtains the amplitude of I/Q signal by cordic algorithm, according to look-up table parameter in amplitude index RAM memory, after time delay alignment, memoryless item and pre-distortion parameters realize pre-distortion in complex multiplication module.Similar, for each memory term, according to the parameter in corresponding look-up table in the amplitude index RAM memory of the I/Q signal after delay at different levels, after time delay alignment, pre-distortion is carried out to each memory term.Memoryless item and the pre-distorted signals of each memory term are obtained after complex addition module is added the pre-distorted signals of baseband signal, and then realize the linearisation object of power amplifier.

Predistorter model adopts memory polynomial model. and memory polynomial model expression is:

$x\left(n\right)=\underset{m=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{a}_{\mathrm{mk}}U(n-m)|U(n-m){|}^k---\left(1\right)$

In formula (1), x (n) is the output signal of n moment predistorter, and n is the moment that signal is corresponding, n=1,2,3....In formula, m=0,1 ..., M-1, M are model memory depth, represent that model is memoryless, k=1 during M=1 ..., K, K are model nonlinear exponent number, a _mkfor the coefficient under corresponding memory depth and non-linear exponent number, the input signal that U (n-m)=I (n-m)+jQ (n-m) is the n-m moment, signal is the complex signal under quadrature modulation mode, I is the real part of input signal, Q is the imaginary part of input signal, | U (n-m) | be the amplitude of n-m moment input signal.

Memory polynomial model is converted, can obtain:

$\begin{array}{c}x\left(n\right)=\underset{m=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{k=1}{\overset{K}{\mathrm{\Σ}}}{a}_{\mathrm{mk}}U(n-m)|U(n-m){|}^k\\ =\underset{m=0}{\overset{M-1}{\mathrm{\Σ}}}U(n-m)\left(a_{\mathrm{mk}}\underset{k=1}{\overset{K}{\mathrm{\Σ}}}\right|U(n-m){|}^k)\\ =U\left(n\right)G_0\left(\right|U\left(n\right)\left|\right)+...+U(n-m)G_m\left(\right|U(n-m)\left|\right)+...+U(n-M+1)G_{M-1}\left(\right|U(n-M+1)\left|\right)\end{array}---\left(2\right)$

In formula (2): for input signal U (n) function G according to correspondence in different amplitude situation _mthe value that () obtains, be stored in corresponding look-up table (LUT_m) respectively, due to look-up table value only with | U (n-m) | and corresponding memory depth is relevant, so look-up table be M with amplitude | U (n-m) | be the memory of index.

Embodiment

Certain Wireless Telecom Equipment needs to use different transmitting powers under different working modes, for this reason, the Equipments Setting power amplifier of different operating frequency, the predistorter of each power amplifier adopts same structure (this example adopts the predistorter of memory polynomial structure), the technical scheme adopting the present invention to propose, uses a predistorter can complete linearisation to different capacity amplifier.

As shown in Figure 3, certain equipment need launch the bandwidth modulated signals of different carrier frequencies: the operating frequency of power amplifier A is 1.8GHZ, the operating frequency of power amplifier B is 2.0GHZ, the operating frequency of power amplifier C is 2.14GHZ, under power amplifier A, B, C work in the different mode of system, for realizing this object, need through following three steps:

1, the extraction of pre-distortion parameters (look-up table data): behavior modeling is carried out to power amplifier A, B, C and its pre-distortion parameters of identification, mainly comprise the following steps:

(1) sample with the input/output signal of fixed sample rate to each power amplifier;

(2) time delay alignment is carried out to each output data sampled;

(3) Confirming model adopt memory depth and non-linear exponent number, utilize least-squares algorithm (LS) or recursive least squares (RLS) scheduling algorithm respectively to each power amplifier modeling, its model parameter of identification;

(4) verify the correctness of each power amplifier model, if incorrect or do not meet technical indicator, then re-execute step (3);

(5) each power amplifier behavior model is inverted, the pre-distortion parameters needed for each power amplifier of identification;

(6) pre-distortion parameters obtained is quantized, generate corresponding predistortion lookup table, stored in DSP.

2, predistortion architecture solidification

For reaching device specifications, the memory depth that power amplifier A, B, C behavior model adopts and non-linear exponent number are respectively:

Power amplifier A: memory depth M=1, non-linear exponent number K=7;

Power amplifier B: memory depth M=2, non-linear exponent number K=7;

Power amplifier C: memory depth M=3, non-linear exponent number K=9;

Thus, the number of predistorter desired seek table mostly is 6 tables most, and every two to show the store-memory degree of depth be respectively 0, and memory depth is 1, and memory depth is the pre-distortion parameters of 2.Wherein, two corresponding under each memory depth tables store real part and the imaginary part of the pre-distortion parameters under each memory depth respectively.

During predistorter work, pre-distortion parameters is injected the RAM memory of FPGA in real time by high speed data bus by DSP, FPGA reads the pre-distortion parameters needed for RAM memory fetch in real time.

Write the FPGA program realizing predistorter, in RAM memory, reserved location is used for depositing predistortion lookup table, the look-up table number used in this example be 6 (use less than look-up table parameter note 0), compiling, comprehensive after by download program in FPGA, realize the solidification of pre-distorter structure.

3, the functional realiey of predistorter

The structure and parameter of predistorter is separated, the applicability of predistorter can be improved; The structure and parameter of predistorter is combined, can predistortion function be realized.

In this device, mode of operation is determined by master control DSP.As shown in Figure 3, DSP, according to device interior and external condition determination mode of operation, select different power amplifiers to amplify signal, and then the linear optimization effect requiring predistorter to realize will change accordingly under different mode of operations.

Concrete, after master control DSP determines mode of operation, by high speed data bus, pre-distortion parameters corresponding for the power amplifier be in work is injected FPGA, FPGA sends into corresponding power amplifier by after the upconvert baseband signals that pre-distortion is crossed by radio-frequency (RF) switch, launch after amplification, filtering, realize complete machine function.

Show particularly with reference to embodiment and describe the present invention above, for one of ordinary skill in the art, according to the thought of the embodiment of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (2)

1. the predistorter of a parameters separated, comprise magnitude extraction module, core look-up table obtains and call unit, complex multiplication module, complex addition module and the DSP for store look-up tables data, it is RAM memory that described core look-up table obtains with call unit, described magnitude extraction module, core look-up table obtains and call unit, complex multiplication module and complex addition module are all integrated on FPGA, look-up table data writes in described DSP, look-up table data to be injected the RAM memory on FPGA by described DSP by data/address bus, according to the amplitude index that described magnitude extraction module obtains, the look-up table data in RAM memory is read in real time.

2. a pre-distortion method for parameters separated, comprises the following steps:

Step 1: first obtain with call unit, complex multiplication module and complex addition module integration on FPGA by magnitude extraction module, core look-up table, it is RAM memory that wherein said core look-up table obtains with call unit;

Step 2: look-up table data write in DSP, then injects the core look-up table acquisition of FPGA and the RAM memory of call unit by data/address bus by the look-up table data in DSP in real time;

Step 3: input signal U (n) obtains amplitude after magnitude extraction module | U (n) |, utilize the look-up table data in RAM memory in amplitude index search step 2, and after complex multiplication module, obtain U (n) G with input signal U (n) ₀(| U (n) |), wherein n is the moment that signal is corresponding;

Step 4: input signal U (n) time delay obtains U (n-1), U (n-2), U (n-M+1), | U (n) | time delay obtains | U (n-1) |, | U (n-2) |, | U (n-M+1) |, utilize the look-up table data in RAM memory in amplitude index search step 2, and with U (n-1), U (n-2), U (n-M+1), after complex multiplication module, obtains U (n-1) G ₁(| U (n-1) |), U (n-2) G ₂(| U (n-2) |) ... U (n-M+1) G _m-1(| U (n-M+1) |), wherein, n=1,2,3..., and n is the moment that signal is corresponding, M is model memory depth;

Step 5: U (n) G that step 3 is obtained ₀all signals that (| U (n) |) signal and step 4 obtain after complex multiplication module are by obtaining pre-distorted signals X (n) exported after complex addition module.