CN110429985B

CN110429985B - Fully-integrated low-cost high-speed high-precision out-of-phase modulator

Info

Publication number: CN110429985B
Application number: CN201810463878.7A
Authority: CN
Inventors: 赵涤燹; 李迪威
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2018-05-15
Filing date: 2018-05-15
Publication date: 2022-12-09
Anticipated expiration: 2038-05-15
Also published as: CN110429985A

Abstract

The invention discloses a fully-integrated low-cost high-speed high-precision outphasing modulator which can decompose one path of high-speed (sampling frequency is more than 1 GHz) digital baseband signal of amplitude modulation and phase modulation (such as QAM, OFDM and the like) into two paths of constant envelope phase modulation signals, and greatly improve the power efficiency and the output power of a millimeter wave power amplification system under the condition of ensuring the linearity. The high-speed outphasing modulator consists of an input stage amplitude-phase calculation module, an intermediate stage outphasing angle calculation module and two output stage I and Q calculation modules. The high-speed outphasing modulator is realized based on a CORDIC algorithm, the precision can be improved by adjusting the iteration times, the CORDIC algorithm only uses an adder to realize operation, a multiplier is not used, table lookup is not needed, the throughput rate is improved, the area on a chip is reduced, and the manufacturing cost can be greatly reduced based on CMOS and other chip manufacturing processes.

Description

Fully-integrated low-cost high-speed high-precision outphasing modulator

Technical Field

The invention relates to a fully-integrated low-cost high-speed high-precision outphasing modulator, belongs to the technical field of electronic circuit design, and is particularly suitable for ultrahigh-speed digital circuit design and power amplifier design in a millimeter wave system.

Background

The 5G era is moving, and millimeter wave wireless systems are becoming increasingly attractive due to the many advantages of millimeter waves. In millimeter wave high-speed data transmission, a millimeter wave linear power amplifier is indispensable. However, millimeter wave power amplifier design is facing a huge challenge-large power consumption and low efficiency.

Out-phase modulation (Outphasing) is a promising technique for improving the efficiency of millimeter wave power amplifiers. The key point of the technology lies in that a signal (such as a baseband digital signal generated by modulation of QAM, OFDM and the like) with constantly changing amplitude and phase is decomposed into two phase modulation signals with constant envelopes and changing phases, the two paths of signals are respectively subjected to power amplification, and finally, the original signal is synthesized. Therefore, the linearity requirement of the two power amplifiers can be reduced, and the working range of the two power amplifiers is close to the saturation region of the transistor, so that high output power and high power efficiency are achieved. Existing power amplifiers employing outphasing modulation techniques can achieve approximately 10% efficiency improvement.

However, the technology needs a high-speed high-precision outphasing modulator, and it is a difficult point of the technology to decompose the ultra-high-speed (GSample/s) baseband digital signal used in the millimeter wave communication system into two outphasing signals with equal amplitudes and different phases.

Disclosure of Invention

In recent years, with the development of millimeter wave communication technology, the requirement on the efficiency of a millimeter wave power amplifier is higher and higher, and meanwhile, the large bandwidth characteristic of millimeter waves requires a high-speed (sampling frequency > 1 GHz) digital processing rate, so that the invention needs to solve the two technical problems.

The bottleneck that the existing millimeter wave linear power amplifier is difficult to realize high efficiency is that the power amplifier works near the saturation region of the transistor to have high efficiency according to the characteristics of the linear power amplifier, but the linearity is poor near the saturation region, so that the output signal is distorted. Therefore, the dynamic range of the existing millimeter wave power amplifier is backed off from the 1dB compression point to ensure good linearity. However, the back-off brings about a reduction in the peak-to-average power ratio (PAPR) of the output signal, thereby causing a reduction in output power and power efficiency.

The out-phase modulation technology decomposes an input signal with variable amplitude and phase into two branch signals with constant amplitude and variable phase, so that two millimeter wave power amplifiers continuously work near a saturation region, the output efficiency of the power amplifiers is greatly improved (about 10 percent), the output power is greatly improved, and good linearity is ensured.

In order to achieve the purpose, the invention adopts the following technical scheme:

a fully-integrated low-cost high-speed high-precision outphasing modulator is based on a CORDIC algorithm and comprises an input stage amplitude and phase calculation module, an intermediate stage outphasing angle calculation module and two output stage I and Q calculation modules, wherein the input stage amplitude and phase calculation module comprises an I input end, a Q input end, a quadrant judgment unit and an arctangent calculation unit; the intermediate-stage out-phase angle calculation module comprises an initial position judgment unit, an inverse cosine calculation unit and a phase calculation unit; the output stage I and Q computing modules are divided into two paths with the same structure, and each path comprises a sine computing module, a cosine computing module, an I output end and a Q output end. The scheme uses a CORDIC algorithm as a design guiding idea, realizes operation only through an adder and does not use a multiplier. The shifter shifts right in each stage by a fixed bit number, directly realizes shifting through wiring, and does not use a logic device.

The input stage amplitude and phase calculation module comprises I and Q input ends, a quadrant judgment unit and an arc tangent calculation unit. The arctangent computing unit is a CORDIC algorithm circuit working in a vector mode and is formed by cascading N stages of typical CORDIC single iteration units. Where N is related to the required accuracy of the output data.

The intermediate-stage out-phase angle calculation module comprises an initial position judgment unit, an inverse cosine calculation unit and a phase calculation unit. The said inverse cosine computing unit is improved CORDIC algorithm circuit working in vector mode, and is formed by N stages of improved CORDIC double-iteration units in cascade connection. Where N is related to the required output data accuracy.

The two output stage I and Q computing modules comprise two sine and cosine computing units with the same structure and I _1,2 、Q _1,2 And (4) an output end. Each path of sine and cosine computing unit is a CORDIC algorithm circuit working in a rotating mode. The CORDIC processing unit working in the rotating mode is formed by cascading N stages of typical CORDIC single iteration units. Where N is related to the required output data accuracy.

Furthermore, the typical CORDIC single iteration unit comprises 3 inputs and 3 outputs, 3 adders and 2 shifters, wherein the 3 inputs are respectively an N-bit in-phase input x _i N-bit quadrature input y _i And N-bit angle input omega _i And 3 outputs are each x _i And shifted y _i Value x added or subtracted by an adder-subtractor _o ，y _i And shifted x _i Value y added or subtracted by an adder-subtractor _o And ω _i And the value ω obtained by addition or subtraction of a known N-bit angle _o The addition and subtraction are controlled by a one-bit control code, and the control code is determined by input; the improved CORDIC double-iteration unit (502) is formed by two CORDIC single-iteration units in a cascaded and simplified mode and comprises 4 inputs and 4 outputs, 1 comparator, 1 adder, 5 adders and 5 shifters, wherein the 4 inputs are respectively N-bit in-phase inputs and x is the same as the input of the comparator, and the adder, the adder and the adder are connected in series and are connected in parallel to form a single-phase input circuit, and the single-phase input circuit is connected with the two inputs of the comparator, the two inputs of the comparator and the two inputs of the adder are connected in series and are connected in a simplified mode _i N-bit quadrature input y _i Reference value t of N bits _i And the N-bit angle input omega _i ；x _i And shiftedy _i By addition or subtraction by adders or subtractions to obtain intermediate results x _t ，y _i And shifted x _i By addition or subtraction by an adder-subtractor to obtain an intermediate result y _t And 4 outputs are x respectively _t And shifted y _t Value x added or subtracted by an adder-subtractor _o ，y _t And shifted x _t Value y added or subtracted by an adder-subtractor _o ，t _i Self and shifted t _i Value t added or subtracted by an adder-subtractor _o And ω _t And the value ω obtained by addition or subtraction of a known N-bit angle _o Addition and subtraction are controlled by a one-bit control code, which is input by x _i And t _i Determined by the output of the comparator.

Furthermore, the shifter shifts right for a fixed number of bits in each stage, and directly realizes shifting through routing without using a logic device or consuming extra resources.

Furthermore, a pipeline design is adopted between the typical CORDIC single iteration unit and the improved CORDIC double iteration unit, and the running speed of the system is maximized.

A method for realizing a fully-integrated low-cost high-speed high-precision outphasing modulator is based on a CORDIC algorithm, and comprises an input stage amplitude and phase calculation module, an intermediate stage phase angle calculation module and two output stage I and Q calculation modules, and specifically comprises the following steps:

firstly, an input stage amplitude and phase calculation module calculates the amplitude A and the phase angle theta of an input I and Q path signal S (t): converting (I, Q) to quadrant 1 and 4 to become (I ', Q'), and calculating amplitude by CORDIC vector mode

(k is a real coefficient due to pseudo-rotation) and phase angle

Second, the intermediate stage out-of-phase angle calculation module (calculates the two decomposed components S ₁ (t) and S ₂ (t) out-of-phase angle

First, calculating by using a CORDIC bivector mode

(R is the amplitude of the output signal and is a real coefficient), then the initial (I, Q) quadrant is judged, if the initial position is in the 1, 4 quadrants, the output is carried out

If the initial position is in quadrants 2 and 3

Thirdly, the two output stage I and Q calculation modules respectively calculate S ₁ (t) corresponding to I ₁ ，Q ₁ And S ₂ (t) corresponding to I ₂ ，Q ₂ : rotation mode calculation using CORDIC

In order to improve the operation speed, the real coefficients of all the formulas do not participate in actual calculation, and the normalization is uniformly carried out on the subsequent analog circuit part. The invention is characterized in that all operations only use the adder, so the delay of the critical path can be optimized only by optimizing the delay of the adder, and the application requirement of millimeter waves can be met.

Further, the first-step input stage amplitude-phase calculation module calculates the amplitude a and the phase angle θ of the input I and Q path signals S (t), and the specific implementation process is as follows: step 11), for the input I and Q signals, determining the quadrant to which (I, Q) belongs, if the input I and Q signals belong to quadrants 1 and 4, outputting Q =0, I '= I and Q' = Q, and if the input I and Q signals belong to quadrants 2 and 3, outputting Q =1, I '= -I and Q' = -Q, wherein Q is a quadrant flag, and the logical value of the quadrant flag is equal to the sign bit value of I; step 12), inputting I ', Q' and 0 into an arctangent calculation unit (401) as initial x, y and omega respectively, and if y is determined in each iteration _i Is positive, then x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Corresponding to a pseudo-rotation of (I ', Q') around the origin of atan (2) ^-i+1 ) Angle if y _i Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Corresponding to a pseudo-rotation atan (2) of (I ', Q') clockwise about the origin ^-i+1 ) Angle, while omega _i Adding a rotation angle, and taking the anticlockwise direction as positive; after N iterations, final y _N Trending toward 0, x of output _N For pseudo-amplitude values kA, k are real coefficients from the pseudo-rotation, N>K tends to 1.646, omega at 6 _N Is the phase θ; the pseudo rotation refers to the rotation with unequal amplitude after rotating for a certain angle and before rotating.

Further, in the second step, the intermediate stage out-phase angle calculation module (calculates the two decomposed components S) ₁ (t) and S ₂ (t) out-of-phase angle

The concrete implementation process is as follows, step 21), the A of the input is solved

t ₀ = A as initial input, input into the inverse cosine calculation unit, and determine the initial position if t ₀ Is greater than

The initial unit vector is rotated from the x-axis if t ₀ Is less than

The initial unit vector is rotated from the y-axis; step 22), carrying out N-stage CORDIC double iteration unit operation, if x _i <t _i Then 2 operations are performed consecutively, x 1 st time _t ＝x _i -(y _i >>i)，y _t ＝y _i +(x _i >>i) 2 nd time x _i+1 ＝x _t -(y _t >>i)，y _i+1 ＝y _t +(x _t >>i) Equivalent to a pseudo-rotation 2 × atan of the initial unit vector counterclockwise about the origin (2) ^-i+1 ) Angle, if x _i ≥t _i Then 2 operations are performed consecutively, x 1 st time _t ＝x _i +(y _i >>i)，y _t ＝y _i -(x _i >>i) 2 nd time x _i+1 ＝x _t +(y _t >>i)，y _i+1 ＝y _t -(x _t >>i) Equivalent to a pseudo-clockwise rotation of the initial unit vector by 2 × atan (2) around the origin ^-i+1 ) An angle; while t is _i+1 ＝t _i +(t _i >>2)，ω _i Adding the rotation angle, taking the anticlockwise direction as positive, outputting omega after N times of iteration _N Is that

Step 23), reading the quadrant mark q, and outputting if the initial position is in quadrants 1 and 4

If the initial position is in quadrants 2 and 3

Further, the concrete implementation process in the third step is as follows, input

Starting from the initial unit vector on the x-axis, N CORDIC iterations 602 of rotation pattern are performed, the i-th rotation direction being defined by ω of the i-th iteration _i Determine if ω is _i Is positive, then x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Corresponding to a pseudo-rotation atan of the initial unit vector counterclockwise about the origin (2) ^-i+1 ) Angle if

Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Equivalent to the initial unit vector enclosurePseudo-rotation atan clockwise around origin (2) ^-i+1 ) Angle, simultaneously omega _i Plus the rotation angle, counterclockwise is positive. X of final output _N ，y _N Are respectively as

And

is corresponding to _1,2 ,Q _1,2 。

Compared with the prior art, the invention has the remarkable effects that: first, the outphasing modulator designed by the invention is especially suitable for millimeter wave communication systems with large baseband bandwidth, and can significantly improve the power efficiency of the millimeter wave power amplifier. Secondly, because only an adder is used in the CORDIC algorithm, and a multiplier which brings large power consumption, large time delay and large area is not used, the structure of the outphasing modulator is simpler, the processing speed of the outphasing modulator is obviously improved, the throughput of the outphasing modulator can reach the sampling frequency which is more than 1GHz, and the power consumption is reduced; thirdly, because a table look-up mode is not adopted to calculate the nonlinear function, and the calculation process is only 3 steps, the calculation method is simple, and no cache memory is needed, so that the area of the chip is greatly saved, and the area of the invention is the smallest of devices of the same type according to the primary simulation result, so that the production cost is obviously saved; fourthly, due to the universality of the CORDIC algorithm, the scheme of the invention has better universality and portability; fifthly, the precision of the output data is related to the CORDIC series N, and the error of the output data is not more than 2 ^-N+1 Extremely high precision can be realized by increasing N; sixthly, the invention has various using methods, is suitable for various out-phase modulation systems, and can adopt a using method that two out-phase angle outputs of the second stage are directly connected with a phase modulator to generate two paths of frequency modulation signals besides a using method that two I and Q modulators are connected after the third stage outputs to generate two paths of frequency modulation signals, thereby omitting the third stage and the two I and Q modulators; seventh, compared with the traditional analog circuit implementation scheme, the digital scheme is adopted, so that the method is more flexible and has higher operation precision. In out-of-phase modulationIn the design of the circuit, the problem of synchronization between two paths of decomposed signals is particularly important, and the synchronization characteristic of a digital circuit is a great advantage compared with the traditional analog circuit. Second, the dynamic range of digital circuits is larger than that of analog circuits. The dynamic range of digital operation is determined by the word length, while the dynamic range of analog circuits is determined by the supply voltage. As the CMOS process becomes more refined, the power supply voltage continues to decrease, and this advantage becomes more significant.

Drawings

Fig. 1 is a schematic diagram of a typical characteristic curve of a millimeter wave linear power amplifier.

Fig. 2 is a schematic position diagram of the present invention in an out-of-phase power amplification system.

FIG. 3 is a schematic diagram of the modules and their functions according to the present invention.

FIG. 4 is a schematic diagram of the input stage magnitude-phase calculation module of the present invention.

FIG. 5 is a block diagram of the intermediate stage out-phasing angle calculation module of the present invention.

Fig. 6 is a schematic diagram of the structure of the I and Q computing modules of the output stage of the present invention.

Detailed Description

In order to further explain the technical scheme disclosed by the invention, the following detailed description is combined with the attached drawings and specific embodiments. Those skilled in the art will recognize that the present invention is susceptible to variations and modifications without departing from the spirit of the invention, and that such variations and modifications are within the scope of the invention as defined by the appended claims and their equivalents.

Example 1: the fully-integrated low-cost high-speed high-precision outphasing modulator related by the invention is suitable for various electronic devices and equipment, including but not limited to radio frequency transmitters, millimeter wave transmitters, modulators of various communication protocols (millimeter wave wireless communication, 5G wireless communication, orthogonal frequency division multiplexing OFDM, wideband code division multiple access CDMA), digital circuits, partial power consumption products, electronic test equipment and the like. The electronic devices include various integrated circuits, programmable logic devices, circuit boards, optical network circuits or other communication networks, and the power consuming products include mobile communication terminals, smart phones, computers, smart tablets, video cameras, digital cameras, portable memory chips, network cards, wireless network cards, multifunctional peripherals, and the like. In addition, electronic devices include industrial, automated equipment, and the like applications.

To more specifically explain the power amplifier efficiency improvement brought by the technology, fig. 1 shows an output characteristic curve and an efficiency curve of a typical millimeter wave linear power amplifier, and a probability density function curve of a traditional I, Q modulation input signal. In a system adopting a traditional I and Q modulation scheme, because the probability density function of the power of signals after I and Q modulation is shown by a PDF curve in figure 1, in order to ensure that the output signals are not seriously distorted, the dynamic range of the input signals is backed off from a saturation interval, so that the average power of the output is P _AVG Efficiency is the average efficiency PAE _AVG (ii) a In the system adopting the Outphasing technology, because the amplitude of an input signal is constant, the input power of two paths of power amplifiers can be set as the saturated input power, and the output power is the saturated output power P at the moment _SAT Efficiency is maximum efficiency PAE _SAT . As can be readily seen in fig. 1, a system employing Outphasing techniques, whether output power or efficiency, is superior to a system employing a conventional I, Q modulation scheme.

FIG. 2 shows an outphasing power amplification system to which the present invention is applied, in which the present invention decomposes high speed (Gbps) baseband I, Q digital signals S (t) into two constant amplitude signals S ₁ (t) and S ₂ And (t), the subsequent IQ modulation module up-converts the signals to millimeter wave frequency to generate two paths of millimeter wave signals with the same amplitude, and the two paths of millimeter wave signals are amplified by two high-efficiency linear power amplifiers and then synthesized and transmitted. The technical difficulty lies in the design of an outphasing signal modulator with ultrahigh speed (Gbps) and high precision, and particularly, referring to FIG. 3, the fully integrated outphasing modulator with low cost, high speed and high precision comprises an input stage amplitude and phase calculation module 301, a middle stage phase-difference angle calculation module 302 and two output stages I and

Q calculation modules

303 and 304 on the basis of a CORDIC algorithm, wherein the input stage amplitude and phase calculation module comprises an I input end, a Q input end, a quadrant judgment unit and an arc tangent calculation unit 401; the intermediate stage out-phasing angle calculationThe module comprises an initial position judging unit, an inverse cosine calculating unit 501 and a phase calculating unit; the output stage I and Q calculation module is divided into two paths with the same structure, and each path comprises a sine calculation unit 601, a cosine calculation unit 601, an I output end and a Q output end. The scheme uses a CORDIC algorithm as a design guiding idea, realizes operation only through an adder and does not use a multiplier. The shifter shifts right in each stage by a fixed bit number, directly realizes shifting through wiring, and does not use a logic device.

The input stage amplitude and phase calculation module comprises I and Q input ends, a quadrant judgment unit and an arc tangent calculation unit. The arctangent computing unit is a CORDIC algorithm circuit working in a vector mode and is formed by cascading N stages of typical CORDIC single iteration units. Where N is related to the required output data accuracy.

Wherein, the two output stage I and Q computing modules comprise two sine and cosine computing units with the same structure and I _1,2 、Q _1,2 And (4) an output end. Each path of sine and cosine computing unit is a CORDIC algorithm circuit working in a rotating mode. The CORDIC processing unit working in the rotating mode is formed by cascading N stages of typical CORDIC single iteration units. Where N is related to the required accuracy of the output data.

The typical CORDIC

single iteration unit

402, 602 includes 3 inputs and 3 outputs, 3 adders and 2 shifters, where the 3 inputs are N-bit inphase input x, N-bit orthogonal input y, and N-bit angle input ω, the 3 outputs are values obtained by adding or subtracting shifted x and y by the adders, values obtained by adding or subtracting shifted y and x by the adders, and values obtained by adding or subtracting ω and a known N-bit angle, the addition or subtraction is controlled by a one-bit control code, and the control code is determined by the input; the improved CORDIC double-deckThe generation unit 502 is formed by two CORDIC single iteration units in a cascaded and simplified manner, and comprises 4 inputs and 4 outputs, 1 comparator, 1 adder, 5 adders and 5 shifters, wherein the 4 inputs are respectively an N-bit in-phase input x, an N-bit quadrature input y, an N-bit reference value t and an N-bit angle input omega. The shifted x and y are added or subtracted by an adder-subtractor to obtain an intermediate result x _t The shifted y and x are added or subtracted by an adder-subtractor to obtain an intermediate result y _t The 4 outputs are respectively the values of shifted x and y added or subtracted by an adder-subtractor, and the shifted y _t And x _t A value obtained by addition or subtraction by an adder-subtractor, a value obtained by addition or subtraction of shifted t and t themselves by an adder-subtractor, and ω _t And the addition or subtraction of the known N-bit angle is controlled by a one-bit control code, which is determined by the size of the inputs x and t. The shifter shifts the fixed bit number to the right in each stage, directly realizes the shift through routing, does not use a logic device, and does not consume extra resources. A pipeline design is adopted between the typical CORDIC single iteration unit and the improved CORDIC double iteration unit, and the running speed of the system is maximized; in the design, the inverse code can be used for replacing the complement code to carry out operation, and the processing speed of the circuit is improved under the condition of sacrificing the precision.

Example 2: referring to fig. 2, a fully integrated low-cost, high-speed, high-precision outphasing modulator is shown. FIG. 2 shows an outphasing power amplifying system suitable for the present invention, in which the present invention decomposes high-speed (Gbps) baseband I and Q digital signals S (t) into two constant amplitude signals S ₁ (t) and S ₂ And (t), the subsequent IQ modulation module up-converts the signals to millimeter wave frequency to generate two paths of millimeter wave signals with the same amplitude, and the two paths of millimeter wave signals are amplified by two high-efficiency linear power amplifiers and then synthesized and transmitted.

Fig. 3 shows the internal structure of the present invention. The CORDIC algorithm is taken as a basis, the CORDIC algorithm comprises an input stage amplitude and phase calculation module 301, an intermediate stage out-phase angle calculation module 302 and two output stage I and Q calculation modules 303 and 304, and the CORDIC algorithm is divided into three steps in terms of algorithm: in the first step, an input stage amplitude and phase calculation module (301) calculates I, and,Amplitude a and phase angle θ of Q-path signal S (t): converting (I, Q) to quadrant 1 and 4 to become (I ', Q'), and calculating amplitude by CORDIC vector mode

(k is a real coefficient due to pseudo rotation) and phase angle

Secondly, the intermediate-stage out-of-phase angle calculation module (302) calculates the two decomposed components S ₁ (t) and S ₂ (t) out-of-phase angle

First using CORDIC bivector mode calculation

If the initial position is in quadrants 2 and 3

Thirdly, the two paths of output stage I and Q computing modules (303 and 304) respectively compute S ₁ (t) corresponding to I ₁ ，Q ₁ And S ₂ (t) corresponding to I ₂ ，Q ₂ : rotation mode calculation using CORDIC

The input stage amplitude and phase calculation module structure 301 of the present invention is shown in FIG. 4, and the structure is actuallyThe existing function is divided into the following 2 steps: in the first step, for the input I and Q signals, it is determined that the quadrant (I, Q) belongs to, if the quadrant belongs to quadrants 1 and 4, Q =0, I '= I and Q' = Q are output, and if the quadrant belongs to quadrants 2 and 3, Q =1, I '= -I and Q' = -Q are output, where Q is a quadrant flag whose logical value is equal to the sign bit value of I. Secondly, inputting I ', Q' and 0 as initial x, y and omega into an arctangent calculation unit (401) respectively, and inputting each stage of single iteration unit C _i Is shown as 402, with each iteration, if y _i Is positive, then x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Corresponding to pseudo-rotation of atan (2) counterclockwise around the origin (I ', Q') ^-i+1 ) Angle if y _i Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Corresponding to a pseudo-rotation atan (2) of (I ', Q') clockwise about the origin ^-i+1 ) And (4) an angle. Simultaneously omega _i Plus the rotation angle, is positive counterclockwise. After N iterations, final y _N Trending toward 0, x of output _N For pseudo-amplitude values kA (k being the real coefficient from the pseudo-rotation, N)>K tends to 1.646) at 6 hours, ω _N Is the phase theta. The pseudo rotation refers to the rotation with different amplitude after rotating a certain angle and before rotating.

The structure of the mid-stage out-phasing angle calculation module 302 of the present invention is shown in fig. 5. The function realized by the structure is divided into the following 3 steps: first, for input A, find

t ₀ = A as initial input, input to the inverse cosine calculation unit (501), and determine the initial position if t ₀ Is greater than

The initial unit vector starts to rotate from the x-axis if t ₀ Is less than

Then the initial unit vectorStarting rotation from the y-axis; secondly, N stages of CORDIC double iteration unit operation are carried out, and each stage of double iteration unit DC _i The circuit structure of (2) is shown in FIG. 5, if x _i <t _i Then 2 operations are performed consecutively, x 1 st time _t ＝x _i -(y _i >>i)，y _t ＝y _i +(x _i >>i) 2 nd time x _i+1 ＝x _t -(y _t >>i)，y _i+1 ＝y _t +(x _t >>i) Equivalent to a pseudo-rotation 2 × atan of the initial unit vector counterclockwise about the origin (2) ^-i+1 ) Angle, if x _i ≥t _i Then 2 operations are performed consecutively, 1 st x _t ＝x _i +(y _i >>i)，y _t ＝y _i -(x _i >>i) 2 nd time x _i+1 ＝x _t +(y _t >>i)，y _i+1 ＝y _t -(x _t >>i) Equivalent to a pseudo-clockwise rotation of the initial unit vector by 2 × atan (2) around the origin ^-i+1 ) And (4) an angle. While t is _i+1 ＝t _i +(t _i >>2)，ω _i Adding the rotation angle, taking the anticlockwise direction as positive, outputting omega after N iterations _N Is that

Thirdly, reading the quadrant mark q, and outputting if the initial position is in quadrants 1 and 4

If the initial position is in quadrants 2 and 3

The structure of the output stage I,

Q calculation modules

303, 304 of the present invention is shown in fig. 6. The module realizes the following functions: input device

Starting from an initial unit vector on an x axis, N times of CORDIC iterations of rotation patterns are carried out, and the rotation direction of the ith time is determined by omega of the ith iteration _i Determine if ω is _i Is positiveThen x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Equivalent to a pseudo-rotation of the initial unit vector around the origin, atan (2) ^-i+1 ) Angle if

Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Equivalent to a pseudo-rotation atan of the initial unit vector clockwise around the origin (2) ^-i+1 ) Angle, while omega _i Plus the rotation angle, counterclockwise is positive. X of final output _N ，y _N Are respectively as

And

is corresponding to I _1,2 ,Q _1,2 。

It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and all equivalent substitutions or substitutions made on the above-mentioned technical solutions belong to the scope of the present invention.

Claims

1. A full-integrated low-cost high-speed high-precision outphasing modulator is characterized in that: the high-speed high-precision outphasing modulator comprises an input stage amplitude and phase calculation module (301), an intermediate stage phase difference angle calculation module (302) and two output stage I and Q calculation modules (303 and 304), wherein the intermediate stage phase difference angle calculation module (302) is arranged between the input stage amplitude and phase calculation module (301) and the two output stage I and Q calculation modules (303 and 304), the input stage amplitude and phase calculation module (301) comprises an I input end, a Q input end, a quadrant judgment unit and an arc tangent calculation unit (401), the arc tangent calculation unit is a CORDIC algorithm circuit working under a vector mode and is formed by cascading N stages of typical CORDIC single iteration units (402); the intermediate-stage out-phase angle calculation module (302) comprises an initial position judgment unit and an inverse cosine meterA calculation unit (501) and a phase calculation unit; the anticosine calculation unit is an improved CORDIC algorithm circuit working in a vector mode and is formed by cascading N stages of improved CORDIC double-iteration units (502), and the two output stage I and Q calculation modules (303 and 304) comprise two sine and cosine calculation units (601) and I calculation units (304) which have the same structure _1,2 、Q _1,2 And at the output end, each path of sine and cosine computing unit is a CORDIC algorithm circuit working in a rotation mode, and the CORDIC algorithm circuit working in the rotation mode is formed by cascading N stages of typical CORDIC single iteration units (602), wherein N is related to the precision of required output data.

2. A fully integrated low-cost high-speed high-accuracy outphasing modulator according to claim 1, characterized in that: the typical CORDIC single iteration unit (402, 602) comprises 3 inputs and 3 outputs, 3 adders and 2 shifters, wherein the 3 inputs are respectively N-bit in-phase inputs x _i N-bit quadrature input y _i And N-bit angle input omega _i And 3 outputs are each x _i And shifted y _i Value x added or subtracted by an adder-subtractor _o ，y _i And shifted x _i Value y added or subtracted by an adder-subtractor _o And ω _i And the value ω obtained by addition or subtraction of a known N-bit angle _o The addition and subtraction are controlled by a one-bit control code, and the control code is determined by input; the improved CORDIC double-iteration unit (502) is formed by cascading and simplifying two CORDIC single-iteration units and comprises 4 inputs and 4 outputs, 1 comparator, 1 summator, 5 adders and 5 shifters, wherein the 4 inputs are respectively N-bit in-phase inputs x _i N-bit quadrature input y _i Reference value t of N bits _i And N-bit angle input omega _i ；x _i And shifted y _i By addition or subtraction by an adder-subtractor to obtain an intermediate result x _t ，y _i And shifted x _i By addition or subtraction by an adder-subtractor to obtain an intermediate result y _t And 4 outputs are x respectively _t And shifted y _t Value x added or subtracted by an adder-subtractor _o ，y _t And shifted x _t Value y added or subtracted by an adder-subtractor _o ，t _i Self and shifted t _i Value t added or subtracted by an adder-subtractor _o And ω _t And the value ω obtained by addition or subtraction of a known N-bit angle _o Addition and subtraction are controlled by a one-bit control code, which is input by x _i And t _i Determined by the output of the comparator.

3. A modulation method applied to a fully integrated low-cost high-speed high-precision outphasing modulator according to any of claims 1-2,

in the first step, an input stage amplitude and phase calculation module (301) calculates the amplitude A and the phase angle theta of an input I and Q path signal S (t): converting (I, Q) into (I ', Q') in quadrants 1 and 4, and calculating amplitude by using CORDIC vector mode

k is the real coefficient and phase angle θ = arctan (Q '/I') from the pseudo rotation;

First using CORDIC bivector mode calculation

R is the amplitude of the output signal and is a real coefficient, then the quadrant of initial (I, Q) is judged, if the initial position is in the quadrants 1 and 4, the output is carried out

If the initial position is in quadrants 2 and 3

In the third step, the first step is to use,two output stage I and Q calculation modules (303 and 304) respectively calculate S ₁ (t) corresponding to I ₁ ，Q ₁ And S ₂ (t) corresponding to I ₂ ，Q ₂ : rotation mode calculation using CORDIC

The first-step input stage amplitude-phase calculation module (301) calculates the amplitude A and the phase angle theta of the input I and Q path signals S (t), and the specific implementation process is as follows: step 11), for the input I and Q signals, judging the quadrant to which (I, Q) belongs, if the (I, Q) signals belong to quadrants 1 and 4, outputting Q =0, I '= I and Q' = Q, and if the (I, Q) signals belong to quadrants 2 and 3, outputting Q =1, I '= -I and Q' = -Q, wherein Q is a quadrant flag, and the logical value of the quadrant flag is equal to the sign bit value of I; step 12), inputting I ', Q' and 0 into an arctangent calculation unit (401) as initial x, y and omega respectively, and if y is determined in each iteration _i Is positive, then x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Corresponding to a pseudo-rotation of (I ', Q') around the origin of atan (2) ^-i+1 ) Angle if y _i Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Corresponding to a pseudo-rotation atan (2) of (I ', Q') clockwise about the origin ^-i+1 ) Angle, simultaneously omega _i Adding a rotation angle, and taking the anticlockwise direction as positive; after N iterations, final y _N Trending toward 0, x of output _N For pseudo-amplitude values kA, k are real coefficients from the pseudo-rotation, N>K tends to 1.646, omega at 6 hours _N Is the phase θ;

in the second step, the intermediate-stage out-phase angle calculation module (302) calculates the two decomposed components S ₁ (t) and S ₂ (t) out-of-phase angle

The initial unit vector is rotated from the x-axis if t ₀ Is less than

The initial unit vector starts to rotate from the y-axis; step 22), carrying out N-stage CORDIC double iteration unit operation, if x _i <t _i Then 2 operations are performed consecutively, x 1 st time _t ＝x _i -(y _i >>i)，y _t ＝y _i +(x _i >>i) 2 nd time x _i+1 ＝x _t -(y _t >>i)，y _i+1 ＝y _t +(x _t >>i) Equivalent to a pseudo-rotation 2 × atan of the initial unit vector counterclockwise about the origin (2) ^-i+1 ) Angle, if x _i ≥t _i Then 2 operations are performed consecutively, x 1 st time _t ＝x _i +(y _i >>i)，y _t ＝y _i -(x _i >>i) 2 nd time x _i+1 ＝x _t +(y _t >>i)，y _i+1 ＝y _t -(x _t >>i) Equivalent to a pseudo-clockwise rotation of the initial unit vector by 2 × atan (2) around the origin ^-i+1 ) An angle; at the same time t _i+1 ＝t _i +(t _i >>2)，ω _i Adding the rotation angle, taking the anticlockwise direction as positive, outputting omega after N times of iteration _N Is that

If the initial position is in quadrants 2 and 3

The third step is realized by inputting

Starting from the initial unit vector on the x-axis, N CORDIC iterations of the rotation pattern are performed, and the i-th rotation direction is defined by ω of the i-th iteration _i Determine if ω is _i Is positive, then x _i+1 ＝x _i -(y _i >>i)，y _i+1 ＝y _i +(x _i >>i) Corresponding to a pseudo-rotation atan of the initial unit vector counterclockwise about the origin (2) ^-i+1 ) Angle if

Is negative, then x _i+1 ＝x _i +(y _i >>i)，y _i+1 ＝y _i -(x _i >>i) Equivalent to a pseudo-rotation atan of the initial unit vector clockwise around the origin (2) ^-i+1 ) Angle, while omega _i Plus the rotation angle, taking the anticlockwise as positive, the x is finally output _N ，y _N Are respectively as

And

is corresponding to I _1,2 ,Q _1,2 。