WO2018176190A1

WO2018176190A1 - Digital power amplifier

Info

Publication number: WO2018176190A1
Application number: PCT/CN2017/078267
Authority: WO
Inventors: 黄伟; 孙益军
Original assignee: 华为技术有限公司
Priority date: 2017-03-27
Filing date: 2017-03-27
Publication date: 2018-10-04
Also published as: CN110463034A; CN110463034B

Abstract

The present application relates to the field of power amplifiers. Disclosed is a digital power amplifier. The digital power amplifier comprises a first DSM, a second DSM, a first PWM, a second PWM, a low-pass filter, a digital up-converter, a comb filter, and a power amplifier. The first PWM is coupled to the first DSM, and is used for modulating a first DSM signal inputted by the first DSM and outputting a first PWM signal. The second PWM is coupled to the second DSM, and is used for modulating a second DSM signal inputted by the second DSM and outputting a second PWM signal. The low-pass filter is separately coupled to the first PWM and the second PWM. The digital up-converter is coupled to the low-pass filter, and is used for modulating the first PWM signal on which low-pass filtering has been performed and the second PWM signal on which low-pass filtering has been performed, and outputting a third PWM signal of a preset radio frequency. The comb filter is coupled to the digital up-converter, and is used for suppressing a PWM harmonic wave of a third PWM signal. The power amplifier is coupled to the comb filter, and is used for performing power amplification processing on the third PWM signal on which harmonic suppression has been performed.

Description

Digital power amplifier

Technical field

The present application relates to the field of power amplifiers, and in particular to a digital power amplifier (English: Digital Power Amplifier, DPA for short).

Background technique

With the continuous development of communication systems, miniaturized communication systems such as base stations and mobile phones are increasingly demanding power consumption requirements, cost requirements, and integration requirements of transmitters. All digital transmitters (English: All Digital Transmitter, ADT) equipped with digital power amplifiers are widely used in miniaturized communication systems due to their low power consumption, low cost and high integration.

In the related art, DPA adopts a architecture of differential cumulative modulation (English: Delta-Sigma Modulation, DSM) + Pulse Wide Modulation (English: Pulse Width Modulation, referred to as PWM). In the working state, after receiving the baseband digital signal, the DPA sequentially performs DSM modulation, PWM modulation, digital up-conversion and power amplification processing on the baseband digital signal, outputs a radio frequency high-power signal, and finally performs the radio frequency high-power signal through the antenna. emission.

However, in the process of DPA processing the baseband digital signal, due to the periodicity of the PWM, under the influence of the PWM harmonics, the signal quality of the RF high-power signal finally output by the DPA is poor; and, in the process of digital up-conversion processing, the mixing The noise entering the band is high, resulting in a low in-band signal-to-noise ratio of the output RF high-power signal.

Summary of the invention

In order to solve the problem that the signal quality of the radio frequency high-power signal of the DPA output in the related art is poor, and the in-band signal-to-noise ratio of the radio frequency high-power signal is relatively low, the embodiment of the present application provides a digital power amplifier.

In a first aspect, the present application provides a digital power amplifier including:

a first DSM, a second DSM, a first PWM, a second PWM, a low pass filter, a digital upconverter, a comb filter, and a power amplifier;

The first PWM is coupled to the first DSM for modulating the first DSM signal of the first DSM input and outputting the first PWM signal to the low pass filter;

The second PWM is coupled to the second DSM, for modulating the second DSM signal of the second DSM input, and outputting the second PWM signal to the low pass filter, the phase difference between the first DSM signal and the second DSM signal is 90°;

The low pass filter is coupled to the first PWM and the second PWM, respectively, for performing low pass filtering on the first PWM signal and the second PWM signal, and outputting the low pass filtered first PWM signal to the digital up converter and Low pass filtered second PWM signal;

The digital up-converter is coupled to the low-pass filter for modulating the low-pass filtered first PWM signal and the low-pass filtered second PWM signal, and outputting a third PWM signal of a predetermined RF frequency to the comb filter;

The comb filter is coupled to the digital upconverter for suppressing the PWM harmonic of the third PWM signal, and outputting the third PWM signal after the harmonic suppression to the power amplifier;

The power amplifier is coupled to the comb filter for power amplification of the third PWM signal after harmonic suppression Reason.

By adding a low-pass filter before the digital up-converter, the low-pass filter is used to low-pass filter the first PWM signal and the second PWM signal to reduce the far-end noise of the first PWM signal and the second PWM signal. In turn, the aliasing of the aliasing into the band during digital up-conversion is reduced, and the in-band signal-to-noise ratio of the output signal is ultimately improved.

In addition, by adding a comb filter after the digital up-converter, the comb filter is used to suppress the PWM harmonic generated during the modulation process, thereby reducing the influence of the PWM harmonic on the output signal, thereby reducing the output. The spurs in the signal improve the signal quality of the output signal.

In a possible design, the low pass filter includes a first low pass filtering unit and a second low pass filtering unit, and the first low pass filtering unit and the second low pass filtering unit are first order low pass filtering units;

The first low pass filtering unit is coupled to the first PWM, and is configured to add a first PWM signal of the current sampling point and a first PWM signal delayed by one sampling point, and output a low pass filtered first PWM signal;

The second low pass filtering unit is coupled to the second PWM, and is configured to add the second PWM signal of the current sampling point and the second PWM signal delayed by one sampling point, and output the low-pass filtered second PWM signal.

In a possible design, the first PWM signal and the second PWM signal are all three-state signals, and the three-state signal includes three states of -1, 0, and 1;

The low-pass filtered first PWM signal and the low-pass filtered second PWM signal are all five-state signals, and the five-state signal includes five states of -2, -1, 0, 1, and 2.

When the PWM signal is filtered by a simple first-order low-pass filter unit, only simple delay and addition of the PWM signal are required, and the complexity of the filtering process is low, thereby reducing the manufacturing cost and overall power consumption of the DPA. At the same time, due to the low state (amplitude) of the PWM signal output after the low-pass filtering process, the complexity of subsequent signal processing is reduced, and the overall power consumption of the DPA is further reduced while ensuring DPA performance.

In a possible design, the digital up converter includes a digital local oscillator, a first multiplier, a second multiplier, and an adder;

The frequency of the digital local oscillator is fs/4, and the digital local oscillator is used to output the in-phase local oscillator signal and the quadrature local oscillator signal. The in-phase local oscillator signal and the quadrature local oscillator signal are all three-state signals, and the in-phase local oscillator signal and The phase difference of the orthogonal local oscillator signal is 90°, fs is the sampling frequency, and the three-state signal includes three states of -1, 0, and 1;

The first multiplier is coupled to the low pass filter and the digital local oscillator, respectively, for modulating the low pass filtered first PWM signal to a predetermined radio frequency according to the in-phase local oscillator signal;

The second multiplier is coupled to the low pass filter and the digital local oscillator, respectively, for modulating the low pass filtered second PWM signal to a predetermined radio frequency according to the orthogonal local oscillator signal;

The adder is coupled to the first multiplier and the second multiplier, respectively, for adding the signals output by the first multiplier and the second multiplier, and outputting the third PWM signal.

In a possible design, the low-pass filtered first PWM signal and the low-pass filtered second PWM signal are all five-state signals, and the third PWM signal output by the digital up-converter is a five-state signal, five states. The signal includes five states of -2, -1, 0, 1, and 2.

By setting the frequency of the digital local oscillator in the digital up-converter to fs/4, it is ensured that the in-phase local oscillator signal and the quadrature local oscillator signal of the digital local oscillator output are three-state signals, and then the in-phase local oscillator signal is utilized. When the quadrature local oscillator signal modulates the PWM signal, the number of states of the modulated PWM signal is small, which is advantageous for subsequent signal processing.

In one possible design, the impulse response function of the comb filter satisfies:

Where N is the output bit width of the first DSM and the second DSM, M is the modulation period of the first PWM and the second PWM, and floor(M/4) is the rounding down of M/4, M=2 ^{(N -1)} .

In a possible design, the comb filter includes one cascaded delay unit and one adder, and each delay unit is configured to output a third PWM signal delayed by four sampling points;

The first adder is configured to add the third PWM signal of the current sampling point to the third PWM signal output by the first delay unit;

The i-th adder is configured to add the signal output by the i-1th adder to the third PWM signal output by the i-th delay unit, 2≤i≤l.

In a possible design, the third PWM signal output by the digital up-converter is a five-state signal, and the third PWM signal after harmonic suppression is an M+1 state signal.

When the comb filter is used to comb filter the third PWM signal, the comb filter can suppress the PWM harmonics and reduce the DPA because the suppression of the comb filter is aligned with the PWM harmonic position. The spurs in the output signal; at the same time, the comb filter performs only simple delay and addition operations, achieving low complexity and power consumption; and the amplitude of the output signal after comb filtering is limited, which is beneficial to subsequent signal processing. .

In a possible design, the power amplifier includes a power mapping unit, L power output units, and a combiner, L=M/2;

The power mapping unit is coupled to the comb filter for splitting the third PWM signal after the harmonic suppression into an L-channel three-state signal;

The power mapping unit is respectively coupled to the L power output units for mapping the L-way three-state signal to the L power output units, and each of the power output units is configured to perform power amplification processing on the three-state signal input by the power mapping unit;

The combiner is coupled to the L power output units for combining signals output by the L power output units.

In a possible design, each power output unit is a switched capacitor power amplifier (English: Switched Capacitor Power Amplifier, SCPA for short), and each SCPA is used to output a three-state signal;

When the third PWM signal after the harmonic suppression is +n, the n power output units of the L power output units are used to output the signal of the +1 state, and the L-n power output units are used for outputting the signal of the 0 state;

When the third PWM signal after the harmonic suppression is -n, the n power output units of the L power output units are used to output the signal of the -1 state, and the L-n power output units are used to output the signal of the 0 state.

Multi-value (L+1 amplitude) signals are split into multiple three-state signals by a power mapping unit in the power amplifier, and are mapped to a plurality of power output units, respectively, which are respectively received by respective power output units. The signal is amplified by power, and finally the RF high-power signal output is realized; since each power amplifying unit operates in a switching state, the power amplifier is simple in implementation and high in efficiency.

In a second aspect, the present application provides a chip system for implementing the digital power amplifier of the first aspect or any of the possible designs of the first aspect. The chip system can be composed of chips, and can also include chips and other discrete devices. The chip may be an Application-Specific Integrated Circuit (ASIC) or other form of chip. Optionally, the chip system may further include a processor for supporting the digital power amplifier to implement the functions involved in the foregoing aspects, for example, obtaining signals and/or parameters involved in the foregoing aspects, and performing the numbers in the foregoing aspects. Power amplification process. In a possible design, the chip system further includes storage The memory is used to store necessary program instructions and data for the digital power amplifier.

DRAWINGS

1 is an architectural diagram of a DPA provided by the related art;

2 is a simulation performance diagram of the DPA shown in FIG. 1 in an operating state;

FIG. 3 is a structural diagram of a DPA provided by an embodiment of the present application;

4 is a schematic structural view of a low pass filter in the DPA shown in FIG. 3;

Figure 5 is a schematic diagram of the digital upconverter, the in-phase local oscillator signal, and the quadrature local oscillator signal in the DPA shown in Figure 3;

6 is a schematic structural view of a comb filter in the DPA shown in FIG. 3;

7 is a schematic structural view of a power amplifier in the DPA shown in FIG. 3;

FIG. 8 is a structural diagram of a DPA provided by another embodiment of the present application;

9 and 10 are simulation performance diagrams of DPA provided by an embodiment of the present application.

detailed description

The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Please refer to FIG. 1 , which shows an architectural diagram of a DPA provided by the related art. The DPA employs a "DSM+PWM" architecture including a first DSM 111, a second DSM 112, a first PWM 121, a second PWM 122, a digital upconverter 130, and a power amplifier 140.

In the working state, the first DSM 111 is configured to receive the in-phase (Inphase: I) signal obtained by upsampling, and the second DSM 112 is configured to receive the orthogonal (English: Quadrature, Q:) signal obtained by upsampling. Wherein the phase difference between the I signal and the Q signal is 90°.

After the first DSM 111 modulates the I signal, the first DSM signal is input to the coupled first PWM 121; after the second DSM 112 modulates the Q signal, the second DSM signal is input to the coupled second PWM 122.

The first PWM 121 and the second PWM 122 respectively modulate the received first DSM signal and the second DSM signal to obtain a first PWM signal and a second PWM signal, and input the first PWM signal and the second PWM signal into the digital Upconverter 130.

After receiving the first PWM signal and the second PWM signal, the digital up-converter 130 respectively modulates the first PWM signal and the second PWM signal to a predetermined RF frequency and passes through an internal multiplexer (English: Multiplexer, referred to as: MUX) multiplexes the modulated first PWM signal and the second PWM signal to obtain a PWM signal of a predetermined RF frequency, and performs power amplification by the coupled power amplifier 140.

In the operating state of the DPA shown in Figure 1, due to the periodicity of the first PWM 121 and the second PWM 122 modulation, the final output signal of the DPA will be affected by the PWM harmonics, resulting in higher spurs in the spectrum. As shown in Fig. 2, in the DPA output signal, the spur closest to the main signal (located at 2 × 10 ⁹ Hz) (at 2.5 × 10 ⁹ Hz) has a small difference (about 3 dB) from the amplitude of the main signal. In order to improve the quality of the output signal, the output of the DPA needs to be set with a filter with strong suppression capability to filter the spurs. However, adding a filter with stronger suppression capability will not only increase the overall manufacturing cost of DPA, reduce the integration of DPA, but also increase the overall power consumption of DPA.

At the same time, in the process of processing the first PWM signal and the second PWM signal by the digital up-converter 130, the signal frequency shifting and the real part processing are performed, and when the real part processing is performed, the positive and negative half frequency signals will be aliased. And negative half-frequency noise Far greater than the positive half frequency, resulting in higher aliasing into the band, resulting in lower in-band signal-to-noise of the output signal.

In order to solve the above problem, in the DPA shown in the embodiment of the present application, the low-pass filter is applied to the first PWM signal and the second PWM signal by using the low-pass filter by adding a low-pass filter before the digital up-converter. Decreasing the far-end noise of the first PWM signal and the second PWM signal, thereby reducing aliasing into the band during digital up-conversion, and ultimately improving the in-band signal-to-noise ratio of the output signal; adding a comb after the digital upconverter The filter is used to suppress the PWM harmonic generated during the modulation process, thereby reducing the influence of the PWM harmonic on the output signal, thereby reducing the spurs in the output signal and improving the output signal. Signal quality. The following description is made using the illustrative embodiments.

Please refer to FIG. 3, which shows an architectural diagram of a DPA provided by an embodiment of the present application. The DPA includes a first DSM 311, a second DSM 312, a first PWM 321, a second PWM 322, a low pass filter 330, a digital upconverter 340, a comb filter 350, and a power amplifier 360.

In a possible implementation, when the DPA shown in FIG. 3 is used in a multi-stage cascade architecture, and the first DSM 311 and the second DSM 312 are the first-stage DSM, the first DSM 311 and the second DSM. The input of 312 is the upsampled I signal and the Q signal (the phase difference between the I signal and the Q signal is 90°). Correspondingly, the first DSM 311 modulates the upsampled I signal and outputs the first DSM signal. The second DSM 312 modulates the upsampled Q signal and outputs a second DSM signal; when the DPA shown in FIG. 3 is used in the multi-stage cascade architecture, and the first DSM 311 and the second DSM 312 are the i-th level At the time of DSM (i ≥ 2), the inputs of the first DSM 311 and the second DSM 312 are the error signals output by the i-1th stage DSM. For the convenience of description, the first DSM 311 and the second DSM 312 are used as the first-stage DSM as an example for illustration, and the present application is not limited thereto.

Optionally, in the process of modulating the I and Q signals, the first DSM 311 and the second DSM 312 perform oversampling, noise shaping, and decimation filtering on the I and Q signals.

After the first DSM 311 and the second DSM 312 complete signal modulation, the first DSM signal and the second DSM signal are input to the coupled first PWM 321 and second PWM 322, respectively.

Since the DSM signals output by the first DSM 311 and the second DSM 312 are both high bit low sampling rate signals, which is disadvantageous for subsequent signal processing, the first PWM 321 receives a high bit low sampling rate in order to improve the efficiency of subsequent signal processing. After the first DSM signal, the first DSM signal is modulated to output a first PWM signal having a low bit high sampling rate. Similarly, the second PWM 322 modulates the second DSM signal of the high bit low sampling rate and outputs the second PWM signal of the low bit high sampling rate.

In a possible implementation manner, when the output bit widths of the first DSM 311 and the second DSM 312 are both N (including the sign bit), the modulation period of the first PWM 321 and the second PWM 322 is M=2 ^{( N-1)} , that is, the first PWM 321 modulates the first DSM signal of the N bit, and outputs a signal with a modulation period of 2 ^(N-1) , wherein the three-state signal includes three states of -1, 0, and 1. That is, the first PWM signal output by the first PWM 321 includes only three amplitudes.

In order to reduce the noise that is aliased into the band during the digital up-conversion process, the DPA is further passed through the low-pass filter 330 for the first PWM signal for the high-sampling rate three-state signal output by the first PWM 321 and the second PWM 322, respectively. Performing low-pass filtering processing with the second PWM signal.

Schematically, the structure of the low pass filter 330 is as shown in FIG. The low pass filter 330 includes a first low pass filtering unit 331 and a second low pass filtering unit 332, and the first low pass filtering unit 331 is coupled to the first PWM 321 , and the second low pass filtering unit 332 and the second PWM 322 coupled. Correspondingly, the first low pass filtering unit 331 is configured to use the first PWM The signal is low pass filtered, and the second low pass filtering unit 332 is configured to low pass filter the second PWM signal.

In a possible implementation manner, the first low pass filtering unit 331 and the second low pass filtering unit 332 are both first order low pass filtering units, and each includes a delay unit and an adder. As shown in FIG. 4, taking the first low-pass filtering unit 331 as an example, the first low-pass filtering unit 331 includes a delay unit 331a for outputting a signal delayed by one sampling point, and an adder 331b. The adder 331b is used to add two signals.

The first low pass filtering unit 331 shown in FIG. 4 performs low pass filtering on the first PWM signal, that is, adds the first PWM signal of the current sampling point and the first PWM signal delayed by one sampling point. The structure of the second low pass filtering unit 332 is similar to that of the first low pass filtering unit 331 for adding the second PWM signal of the current sampling point to the second PWM signal delayed by one sampling point.

Since the low pass filter 330 adds the PWM signal of the current sampling point to the PWM signal delayed by one sampling point, when the first PWM signal and the second PWM signal are both three-state signals, the low pass is passed. The filtered first PWM signal and the second PWM signal are five-state signals, and the five-state signal includes five states of -2, -1, 0, 1, and 2.

To modulate the signal to a predetermined RF frequency, the low pass filtered PWM signal is further input to a digital upconverter 340 which is modulated by a digital upconverter 340 onto a carrier of a predetermined RF frequency.

In a possible implementation, as shown in FIG. 5, the digital up-converter 340 includes a digital local oscillator 341, a first multiplier 342, a second multiplier 343, and an adder 344.

The digital local oscillator 341 is used to output the in-phase local oscillator signal (LO_I) and the quadrature local oscillator signal (LO_Q), wherein the phase difference between the in-phase local oscillator signal and the quadrature local oscillator signal is 90°. In order to make the DPA work as much as possible in the switching state, the frequency of the digital local oscillator 341 is set to fs/4, at which the frequency of the in-phase local oscillator signal and the quadrature local oscillator signal output by the digital local oscillator 341 are both Fs/4 (same as the predetermined RF frequency), and the in-phase local oscillator signal and the quadrature local oscillator signal are all three-state signals.

Illustratively, as shown in FIG. 5, the amplitude of the in-phase local oscillator signal output by the digital local oscillator 341 is 0→1→0→-1→0 cycles, and the amplitude of the output quadrature local oscillator signal is 1→0. →-1→0→1 cycle.

The first multiplier 342 is coupled to the low pass filter and the digital local oscillator 341, respectively. When receiving the low-pass filtered first PWM signal and the in-phase local oscillator signal, the first multiplier 342 multiplies the two signals, thereby modulating the low-pass filtered first PWM signal to a predetermined condition by using the in-phase local oscillator signal RF frequency (ie fs/4).

Similar to the first multiplier 342, the second multiplier 343 is coupled to the low pass filter and the digital local oscillator 341, respectively. When receiving the low-pass filtered second PWM signal and the quadrature local oscillator signal, the second multiplier 343 multiplies the two signals to modulate the low-pass filtered second PWM signal by using the orthogonal local oscillator signal To the predetermined RF frequency.

Since the output in-phase local oscillator signal and the quadrature local oscillator signal are all three-state signals, after passing through the first multiplier 342 and the second multiplier 343, the state of the PWM signal remains unchanged, that is, the output signal is still Five-state signal.

The adder 344 is coupled to the first multiplier 342 and the second multiplier 343, respectively. For the signals output by the first multiplier 342 and the second multiplier 343, the adder 344 adds the two and outputs a third PWM signal. Alternatively, the adder 344 can be replaced with a multiplexer.

Since the in-phase local oscillator signal and the quadrature local oscillator signal are all three-state signals, and at the same time, the amplitude of one of the in-phase local oscillator signal and the quadrature local oscillator signal must be 0, therefore, the first multiplier 342 After the five-state signal outputted by the second multiplier 343 is added via the adder 343, the output third PWM signal is still a five-state signal.

Different from the input signal of the digital up-converter directly to the power amplifier in the related art, in the present embodiment, in order to reduce the influence of the PWM harmonic on the output signal, the digital up-converter 340 is further provided with a comb filter 350. Wherein, the suppression band of the comb filter 350 is aligned with the PWM harmonic position, thereby suppressing the PWM harmonics.

The comb filter 350 is a special finite-length unit impulse response (Finite Impulse Response, FIR for short) filter whose structure is related to the modulation period M of the PWM. Illustratively, as shown in FIG. 6, the comb filter 350 includes one cascaded delay unit 351 and one adder 352, l=floor(M/4)-1.

The delay unit 351 is configured to output a third PWM signal delayed by four sampling points, and the adder 352 is configured to perform an addition operation on the two input signals.

Correspondingly, the impulse response function of the comb filter 350 shown in FIG. 6 satisfies:

After the comb filter 350 shown in FIG. 6 receives the third PWM signal outputted by the digital up-converter 340, the first delay unit 351 outputs a third PWM signal delayed by four sampling points, and is added by the first adder 352. Adding the third PWM signal of the current sampling point and the third PWM signal delayed by four sampling points, since the third PWM signal is a five-state signal (five states of -2 to 2), the first adder The signal output by 352 is a nine-state signal (a total of nine states of -4 to 4); further, the second delay unit 351 outputs a third PWM signal delayed by four sampling points, and is paired by the second adder 352. The signal output from one adder is added to the third PWM signal output from the second delay unit, and a thirteen state signal (a total of 13 states of -6 to 6) is output. By analogy, the lth adder 352 adds the signal outputted by the l-1th adder to the third PWM signal outputted by the lth delay unit, and finally outputs an M+1 state signal (-M/2 to M). /2 total M+1 states).

When the third PWM signal is filtered by the comb filter 350, since the suppression of the comb filter 350 is aligned with the position of the PWM harmonic, the PWM harmonic of the third PWM signal after comb filtering is performed. Can be suppressed. Moreover, the comb filter 350 has a simple structure, and only needs to delay and add the third PWM signal, and the implementation complexity is low. Meanwhile, since the number of states (amplitude) of the signal output after comb filtering is small, Therefore, the complexity of subsequent signal processing is low.

In order to increase the power of the output signal, the signal output from the comb filter 350 is further power amplified by the power amplifier 360. In a possible implementation, as shown in FIG. 7, the power amplifier 360 includes a power mapping unit 361, L power output units 362, and a combiner 363, wherein the number of power output units 362 and the comb filter The number of states of the 350 output signal is related, optionally, L = M/2.

One end of the power mapping unit 361 is coupled to the comb filter 350, and the other end is coupled to the L power output units 362, respectively. In order to make the power amplifier 360 operate in the switching state, thereby improving the efficiency of the power amplifier 360, after the power mapping unit 361 receives the multi-amplitude signal outputted by the comb filter 350 (ie, the comb-filtered third PWM signal), The multi-amplitude signal is split into L-channel three-state signals, and the L-channel three-state signals are mapped to L power output units 362.

Optionally, the power mapping unit 361 includes a fetch unit and a framing unit. For the received multi-value signal, the power mapping unit 361 extracts the sign (+ or -) of the multi-value signal by taking the symbol unit, and extracts the amplitude of the multi-value signal by taking the amplitude unit, thereby extracting the The sign and amplitude determine the sign and magnitude of each three-state signal.

Schematically, when the comb-filtered third PWM signal received by the power mapping unit 361 is +n (ie, the multi-value signal is +n), the power mapping unit 361 extracts the symbol to "+" and the amplitude. Is n, thereby determining the L-way three-state letter In the number, the n-way three-state signal is +1, and the Ln-way three-state signal is 0; similarly, when the comb-filtered third PWM signal received by the power mapping unit 361 is -n, the power mapping unit 361 extracts When the sign is "-" and the amplitude is n, thereby determining the L-way three-state signal, the n-way three-state signal is -1, and the Ln-way three-state signal is 0.

Correspondingly, after receiving the respective three-state signals, the L power output units perform power amplification on the three-state signal, and combine and output the L-channel amplified three-state signals through the coupled combiner 363.

In a possible implementation, each power output unit 362 is an SCPA that operates in a switch state for outputting a three-state signal (-1, 0, 1). When the third PWM signal after harmonic suppression is +n, n power output units of the L power output units are used to output a signal of +1 state (via power amplification), and Ln power output units are used for outputting 0 The signal of the state; when the third PWM signal after the harmonic suppression is -n, the n power output units of the L power output units are used to output the signal of the -1 state (via power amplification), Ln power output units A signal for outputting a 0 state.

Finally, the combiner 363 combines the signals output by the L power output units 362, and feeds the combined signals to the antenna, thereby radiating a high-power signal of a predetermined RF frequency by the antenna.

In conjunction with the embodiment illustrated in Figures 3 through 7, in an exemplary embodiment, the structure of the DPA is as shown in Figure 8.

In the DPA shown in FIG. 8, the output bit widths of the first DSM 811 and the second DSM 812 are both 5 bits (including 1-bit sign bits), and the modulation periods of the first PWM 821 and the second PWM 822 are 2 ^{(5- 1)} =16. In the working state, the first PWM 821 and the second PWM 822 modulate the high bit low sampling rate DSM signal, and output a low bit high sampling rate first PWM signal and a second PWM signal, wherein the first PWM signal and The second PWM signal is a three-state signal. After the first PWM signal and the second PWM signal are input to the low pass filter 830, they are respectively filtered by a first-order low-pass filtering unit (combination of Z ^-1 and adder) to output two five-state signals. Further, after receiving the input two-way five-state signal input, the digital up-converter 840 modulates the two five-state signals to a predetermined radio frequency, and outputs a five-state signal of a predetermined radio frequency. The comb filter 850 receives a five-state signal of a predetermined radio frequency, and comb-filters the five-state signal through three internal delay units (Z ^-4 ) and three adders, and finally outputs the power to the power amplifier 860. A seventeen state signal, wherein the impulse response function of the comb filter 850 is h = [1 0 0 0 1 0 0 0 1 0 0 0 1]. The power amplifier 860 includes a power mapping unit 861, eight power amplifying units 862, and a combiner 863. After receiving the input signal, the power mapping unit 861 extracts the symbol and amplitude of the corresponding signal of each sampling point, generates a set of 8 signals (each signal is a three-state signal), and maps 8 signals to 8 signals. The power amplifying unit 862 respectively performs power amplification on the signals received by the eight power amplifying units 862, and finally combines the signals amplified by the eight channels by the combiner 863, schematically, when the power amplifying unit 862 When both are SCPA, the relationship between the input signal and the output signal is shown in Table 1.

Table I

When the DPA output RF high-power signal provided by the embodiment of the present application is used, since the signal input to the digital up-converter is previously subjected to low-pass filtering, the far-end noise of the input signal is reduced; correspondingly, the digital up-converter inputs the signal. When RF modulation is performed, less noise is mixed into the band, which improves the in-band signal-to-noise ratio of the digital inverter output RF signal. In the simulation experiment, as shown in Figure 9, after adding a low-pass filter, the noise of the final output signal of DPA is significantly reduced.

In addition, in the embodiment of the present application, by adding a comb filter after the digital up-converter, the comb-shaped filter is used to perform PWM harmonic suppression on the signal output by the digital up-converter, thereby further improving the quality of the DPA output signal. In the simulation experiment, as shown in Figure 10, after adding the comb filter, the spur of the RF high-power signal output by DPA is significantly reduced in the spectrum, and the main signal (at 2 × 10 ⁹ Hz) and the nearest spur (Located at 2.5×10 ⁹ Hz), the difference is large, and the subsequent high-power RF high-power signal can be obtained without setting a filter (or setting a weaker filter), thereby reducing the manufacturing cost and overall power consumption of the DPA. .

The digital power amplifier described in the embodiment of the present application or a component thereof may be a circuit. This circuit can be implemented by a chip system. The chip system may include: a central processing unit (English: Central Processing, referred to as: UnitCPU), a general-purpose processor, a digital signal processor (English: Digital Signal Processing, referred to as: DSP), an application specific integrated circuit (ASIC), on-site A gate-programmable gate array (English: Field-Programmable Gate Array, FPGA for short) or other programmable logic device, transistor logic device, discrete device, hardware component, or any combination of the above. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The digital power amplifier can also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.

Claims

A digital power amplifier DPA, characterized in that the DPA comprises:

a first differential cumulative modulator DSM, a second DSM, a first pulse wideband modulator PWM, a second PWM, a low pass filter, a digital upconverter, a comb filter, and a power amplifier;

The first PWM is coupled to the first DSM, configured to modulate a first DSM signal input by the first DSM, and output a first PWM signal to the low pass filter;

The second PWM is coupled to the second DSM for modulating a second DSM signal of the second DSM input, and outputting a second PWM signal to the low pass filter, the first DSM signal and The phase difference of the second DSM signal is 90°;

The low pass filter is coupled to the first PWM and the second PWM, respectively, for low pass filtering processing the first PWM signal and the second PWM signal, and upconverting the digital The device outputs a low pass filtered first PWM signal and a low pass filtered second PWM signal;

The digital up-converter is coupled to the low-pass filter for modulating the low-pass filtered first PWM signal and the low-pass filtered second PWM signal, and outputting a predetermined RF frequency to the comb filter Third PWM signal;

The comb filter is coupled to the digital upconverter for suppressing PWM harmonics of the third PWM signal, and outputting a third PWM signal after harmonic suppression to the power amplifier;

The power amplifier is coupled to the comb filter for performing power amplification processing on the third PWM signal after harmonic suppression.
The DPA according to claim 1, wherein the low pass filter comprises a first low pass filtering unit and a second low pass filtering unit, the first low pass filtering unit and the second low pass The filtering units are all first-order low-pass filtering units;

The first low pass filtering unit is coupled to the first PWM, and is configured to add a first PWM signal of a current sampling point and a first PWM signal delayed by one sampling point, and output the first low-pass filtered signal. PWM signal;

The second low pass filtering unit is coupled to the second PWM, and is configured to add a second PWM signal of a current sampling point and a second PWM signal delayed by one sampling point, and output the second low voltage filtered signal. PWM signal.
The DPA according to claim 2, wherein the first PWM signal and the second PWM signal are three-state signals, and the three-state signal includes three states of -1, 0, and 1;

The low pass filtered first PWM signal and the low pass filtered second PWM signal are all five state signals, and the five state signals include -5, -1, 0, 1, and two states.
The DPA according to any one of claims 1 to 3, characterized in that the digital up-converter comprises a digital local oscillator, a first multiplier, a second multiplier and an adder;

The frequency of the digital local oscillator is fs/4, and the digital local oscillator is used to output an in-phase local oscillator signal and a quadrature local oscillator signal, and the in-phase local oscillator signal and the quadrature local oscillator signal are all three states. a signal, wherein a phase difference between the in-phase local oscillator signal and the quadrature local oscillator signal is 90°, fs is a sampling frequency, and the three-state signal includes three states of −1, 0, and 1;

The first multiplier is coupled to the low pass filter and the digital local oscillator, respectively, for using the in-phase local oscillator signal No. modulating the low pass filtered first PWM signal to the predetermined radio frequency;

The second multiplier is coupled to the low pass filter and the digital local oscillator, respectively, for modulating the low pass filtered second PWM signal to the predetermined radio frequency according to the orthogonal local oscillator signal frequency;

The adder is coupled to the first multiplier and the second multiplier, respectively, for adding signals output by the first multiplier and the second multiplier, and outputting the third PWM signal .
The DPA according to claim 4, wherein the low pass filtered first PWM signal and the low pass filtered second PWM signal are five state signals, the digital upconverter output The third PWM signal is a five-state signal, and the five-state signal includes five states of -2, -1, 0, 1, and 2.
A DPA according to any one of claims 1 to 5, characterized in that

The impulse response function of the comb filter satisfies:

Where N is the output bit width of the first DSM and the second DSM, M is the modulation period of the first PWM and the second PWM, and floor(M/4) is M/4 downward Rounded, M=2 (N-1) .
The DPA according to claim 6, wherein the comb filter comprises one cascaded delay unit and one adder, and each delay unit is configured to output a third PWM signal delayed by four sampling points. ;

The first adder is configured to add the third PWM signal of the current sampling point to the third PWM signal output by the first delay unit;

The i-th adder is configured to add the signal output by the i-1th adder to the third PWM signal output by the i-th delay unit, 2≤i≤l.
The DPA according to claim 6 or 7, wherein the third PWM signal output by the digital up-converter is a five-state signal, and the third PWM signal after the harmonic suppression is an M+1 state. signal.
The DPA according to any one of claims 5 to 8, wherein the power amplifier includes a power mapping unit, L power output units, and a combiner, L = M/2;

The power mapping unit is coupled to the comb filter, and configured to split the third PWM signal after the harmonic suppression into an L-channel three-state signal;

The power mapping unit is respectively coupled to the L power output units for mapping the L-way three-state signal to the L power output units, and each power output unit is configured to input the power mapping unit The three-state signal is subjected to power amplification processing;

The combiner is coupled to the L power output units for combining signals output by the L power output units.
The DPA according to claim 9, wherein each of the power output units is a switched capacitor power amplifier SCPA, and each SCPA is used to output a three-state signal;

When the third PWM signal after the harmonic suppression is +n, n of the L power output units are used to output a signal of a +1 state, and Ln power output units are used to output a 0 state. signal of;

When the third PWM signal after the harmonic suppression is -n, n of the L power output units are used to output a signal of -1 state, and Ln power output units are used for outputting a 0 state signal of.