CN110428773A - Display control method, circuit and its display panel - Google Patents
Display control method, circuit and its display panel Download PDFInfo
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- CN110428773A CN110428773A CN201910618034.XA CN201910618034A CN110428773A CN 110428773 A CN110428773 A CN 110428773A CN 201910618034 A CN201910618034 A CN 201910618034A CN 110428773 A CN110428773 A CN 110428773A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of display control method, circuit and its display panel are disclosed, display control method includes the delay area between the adjacent row scan phase of at least two in multiple row scan phases in initial frame period, to obtain the corresponding target frame period；The scanning signal for being in the first level is provided in the multiple row scan phase, provides the scanning signal for being in second electrical level, in the delay area to show corresponding frame picture in each frame period.Display control method and its circuit provided by the invention, display frame rate is reduced by continuous in multiple row scan phases in initial frame period or segmentation delay area, its target frame rate is optional, and the scanning signal for being in second electrical level is provided when its delay area, drives display panel to show corresponding frame picture in each frame period.Display control method provided by the invention, circuit, reduce the power consumption of display panel while reducing picture frame per second.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of display control method, circuit and its display panel.
Background technique
OLED (Organic Light Emitting Diode, organic electroluminescent LED) display panel includes transparent
Anode, metallic cathode and the hole transmission layer being clipped between metallic cathode and transparent anode, luminescent layer, charge transport layer.
OLED display panel, respectively as the anode and cathode of display device, is driven using transparent electrode and metal electrode in certain voltage
Under, electrons and holes are injected into charge transport layer and hole transmission layer from cathode and anode respectively, and electrons and holes are passed through respectively
Electron transfer layer and hole transmission layer move to luminescent layer, and in luminescent layer combine formed exciton make light emitting molecule excitation in turn
Issue visible light.
The frame per second of display panel indicates the speed that display picture changes, i.e. frame per second is higher, and display panel can give birth in 1 second
At picture frame number it is more.OLED display panel generally reduces frame per second by modes such as clock division or frame-skippings at present.However
The above two alternative target frame rate of mode is limited, and there may be macroscopic scintillations.
Summary of the invention
It in view of the above problems, can the purpose of the present invention is to provide a kind of display control method, circuit and its display panel
With by initial frame period modulation to target frame period, and the display quality of display panel can follow the variation in frame period to obtain
Adaptive equalization.
According to an aspect of the present invention, a kind of display control method is provided, including multiple rows scanning in the initial frame period
Delay area between at least two adjacent row scan phases in stage, to obtain the corresponding target frame period；In
The scanning signal for being in the first level is provided in the multiple row scan phase, is provided in the delay area and is in second electrical level
Scanning signal, to show corresponding frame picture in each frame period.
Optionally, the insert continually delay area between two adjacent row scan phases, to obtain the target frame
Period.
Optionally, delay area is segmented between the adjacent scan phase of every two of multiple row scan phases, with
Obtain the target frame period.
Optionally, before being inserted into the delay area, one section of buffer area is inserted between the initial frame period, it is described slow
Area is rushed for connecting initial frame scan phase and frame scan stage adjusted.
Optionally, the mechanical periodicity trend in the frame scan stage of the buffer area characterization adjustment front and back.
Optionally, the display control method further include according to the target frame Periodic Compensation show color, display brightness,
Display power supply.
According to another aspect of the present invention, a kind of display control circuit for display panel, the display panel are provided
Including multirow pixel unit, the control circuit includes control module, in multiple row scan phases in each initial frame period
The scanning signal for being in the first level is provided, to pixel unit described in each row successively to drive the display in each frame period
The corresponding frame picture of Display panel；And adjustment module, it connect, is used for according to indication signal described more with the control module
Delay area between at least two adjacent row scan phases in a row scan phase, to obtain corresponding target frame
In the period, in the delay area, the control module provides the scanning for being in second electrical level to the multirow pixel unit
Signal.
Optionally, the adjustment module includes: configuration unit, presets what multiple groups matched with the different target frame period
Delayed data, according to the selected delayed data to match with the target frame period of the indication signal；Counting unit, even
The configuration unit is connect, according to the selected delayed data, is inserted between at least two adjacent row scan phases
The delay area.
Optionally, according to the delayed data between two adjacent row scan phases insert continually be delayed area,
To obtain the target frame period.
Optionally, divided between the adjacent scan phase of every two of multiple row scan phases according to the delayed data
Section delay area, to obtain the target frame period.
Optionally, the counting unit includes: frame counter；Linage-counter；It is single to connect the configuration for counter controller
Member starts one of the frame counter or linage-counter insertion delay area according to the selected delayed data, wherein
When the counter controller is by between the two adjacent row scan phases of delay area insert continually, control starting institute
It states frame counter and is inserted into the delay area, the multiple rows of section insertion are distinguished into the delay when the counter controller and scan rank
When between the adjacent scan phase of every two of section, control starts the linage-counter and is inserted into the delay area.
Optionally, the delayed data includes delay area, Inserted delay point.
Optionally, further include detection unit, be used for detection frame picture, when testing result is characterized as tableaux, generate
The indication signal obtains the target frame period for adjusting.
Optionally, the frame picture currently read is compared with the frame picture formerly stored, when grayscale difference is in threshold value model
In enclosing, testing result is the tableaux.
Optionally, by the cyclic redundancy of the cyclic redundancy check value of the frame picture currently read and the frame picture formerly stored
Check value compares, and when the previous cycle redundancy check value is constant, testing result is the tableaux.
Optionally, for the picture barycentre offset of the frame picture currently read in setting range, testing result is the static state
Picture.
Optionally, the target frame period is related to the frame number that the tableaux maintains.
Optionally, further include processing unit, connect the counting unit, scan phase of being expert at be inserted into the delay area it
Before, one section of buffer area is inserted between the initial frame period, the buffer area is for connecting initial frame scan phase and adjustment
The frame scan stage afterwards.
Optionally, the mechanical periodicity trend in the frame scan stage of the buffer area characterization adjustment front and back.
Optionally, further include color compensation unit, connect the adjustment module, for the frame picture week according to adjustment front and back
Phase updates gamma curve.
Optionally, further include luminance compensation unit, connect the adjustment module, according to the row picture in the target frame period
The variation tendency of scan period generates a brightness control signal.
It optionally, further include for electric compensation unit, described for electric compensation unit includes burr detector, and detection is in target
The waveform of power supply clock signal under frame per second；Waveform processor connects the burr detector, when detecting the power supply clock
Signal is there are when burr, by the cycle stretch-out of the burr to obtain thermal compensation signal；With door, input terminal receives the power supply clock
Signal and the thermal compensation signal, output end export compensated power supply clock signal.
Optionally, the indication signal is originated from display system.
According to another aspect of the present invention, a kind of display panel is provided, including display control circuit described above.
Optionally, the display panel includes organic LED display panel, LED display panel, liquid crystal
Display panel.
Display control method provided by the invention and its display control circuit pass through multiple rows scanning in the initial frame period
Continuous or segmentation delay area is in stage to reduce display frame rate, and target frame rate is optional, and when its delay area
The scanning signal for being in second electrical level is provided, i.e., control driving circuit stops scanning when the scanning signal is in second electrical level, because
This display control method provided by the invention, circuit, reduce the power consumption of display panel while reducing picture frame per second.
Preferably, which is also provided with processing unit, for being first inserted into one section of buffering before frame per second adjustment
Area, to connect the scan phase and the scan phase in target frame period in initial frame period so that picture show it is more smooth, further
It ensure that display quality.
Preferably, the invention shows control circuits to be also provided with compensating module, is used for the adaptive equalization when reducing frame per second
Show picture brightness, display picture color and display power supply so that display panel frame per second reduce when can still guarantee it is high-quality
Amount display.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the structural schematic diagram of the display panel provided according to embodiments of the present invention.
Fig. 2 shows a kind of structural schematic diagrams of display control circuit of offer according to embodiments of the present invention.
Fig. 3 A, which shows display control circuit in Fig. 2, reduces a kind of principle schematic diagram of frame per second.
Fig. 3 B, which shows display control circuit in Fig. 2, reduces another principle schematic diagram of frame per second.
Fig. 4 shows the structural schematic diagram of another display control circuit provided according to embodiments of the present invention.
Fig. 5, which shows display control circuit in Fig. 4, reduces the principle schematic diagram of frame per second.
The waveform diagram of power supply clock signal when Fig. 6 shows the frame per second reduction provided according to embodiments of the present invention.
Fig. 7 shows the structural schematic diagram for electric compensation unit provided according to embodiments of the present invention.
Fig. 8 shows the waveform diagram that waveform processor works in different mode in Fig. 7.
Fig. 9 shows the waveform diagram for the brightness control signal that luminance compensation unit provides in Fig. 4.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
Fig. 1 shows the structural schematic diagram of the display panel provided according to embodiments of the present invention.
As shown in Figure 1, display panel 1000 provided in an embodiment of the present invention is illustrated by taking OLED display panel as an example, so
And display panel of the invention can also be LED display panel or liquid crystal display panel.Display panel 1000 includes
Pixel array 1100, driving circuit 1200 and display control circuit 1300.
Pixel array 1100 includes that N row M arranges the N × M pixel unit 1110 that is arranged in array, with N=in the present embodiment
4, it is described in detail for M=6.Including Organic Light Emitting Diode and for controlling organic light emission two in each pixel unit 1110
The multiple switch element of pole pipe on or off.
Driving circuit 1200 connects each pixel unit 1110 in pixel array 1100, for mentioning to pixel unit 1110
For corresponding pixel data, and scanning element unit 1110 is controlled to realize the display function of display panel.Specifically, driving electricity
Road 1200 includes row drive module 1210 and column drive module 1220.Column drive module 1220 connects respectively via data line S1-S6
The input terminal for connecing a column pixel unit 1110, for providing corresponding pixel data.Row drive module 1210 is via scan line G1-
G4 is separately connected the control terminal of one-row pixels unit 1110, for providing row gating signal.
When row drive module 1210 provides control terminal of the row gating signal to pixel unit 1110, pixel unit 1110 will
The received pixel data write-in of input terminal, and glow current realization is generated to Organic Light Emitting Diode charging and is shone, and then is realized
Display function.
Display control circuit 1300 connects driving circuit 1200, shows for being adjusted according to 1000 actual demand of display panel
Panel frame per second, and based on frame per second compensation display brightness, color and the power supply etc. after adjusting, so that display panel 1000 is in frame per second
It can still guarantee high-quality display when reduction.Specifically, display control circuit 1300 is receiving the indication signal for reducing frame per second
Afterwards, one section of delay area is inserted into the initial frame period, to obtain the target frame period of characterization target frame rate, wherein in initial frame week
The scan phase of phase provides the scanning signal for being in the first level to driving circuit 1200, to driving circuit 1200 in delay area
The scanning signal for being in second electrical level is provided, to drive the driving circuit 1200 of display panel to show in each target frame period
Corresponding frame picture.
Wherein, of the invention is in embodiment, and the first level can be one of high level or low level, second electrical level example
Such as with the first level on the contrary, the first level, which for example characterizes scanning signal, is in effective status, normal scan shows frame picture at this time,
Second electrical level for example characterizes scanning signal and is in invalid state, stops scanning at this time.
Fig. 2 shows a kind of structural schematic diagrams of display control circuit of offer according to embodiments of the present invention.
As shown in Fig. 2, display control circuit 1300 includes adjustment module 1310, control module 1320 and compensating module
1330。
Adjustment module 1310 for example receives the indication signal for reducing frame per second, in multiple row scan phases in initial frame period
At least two adjacent row scan phases between delay area, to obtain the corresponding target frame period.Wherein, the delay area
It can continuously be inserted into two adjacent rows scan phases of initial frame picture, can also be segmented and be inserted into initial frame picture
In between multiple row picture scan phases, it is preferable that this section delay area can with piecewise uniform be inserted into initial frame picture
In each row picture scan phase, wherein insertion point for example can be in any position of each initial row picture scan phase.Tool
Body, adjustment module 1310 includes configuration unit 1311, counting unit 1312.
The delayed data that configuration unit 1311 presets multiple groups and the different target frame period matches, delayed data include
Be delayed area, Inserted delay point.When configuration unit 1311 receives the indication signal for reducing frame per second, select and target frame period phase
Matched delayed data.Configuration unit 1311 is, for example, configurable register.
Counting unit 1312 connects configuration unit 1311 to receive one group of selected delayed data, and is believed according to reception delay
Breath delay area between at least two adjacent row scan phases, to obtain embodying the target frame period of target frame rate.Tool
Body, counting unit 1312 can control the phase being continuously inserted into this whole section delay area in the initial frame picture scan period
Between adjacent two row scan phases, it also can control and this whole section delay be distinguished into for example uniform or non-uniform several segments
It is inserted between the every two adjacent rows scan phase of multiple row picture scan phases of initial frame picture.Specifically, it counts single
Member 1312 includes counter controller, linage-counter and frame counter.Counter controller receives the output of configuration unit 1311
Delayed data is started frame counter according to delayed data and is swept with the two neighboring row of multiple row scan phases in initial frame picture
It retouches and is continuously inserted into one whole section of delay area between the stage, or control starting linage-counter is to be distinguished into example for this whole section delay
Such as every two row for multiple row picture scan phases that such as uniform or non-uniform several segments are inserted into initial frame picture is swept
It retouches between the stage.Preferably, multiple row picture scan phases may include each row picture scanning in an initial frame picture
Stage.Counting unit 1312 is by the characterization target frame period adjusted provided by one of frame counter or linage-counter later
Information output.
Control module 1320 is successively in the offer of each row pixel unit in multiple row scan phases in each frame period
The scanning signal of first level, to drive display panel to show corresponding frame picture in each frame period.Control module 1320
Connection adjustment module 1310, in delay area, control module 1320, multirow pixel unit, which provides the scanning in second electrical level, to be believed
Number, display panel for example keeps display previous frame picture or does not show picture at this time.
The connection adjustment module 1310 of compensating module 1330 is bright to be shown according to target frame period adaptive compensation adjusted
Degree, color and power supply, so that display panel 1000 can still guarantee high-quality display when frame per second reduces.
Wherein, the received indication signal of display control circuit provided in this embodiment both can directly from display system,
It can also be generated by detection unit 1314, it is preferable that indication signal can also be total by display system and detection unit 1314
With offer.Specifically, detection unit 1314 is used for detection frame picture, when the picture for detecting at least two frame pictures is identical or
It is tableaux, the indication signal that detection unit 1314 generates for reducing frame per second that initial frame information is characterized when similar.Wherein, mesh
It is related with the frame number that tableaux maintains to mark the frame period, when the same or similar frame number of frame picture is more, the target frame period and
The difference in initial frame period is bigger.Wherein, the identical method of discrimination of frame picture is see following several: one, more presently written
Whether frame picture data and stored frame picture data are identical, determine that picture is identical if data are identical；Two, compare present frame
Whether the cyclic redundancy check value of picture is consistent with the cyclic redundancy check value of former frame picture, determines that picture is identical if consistent；
Three, frame picture write instruction is monitored, when monitoring new write command, then determines that the picture of write-in and original picture be not identical,
Otherwise picture is identical.The similar method of discrimination of frame picture is see following several: one, more presently written frame picture data with
The absolute difference of the frame picture data of storage then determines that picture is similar when the absolute value is within range of set value；Two, compare
The absolute difference of more presently written frame picture data and stored frame picture data, is setting if the absolute value is added up
Within the scope of value, then determine that picture is similar；Three, the image block center of gravity for calculating presently written frame picture, when barycentre offset not
Then determine that picture is similar more than setting value, wherein the image block of frame picture is, for example, a line picture, three colors in a line picture
Sub-pixel value can for example calculate separately；Four, the whole image center of gravity for calculating presently written frame picture, when barycentre offset not
Then determine that picture is similar more than setting value, wherein three sub-pixels values in entire picture image can for example calculate separately；Five,
The new method of discrimination that above four kinds of method various combinations are formed still can differentiate whether picture is similar, no longer arranges one by one herein
The combination of act method, but above method any combination belong to it is proposed by the present invention for differentiating the similar method of picture.
Preferably, detection unit 1314 can be directly connected to control module 1320, when certain row for detecting initial frame picture
When picture is characterized as Blank pictures, the scanning signal in second electrical level is provided and acts on control module 1320 to control driving electricity
Road resets or stops scanning.
Fig. 3 A, which shows display control circuit in Fig. 2, reduces a kind of principle schematic diagram of frame per second, and Fig. 3 B is shown in Fig. 3
Another principle schematic diagram of display control circuit reduction frame per second.
As Fig. 3 A shows the counting unit 1312 of adjustment module 1310 by starting frame counter in initial frame picture
One whole section of delay area is inserted between two neighboring row scan phase in scan phase, continuously to obtain the characterization target frame period
Target frame information.By being continuously inserted into one whole section after insertion point within the frame picture scan period of initial frame per second F0
Be delayed area.Wherein under the adjustment modes, between two adjacent row scan phases when delay area, mould is accordingly controlled
Block provides the scanning signal for being in second electrical level to the rear end driving circuit of display panel, and rear end driving circuit for example stops to picture
Multirow pixel unit scanning in pixel array, display panel for example shows previous frame picture or does not show picture at this time.
As Fig. 3 B shows the counting unit 1312 of adjustment module 1310 by starting linage-counter in initial frame picture
One section of delay area is respectively inserted between the every two row scan phase of multiple row scan phases in scan phase, to obtain table
Levy the target frame information in target frame period.By within the frame picture scan period of initial frame per second F0, in multiple row scan phases
Insertion point after be inserted into respectively it is a bit of delay area after obtain target frame rate be F1 the frame picture scan period.The wherein adjustment
Under mode, between every two adjacent row scan phase when delay area, accordingly control module is to after display panel
Driving circuit is held to provide the scanning signal for being in second electrical level, rear end driving circuit for example stops to the multirow picture in pixel array
Plain unit scan, display panel for example shows previous frame picture or does not show picture at this time.
The above two mode for reducing frame per second, the former is one section of delay area of insert continually in an initial frame period, after
Person is to be inserted into one section of delay area respectively in multiple initial line-scanning periods in an initial frame period.In practical applications,
The above two mode for reducing frame per second can be selected according to the actual situation.
In the present embodiment, frame per second is reduced by two kinds of optional adjustment modes, the display for both having met display panel needs
It asks, while reducing the control complexity of control module again.And the present embodiment is believed by providing the scanning in second electrical level
Number mode enter the area that is delayed in initial frame cycle interpolation, while the power consumption for reducing display panel, also reduce for controlling
The power consumption of the integrated circuit of display panel processed.Preferably, compensating module, In are additionally provided in the display control circuit of the present embodiment
While reducing frame per second, display picture brightness, display picture color and display power supply are compensated to being adapted to property.
Fig. 4 shows the structural schematic diagram of another display control circuit provided according to embodiments of the present invention.Fig. 5 is shown
Display control circuit reduces the principle schematic diagram of frame per second in Fig. 4.Fig. 6 shows the frame per second provided according to embodiments of the present invention
The waveform diagram of power supply clock signal when reduction.Fig. 7 show provide according to embodiments of the present invention for electric compensation unit
Structural schematic diagram.Fig. 8 shows the waveform diagram that waveform processor works in different mode in Fig. 7.Fig. 9 shows Fig. 4
The waveform diagram for the brightness control signal that middle luminance compensation unit provides.
It is small by being inserted into one respectively in multiple initial row scan phases in an initial frame period in following embodiment
The mode in section delay area reduces the frame per second of display panel.
As shown in figure 4, display control circuit 2300 on the basis of display control circuit 1300, increases in adjustment module
Processing unit 2313, i.e. display control circuit 2300 include adjustment module 2310, control module 2320, compensating module 2330.
Adjusting module 2310 includes detection unit 2314, configuration unit 2311, processing unit 2313 and counting unit
2312。
Processing unit 2313 is connected between detection unit 2314 and counting unit 2312, when target frame rate and initial frame per second
Absolute difference when except predetermined value, can star processing unit 2313, frame per second adjustment before first be inserted into one section of buffer area,
For connecting initial frame scan phase and frame scan stage adjusted.Wherein, the frame scan rank of buffer area characterization adjustment front and back
The mechanical periodicity trend of section.Specifically, it is described further in conjunction with Fig. 5.
As shown in figure 5, the frame per second of picture M1 is that F0 is needed when receiving indication signal and needing frame per second being reduced to F1
Continuous or segmentation delay area in turn will in the frame picture scan phase that frame per second is F0 with extending the frame picture scan period
Frame per second is reduced to F1, however when extending suddenly the frame picture scan period, it may be such that image display quality is deteriorated, to avoid
Above situation, the starting of processing unit 2313 are inserted into a buffer area D1 before frame per second adjusts, wherein the frame-scan period of buffer area D1
Uniform or non-uniform extension when so that the frame per second of picture M2 being reduced to F1 from F0, is inserted into frame picture scan phase
Buffer time gradually extends.Similarly, when receiving indication signal and needing frame per second being reduced to F2 from F1, it still can star place
Reason unit 2313 is inserted into a buffer area D2 before adjust frame per second, wherein in the D2 of buffer area each frame picture scan phase it is uniform or
The non-uniform extension of person, when so that the frame per second of picture M2 being reduced to F2 from F1, when the buffering being inserted into the frame picture scan period
Between gradually extend.
Wherein, processing unit 2313 can be when the absolute difference of target frame rate and initial frame per second is when except predetermined value
Automatic starting according to artificial control starting or can also close, and the buffer circle that processing unit 2313 is inserted into can be with people
For adjustment.
The invention shows the compensating modules 2330 in control circuit to be used for when reducing frame per second, and adaptive equalization shows picture
Brightness, display picture color and display power supply.Compensating module 2330 includes color compensation unit 2331, for electric compensation unit
2332 and luminance compensation unit 2333.
Color compensation unit 2331 receives the luma data of adjustment module output, is characterized when the target frame period adjusted
Frame per second reduce when, color compensation unit 1331 be used for according to initial frame period and target frame period modulation original gamma adjusted
The several segmentations of certain of curve generate new gamma curve, to guarantee that the color of display picture does not occur partially because frame per second reduces
The abnormal phenomenon such as color.Preferably, when frame per second reduces, the changing value of gamma curve should be with the row scan phase of the buffer area of insertion
Period keep coordinate so that compensated gamma curve frame per second reduce in the case of to driving circuit generate driving believe
It number is corrected, ensure that display picture color is not abnormal phenomenon.
Preferably, when compensating gamma curve, only certain several segmentation of former gamma curve are adjusted, i.e., to a few
When a segmentation zooms in and out processing, hardware resource can be saved, hardware cost of the invention is reduced.
Power supply clock signal is compensated for electric compensation unit 2332, which is used for display panel late-class circuit
Power supply is provided.The waveform diagram of the power supply clock signal gone out as shown in connection with fig. 6, as shown in fig. 6, being supplied in initial frame per second F0
The period of electrical clock signal CLK1 is according to the mechanical periodicity of initial row scan phase.Target frame rate F1 is reduced in initial frame per second F0
When, the period of target line scan phase changes, and the period of clock signal CLK3 follows target line scan phase while power is being supplied
When mechanical periodicity, the waveform of power supply clock signal CLK3 will not generate burr, but when the period of target line scan phase is too long
When, the frequency of power supply clock signal CLK3 is too low, can make voltage instability.Therefore, target frame rate is reduced in initial frame per second F0
When F1, the period of power supply clock signal CLK2 can be unstable to avoid power supply when still following the mechanical periodicity of initial row scan phase
The phenomenon that occur, but the waveform of power supply clock signal CLK2 there may be burr influence normal power supply.
Therefore, it is arranged in display control circuit above-mentioned because frame per second reduces the power supply introduced to solve for electric compensation unit 2332
Abnormal problem.As shown in Figure 7,8, for electric compensation unit 2332 include burr detector 23321, waveform processor 23322 and
Logic gate U1.For electric compensation unit 2332 burr detector 23321 receive frame per second reduce after by Waveform generator output
When power supply clock signal CLK, when the period suddenly change of row scan phase, the burr in waveform is detected, when detecting hair
When thorn, waveform processor 23322 broadens the period of the burr occurred in waveform to obtain thermal compensation signal CLK4, and burr is multiple at this time
Position no longer influences power supply.Two input terminals of logic gate U1 are separately connected the thermal compensation signal of 23322 output end of waveform processor output
The CLK4 and power supply clock signal CLK of Waveform generator output, and compensated power supply clock signal is exported by output end
CLK5.Wherein, do not changed, the logic with the variation of frame per second by the period of the power supply clock signal CLK of Waveform generator output
Door U1 be, for example, with door or or the logical devices such as door, be, for example, in the present embodiment and door.
However when detecting burr, when waveform processor 23322 removes the burr occurred in waveform, burr meeting at this time
It is distorted, the compensation effect in turn resulting in power supply clock signal is deteriorated.Therefore, provided by the invention for electric compensation unit 2332
After detecting burr, processing is broadened to compensate power supply clock signal to the period of burr, ensure that display panel is dropped in frame per second
Normal power supply is remained in the case of low.
Luminance compensation unit 2333 is used for when display panel frame per second reduces, and compensation brightness controls signal, to guarantee to show
Panel display brightness when frame per second reduces still remains normal.Specifically, as shown in connection with fig. 9, when scan period VST is initial frame
When the scan period T0 of picture, the amplitude of brightness control signal BC is initial value, when frame per second adjusts one buffer area of insertion, currently
The period of scan phase follows the mechanical periodicity of the scan phase in buffer area, and the amplitude of brightness control signal BC is with covariant at this time
Change, when extending to T1 after the scan period is by insertion buffer area, the amplitude of brightness control signal remains unchanged.Then, when
When scan period is changed to T2 from T1, such as can first it restore from first object frame per second T1 to initial frame per second T0, then from initial frame
Rate T0 is reduced to the second target frame rate T2, at this point, still root with the variation of frame per second compensates adjustment to brightness control signal BC, with
So that display panel display brightness when frame per second reduces still remains normal.Wherein, restore from target frame rate to initial frame per second example
Such as realized by resetting adjustment module 2310.
Display panel provided by the invention includes display control circuit described above, wherein the display panel includes
OLED display panel.
Display control method provided by the invention executes in above-mentioned display control circuit.The display control method is main
It include: the delay area between at least two adjacent row scan phases in multiple row scan phases in frame period, with
To the corresponding target frame period；The scanning signal for being in the first level is provided in multiple row scan phases, in delay Qu Zhongti
For being in the scanning signal of second electrical level, to show corresponding frame picture in each frame period.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (25)
1. a kind of display control method, which is characterized in that the described method includes:
The delay between the adjacent row scan phase of at least two in multiple row scan phases in initial frame period
Area, to obtain the corresponding target frame period；
The scanning signal for being in the first level is provided in the multiple row scan phase, is provided in the delay area and is in the
The scanning signal of two level, to show corresponding frame picture in each frame period.
2. display control method according to claim 1, which is characterized in that two adjacent row scan phases it
Between insert continually be delayed area, to obtain the target frame period.
3. display control method according to claim 1, which is characterized in that in the every two of multiple row scan phases
Delay area is segmented between adjacent scan phase, to obtain the target frame period.
4. display control method according to claim 1, which is characterized in that before being inserted into the delay area, described
One section of buffer area is inserted between the initial frame period, the buffer area is for connecting initial frame scan phase and frame scan adjusted
Stage.
5. display control method according to claim 4, which is characterized in that the frame of the buffer area characterization adjustment front and back is swept
Retouch the mechanical periodicity trend in stage.
6. display control method according to claim 1, which is characterized in that further include:
Color, display brightness, display power supply are shown according to the target frame Periodic Compensation.
7. a kind of display control circuit for display panel, the display panel includes multirow pixel unit, which is characterized in that
The control circuit includes:
Control module successively has to the offer of pixel unit described in each row in multiple row scan phases in each initial frame period
The scanning signal of first level, to drive the display panel to show corresponding frame picture in each frame period；And
Adjust module, connect with the control module, for according to indication signal in the multiple row scan phase at least
Delay area between two adjacent row scan phases, to obtain the corresponding target frame period,
Wherein, in the delay area, the control module is provided to the multirow pixel unit in described in second electrical level
Scanning signal.
8. display control circuit according to claim 7, which is characterized in that the adjustment module includes:
Configuration unit presets the delayed data that multiple groups match with the different target frame period, is selected according to the indication signal
The fixed delayed data to match with the target frame period；
Counting unit connects the configuration unit, according to the selected delayed data, sweeps in at least two adjacent rows
It retouches and is inserted into the delay area between the stage.
9. display control circuit according to claim 8, which is characterized in that according to the delayed data two adjacent
Insert continually delay area between the row scan phase, to obtain the target frame period.
10. display control circuit according to claim 8, which is characterized in that according to the delayed data multiple described
Delay area is segmented between the adjacent scan phase of the every two of row scan phase, to obtain the target frame period.
11. display control circuit according to claim 8, which is characterized in that the counting unit includes:
Frame counter；
Linage-counter；
Counter controller connects the configuration unit, starts the frame counter or row according to the selected delayed data
One of counter is inserted into the delay area,
Wherein, when the counter controller is by between the two adjacent row scan phases of delay area insert continually,
Control starts the frame counter and is inserted into the delay area, and section is distinguished in the delay when the counter controller and is inserted into multiple institutes
When stating between the adjacent scan phase of every two of row scan phase, control starts the linage-counter and is inserted into the delay area.
12. display control circuit according to claim 8, which is characterized in that the delayed data includes delay area, delay
Insertion point.
13. display control circuit according to claim 7, which is characterized in that further include:
Detection unit generates the indication signal, is used for for detection frame picture when testing result is characterized as tableaux
Adjustment obtains the target frame period.
14. display control circuit according to claim 13, which is characterized in that by the frame picture currently read with formerly deposit
The frame picture of storage compares, and when grayscale difference is in threshold range, testing result is the tableaux.
15. display control circuit according to claim 13, which is characterized in that the circulation of the frame picture currently read is superfluous
Remaining check value compared with the cyclic redundancy check value of the frame picture formerly stored, when the previous cycle redundancy check value not
Become, testing result is the tableaux.
16. display control circuit according to claim 13, which is characterized in that the picture center of gravity of the frame picture currently read
For offset in setting range, testing result is the tableaux.
17. display control circuit according to claim 13, which is characterized in that the target frame period and the static picture
The frame number that face maintains is related.
18. display control circuit according to claim 8, which is characterized in that further include:
Processing unit connects the counting unit, and scan phase of being expert at is inserted into before the delay area, in the initial frame period
Between be inserted into one section of buffer area, the buffer area is for connecting initial frame scan phase and frame scan stage adjusted.
19. display control circuit according to claim 18, which is characterized in that the frame of the buffer area characterization adjustment front and back
The mechanical periodicity trend of scan phase.
20. display control circuit according to claim 7, which is characterized in that further include:
Color compensation unit connects the adjustment module, for updating gamma curve according to the frame picture cycle of adjustment front and back.
21. display control circuit according to claim 7, which is characterized in that further include:
Luminance compensation unit connects the adjustment module, is become according to the variation of the row picture scan period in the target frame period
Gesture generates a brightness control signal.
22. display control circuit according to claim 7, which is characterized in that further include the power supply for electric compensation unit
Compensating unit includes:
Burr detector, the waveform of power supply clock signal of the detection under target frame rate；
Waveform processor connects the burr detector, when detecting the power supply clock signal there are when burr, by the hair
The cycle stretch-out of thorn is to obtain thermal compensation signal；
Logic gate, input terminal receives the power supply clock signal and the thermal compensation signal, when output end exports compensated power supply
Clock signal.
23. display control circuit according to claim 7, which is characterized in that the indication signal is originated from display system.
24. a kind of display panel, which is characterized in that including the described in any item display control circuits of claim 7-23.
25. display panel according to claim 24, which is characterized in that the display panel includes Organic Light Emitting Diode
Display panel, LED display panel, liquid crystal display panel.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112837641A (en) * | 2019-11-25 | 2021-05-25 | 敦泰电子股份有限公司 | Display low frame rate mode driving method |
| CN112885310A (en) * | 2021-01-25 | 2021-06-01 | 北京欧铼德微电子技术有限公司 | Driving method and device and electronic equipment |
| CN115019749A (en) * | 2022-06-07 | 2022-09-06 | 福建华佳彩有限公司 | Panel display system capable of automatically and dynamically adjusting refresh rate |
| CN115273719A (en) * | 2022-07-18 | 2022-11-01 | 晟合微电子(肇庆)有限公司 | Display drive IC containing frame buffer, display system and frame rate control method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093658A (en) * | 2006-05-30 | 2007-12-26 | 英特尔公司 | Conversion of display refreshing speed |
| US20080143729A1 (en) * | 2006-12-15 | 2008-06-19 | Nvidia Corporation | System, method and computer program product for adjusting a refresh rate of a display for power savings |
| CN101286735A (en) * | 2008-05-29 | 2008-10-15 | 那微微电子科技（上海）有限公司 | Delay device of reset signal |
| US20100277512A1 (en) * | 2009-04-30 | 2010-11-04 | Tzu-Chiang Shen | Frame rate adjuster and method thereof |
| CN102194409A (en) * | 2010-03-18 | 2011-09-21 | 精工爱普生株式会社 | Image processing device, display system, electronic apparatus, and image processing method |
| CN104751757A (en) * | 2013-12-31 | 2015-07-01 | 乐金显示有限公司 | Display device capable of driving at low speed |
| US20170124964A1 (en) * | 2012-03-15 | 2017-05-04 | Japan Display Inc. | Liquid crystal display device, driving method of liquid crystal display device and electronic apparatus |
| CN106782259A (en) * | 2015-09-25 | 2017-05-31 | 乐金显示有限公司 | Display device and the method for driving the display device |
| CN108109583A (en) * | 2016-11-25 | 2018-06-01 | 乐金显示有限公司 | El display device and its driving method |
-
2019
- 2019-07-10 CN CN201910618034.XA patent/CN110428773B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093658A (en) * | 2006-05-30 | 2007-12-26 | 英特尔公司 | Conversion of display refreshing speed |
| US20080143729A1 (en) * | 2006-12-15 | 2008-06-19 | Nvidia Corporation | System, method and computer program product for adjusting a refresh rate of a display for power savings |
| CN101286735A (en) * | 2008-05-29 | 2008-10-15 | 那微微电子科技（上海）有限公司 | Delay device of reset signal |
| US20100277512A1 (en) * | 2009-04-30 | 2010-11-04 | Tzu-Chiang Shen | Frame rate adjuster and method thereof |
| CN102194409A (en) * | 2010-03-18 | 2011-09-21 | 精工爱普生株式会社 | Image processing device, display system, electronic apparatus, and image processing method |
| US20170124964A1 (en) * | 2012-03-15 | 2017-05-04 | Japan Display Inc. | Liquid crystal display device, driving method of liquid crystal display device and electronic apparatus |
| CN104751757A (en) * | 2013-12-31 | 2015-07-01 | 乐金显示有限公司 | Display device capable of driving at low speed |
| CN106782259A (en) * | 2015-09-25 | 2017-05-31 | 乐金显示有限公司 | Display device and the method for driving the display device |
| CN108109583A (en) * | 2016-11-25 | 2018-06-01 | 乐金显示有限公司 | El display device and its driving method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112837641A (en) * | 2019-11-25 | 2021-05-25 | 敦泰电子股份有限公司 | Display low frame rate mode driving method |
| CN112837641B (en) * | 2019-11-25 | 2023-09-12 | 敦泰电子股份有限公司 | Display low frame rate mode driving method |
| CN112885310A (en) * | 2021-01-25 | 2021-06-01 | 北京欧铼德微电子技术有限公司 | Driving method and device and electronic equipment |
| CN112885310B (en) * | 2021-01-25 | 2022-05-03 | 北京欧铼德微电子技术有限公司 | Driving method and device and electronic equipment |
| CN115019749A (en) * | 2022-06-07 | 2022-09-06 | 福建华佳彩有限公司 | Panel display system capable of automatically and dynamically adjusting refresh rate |
| CN115273719A (en) * | 2022-07-18 | 2022-11-01 | 晟合微电子(肇庆)有限公司 | Display drive IC containing frame buffer, display system and frame rate control method |
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|---|---|
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