CN115273719A - Display drive IC containing frame buffer, display system and frame rate control method - Google Patents

Display drive IC containing frame buffer, display system and frame rate control method Download PDF

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Publication number
CN115273719A
CN115273719A CN202210843449.9A CN202210843449A CN115273719A CN 115273719 A CN115273719 A CN 115273719A CN 202210843449 A CN202210843449 A CN 202210843449A CN 115273719 A CN115273719 A CN 115273719A
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China
Prior art keywords
frame rate
display
frame
period
adjusting
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CN202210843449.9A
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Chinese (zh)
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成昶昊
郑凯
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Shenghe Microelectronics Zhaoqing Co ltd
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Shenghe Microelectronics Zhaoqing Co ltd
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Priority to CN202210843449.9A priority Critical patent/CN115273719A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A display drive IC containing a frame buffer, a display system and a frame rate control method relate to the field of display drive ICs. When the image is not changed within the specified duration, the display drive IC automatically reduces the frame rate; and when an event of changing the image is received, the display driving IC immediately returns to the frame rate of the normal state, so that the power consumption of the whole display system is reduced on the premise of not reducing the image quality.

Description

Display drive IC containing frame buffer, display system and frame rate control method
Technical Field
The invention relates to the technical field of display driver ICs (Integrated circuits), in particular to a frame rate control method of a display driver IC with a built-in frame buffer, a display driver IC with a frame buffer and a display system with the display driver IC.
Background
In a general display system using a display driver IC (hereinafter, simply referred to as a driver IC) having a built-in frame buffer, image data information is transmitted to a display panel through the driver IC at a predetermined frame rate such as 60Hz, 30Hz, 50Hz, or 120Hz depending on an operation mode, but an AP (application processor) used outside the driver IC does not always transmit image data at the predetermined frame rate, but transmits image data to the driver IC when an image to be displayed is changed, and does not transmit image data.
Even if the AP does not transmit data, since the image information of the previous frame is stored in the built-in frame memory of the driver IC, the driver IC performs a display operation using the data at a predetermined frame rate. If the AP does not transmit image data for a longer time, the same picture without change is displayed on the display panel during that time.
The conditions for changing the display screen of the panel are as follows: the AP transmits new image data, changes a DBV (display luminance value) value for controlling image luminance, changes a condition of a color enhancement function for changing image quality characteristics, and the like.
Generally, if the frame rate is lowered for display, a phenomenon of deterioration in picture quality such as flickering or picture darkening occurs. However, when the same image is displayed for a long time, the frame rate can be reduced to a certain level while avoiding degradation of the image quality to the extent that the user can see with the naked eye.
In a display system, the most important factors determining power consumption are: a data transfer frequency between the AP and the driver IC, an operation frequency at which the driver IC transmits data to the panel and drives the panel, a number of operations per unit time at which various functions are autonomously operated inside the driver IC, and the like.
If the frame rate of the driver IC can be lowered while maintaining the same image quality, the number of data transfers and panel driving between the driver IC and the panel can be reduced, and the power consumption of the entire display system can be reduced by reducing the operation of the driver IC itself.
In view of the above-mentioned studies, the present invention has been made.
Disclosure of Invention
The invention aims to provide a display drive IC with a frame buffer, a display system and a frame rate control method, which can enable the display drive IC to lower the frame rate by itself and drive a display panel under the condition that an image needing to be displayed is not changed within a specified time length, and reduce the power consumption of the whole system under the premise of not lowering the image quality.
The general concept of the invention is: if the external AP does not transmit image data within the predetermined time period and the brightness information and image quality conditions are not changed, the driver IC displays the image at a frame rate lower than a predetermined frame rate (for example, 60 Hz). In the state where the frame rate is lowered, if a condition for changing the image data is not generated within a specified period of time, the frame rate is lowered again for display. In this way, the frame rate is gradually lowered in predetermined stages and displayed. If the condition of changing the panel display image occurs during the display in the state of lowering the frame rate by operating the function in the driving IC, the display state should be immediately returned to the frame rate (for example, 60 Hz) designated by the normal state, so that the image quality of the screen in the changed state can be prevented from being deteriorated.
The technical scheme adopted by the invention is as follows:
a frame rate control method of a display driver IC having a built-in frame buffer includes:
when the image is not changed within the appointed time length, the display driving IC automatically reduces the frame rate; and
when an event of changing an image is received, the display drive IC immediately returns to the frame rate of the normal state.
In the above frame rate control method, it is preferable that a plurality of stages for lowering the frame rate are included, and the specified time length used for determining whether each stage enters the next stage is the same or different. Moreover, after each stage enters the next stage, the rate of frame rate reduction may be the same or different.
In the above-described frame rate control method, it is preferable that the specified time period is measured using a Real Time Clock (RTC), a watchdog timer (WDT), or a frame counter.
In the above frame rate control method, preferably, the event of changing the image includes: the display driver IC receives image data input by the application processor, a DBV different from the DBV currently used by the display driver IC and input by the application processor, or data for changing the image quality and color and input by the application processor.
In the above frame rate control method, preferably, the method for the display driver IC to lower the frame rate by itself includes: adjusting the length of HFP (horizontal front porch) and HBP (horizontal back porch) to adjust the period of HSYNC (horizontal synchronization); and/or adjusting the length of the VFP (Vertical front porch) and VBP (Vertical back porch) to adjust the period of VSYNC (Vertical Synchronization); and/or adjusting a period of an oscillator clock used in the display drive IC; and/or adjusting the ratio of display frames to skipped frames.
A display driver IC with a built-in frame buffer, comprising: the frame rate reducing device is used for reducing the frame rate of the display drive IC when the event of changing the image does not exist in the specified duration; and a frame rate restoring means for immediately returning the display drive IC to the frame rate of the normal state when an event for changing the image is received.
In the display driver IC including the built-in frame buffer, preferably, the frame rate reduction means includes a plurality of frame rate reduction sub-means connected in cascade, and is capable of reducing the frame rate in a plurality of stages.
In the above display drive IC with a built-in frame buffer, preferably, the frame rate reduction device includes: the HSYNC cycle adjusting sub-device is used for adjusting the lengths of HFP and HBP so as to adjust the cycle of HSYNC; and/or a VSYNC cycle adjusting sub-device, which is used for adjusting the length of VFP and VBP so as to adjust the cycle of VSYNC; and/or a clock period adjusting sub-means for adjusting a period of an oscillator clock used in the display drive IC; and/or a frame ratio adjusting sub-means for adjusting the ratio of the display frame to the frame skipping.
A display system comprises an application processor, a display drive IC with a built-in frame buffer, and a display panel, wherein the display drive IC is the display drive IC, the frame rate reduction device and the frame rate restoration device detect data input by the application processor, and further adjust the frame rate of sending image data to the display panel.
Compared with the prior art, the invention has at least the following beneficial effects:
the power consumption of the whole system can be reduced on the premise of not reducing the image quality.
Drawings
FIG. 1 is a flow chart of a frame rate control method;
FIG. 2 is a schematic diagram of adjusting H-Blank time to lower the display frame rate;
FIG. 3 is a schematic diagram of adjusting V-Blank time to reduce the display frame rate;
FIG. 4 is a schematic diagram of adjusting the period of the oscillator clock of the driving IC to lower the display frame rate;
FIG. 5 is a schematic diagram of adjusting the ratio of display frames to non-display frames to reduce the display frame rate;
FIG. 6 is a diagram of a frame rate control apparatus;
fig. 7 is a schematic diagram of a display system.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
Fig. 1 is a flowchart of a frame rate control method according to the present invention. In a system for displaying at a predetermined frame rate, if the condition that the picture is not changed within a specified time is maintained, the driving IC adjusts itself to lower the frame rate, thereby reducing the power consumption of the whole system.
Step S101 indicates a normal display state in which the display system performs display at a predetermined frame rate. In fig. 1, although 60Hz is indicated, designated states of 50Hz, 30Hz, 120Hz, etc. corresponding to the system purpose are shown.
Step S102 represents a stage of moving to a state (low frame rate state 1) in which a lower frame rate is operated if the output frame does not change within the specified time period T1, that is, if there is no event of changing the image in the normal display state, and returning to the normal display state (60 Hz in the figure) again if an event of bringing about a change in the image occurs.
Here, T1 represents a "specified time period", and a method of measuring the "specified time period" may use a time measuring module such as a real-time clock, a watchdog timer, or may use the number of frames displayed inside the driver IC, that is, may use a frame counter.
N1, N2, N3, etc. in fig. 1 represent the number of frames. If the no-event condition in step S102 is satisfied, the process proceeds to step S103, and display is performed at a frame rate lower than that in step S101. In the same manner, the process is repeated through steps S104, S105, and the like, and finally the m-th state is entered, that is, step S106, and the display is performed at the lowest frame rate until the event causing the screen change is entered, that is, step S107.
The specific value of the lowest frame rate is to avoid the image quality degradation phenomenon, such as flicker or picture darkening, which is visible to the user.
FIG. 1 shows m using several stages in total, and variables such as T1, T2, · · ·, tm, N1, N2, · · ·, nm, etc., which determine whether each stage is changed within a certain period of time and then proceed to the next stage, can be arbitrarily determined by a user.
Among these, events that change the image, for example: the display driver IC receives image data input by the application processor, a DBV different from the DBV currently used by the display driver IC and input by the application processor, or data for changing the image quality and color and input by the application processor. In addition, an event such as a change in the operation mode of the entire system may be an event for changing the image.
Fig. 2 to 5 illustrate four specific methods for reducing the frame rate.
Fig. 2 shows a method of increasing the time of 1 line to change the frame rate. As shown in 201, 202, and 203, one cycle of the HSYNC is composed of an HBP section, a display section in which DE (valid data strobe) is activated, and an HFP section, and in order to increase the cycle of the HSYNC, the driver IC uses a method of increasing an H blank (horizontal blanking) section 204 in which HFP is connected to the HBP.
The determined HFP and/or HBP values are specified for each state in fig. 1, wherein at least one of the HFP and HBP values is gradually increased from state 1 to state m. When the state corresponding to fig. 1 is entered, the H blank interval is increased by using the HFP and/or HBP value corresponding to the state, so that the frame rate is lowered. In fig. 2, 205 shows an example of increasing the H blank interval while changing the state.
Fig. 3 shows a method of increasing the number of lines constituting 1 frame to change the frame rate. As shown in 301, 302, and 303, one period of VSYNC is composed of a VBP section, a V-ACTIVE section for actual display data processing, and a VFP section, and in order to increase the period of VSYNC, the drive IC uses a method of increasing a V blank section 304 in which VFP is connected to VBP.
Corresponding to the respective states in fig. 1, certain VFP and/or VBP values are specified, wherein at least one of the VFP and VBP values is gradually increased from state 1 to state m. When the state corresponding to fig. 1 is entered, the VFP and/or VBP value corresponding to the state is used to increase the V blank interval to decrease the frame rate. In fig. 3, 305 shows an example of increasing the V blank interval while changing state.
Fig. 4 shows a method of increasing the clock output period of a built-in oscillator used in a drive IC to lower the frame rate.
Corresponding to states 1 to m in fig. 1, the internal oscillator clock output period is denoted as p1, p2, p3,. And.. And pm, and the normal display state, the internal oscillator clock output period is denoted as p, p < p1< p2< p3<. And.. And. < pm. In the normal display state, the display device operates at a period p, operates at a period p1 when entering the state 1, operates at a period p2 when entering the state 2, and so on, and operates at a period pm when entering the state m, thereby reducing the frame rate. The period p is shown at 401 and the period p1 is shown at 402 in fig. 4.
In order to make the oscillator clock period slow, the drive IC needs to have a function of controlling the oscillator speed to utilize the function.
Fig. 5 shows a frame skipping function for stopping display in the middle of a frame in order to reduce the frame rate of image data to be transmitted to the panel. Wherein display represents a display frame and skip represents a skip frame. As shown in 501, in the normal state, all frames are normally displayed, but are converted into the state 1 under the corresponding condition, and the frame is divided into the display frame and the frame which is not displayed (i.e. frame skipping) according to a specific proportion to act.
As shown in 502-504, the ratio of display frame to skip frame is specified for each state in FIG. 1, and the function can be run according to the user's request. In the frame skipping, the black screen can be simply transmitted to the panel, or the operation of the panel can be directly stopped. In this way, the operation inside the driver IC can be reduced, and the number of panel driving times can be reduced, thereby reducing the power consumption of the entire system. It should be noted that the specific proportional values are exemplary and not limiting.
The four specific methods for reducing the frame rate shown in fig. 2 to 5 may be used in combination or individually.
Fig. 6 shows a configuration of a frame rate control apparatus 600, and the frame rate control apparatus 600 is applicable to a display driver IC including a built-in frame buffer.
The frame rate control device 600 comprises a frame rate reduction device 610 and a frame rate restoration device 620. The frame rate reduction device 610 is used for reducing the frame rate of the display driving IC when the image is not changed within the specified duration. And a frame rate restoring means 620 for immediately returning the display driving IC to the frame rate of the normal state when receiving the event of changing the image.
The frame rate down-conversion means 610 comprises a plurality of cascaded frame rate down-conversion sub-means 611, 612, 613, 614, and is capable of reducing the frame rate in a plurality of stages.
The frame rate reduction device 610 preferably further comprises one or more of the following sub-devices: the system comprises an HSYNC period adjusting sub-device, a VSYNC period adjusting sub-device, a clock period adjusting sub-device and a frame proportion adjusting sub-device, wherein the HSYNC period adjusting sub-device adjusts the period of the HSYNC by adjusting the lengths of HFP and HBP, so that the purpose of reducing the frame rate is achieved; the VSYNC period adjusting sub-device adjusts the period of VSYNC by adjusting the lengths of VFP and VBP, thereby achieving the purpose of reducing the frame rate; the clock period adjusting sub-device achieves the purpose of reducing the frame rate by adjusting the period of an oscillator clock used in the display driving IC; the frame ratio adjusting sub-device achieves the purpose of reducing the frame rate by adjusting the ratio of the display frame to the frame skipping. Specific methods for lowering the frame rate of each sub-device are shown in fig. 2-5.
Fig. 7 shows a display system. The display system includes an application processor 710, a display driver IC 720 having a built-in frame buffer, and a display panel 730. Application processor 710 provides events to display driver IC 720 that change images including, but not limited to: new image data, a DBV different from the DBV currently used by the display driver IC, data for changing the image quality and color, and operation mode change data. The display driver IC 720 supplies image data to the display panel 730 at a predetermined frame rate.
During display, when the application processor 710 does not supply image data to the display driver IC 720, the display driver IC 720 reads previous frame image data from the built-in frame buffer 721 to supply to the display panel 730. At this time, the frame rate control device 600 is activated, and the frame rate reduction device detects the data input by the application processor 710, and further adjusts the frame rate of transmitting the image data to the display panel 730. Specifically, when the image data input from the application processor 710 is not detected or an event such as a change in the luminance information or the image quality condition is not detected within a predetermined period of time, the frame rate is automatically lowered and display is performed at a frame rate lower than the predetermined frame rate. The frame rate control device 600 is configured as shown in fig. 6. In the process of displaying the image at the reduced frame rate, the frame rate recovery device of the frame rate control device 600 detects the data input from the application processor 710, and if the image data or event is received from the application processor 710, the frame rate control device 600 immediately recovers the predetermined frame rate corresponding to the normal display state and displays the image at the predetermined frame rate.
The present invention has been described in detail with reference to the specific embodiments, and the detailed description is only for assisting the understanding of the present invention by those skilled in the art, and is not to be construed as limiting the scope of the present invention. Various modifications, equivalent changes, etc., which can be made by those skilled in the art under the conception of the present invention, should be included in the protection scope of the present invention.

Claims (10)

1. A method for controlling a frame rate of a display driver IC having a built-in frame buffer, comprising:
when the image is not changed within the specified duration, the display drive IC automatically reduces the frame rate; and
when an event of changing an image is received, the display drive IC immediately returns to the frame rate of the normal state.
2. The method of claim 1, comprising a plurality of stages for reducing the frame rate, wherein the specified time duration for determining whether each stage enters the next stage is the same or different.
3. The method as claimed in claim 2, wherein the frame rate reduction ratio is the same or different after each stage enters the next stage.
4. The frame rate control method according to claim 1, wherein the specified time period is measured using a real time clock, a watchdog timer or a frame counter.
5. The frame rate control method according to claim 1, wherein the event of changing the image comprises:
the display driver IC receives image data input from the application processor, receives a DBV different from the DBV currently used for the operation of the display driver IC and input from the application processor, and receives data for changing the image quality and color and input from the application processor.
6. The frame rate control method according to claim 1, wherein the method for the display driver IC to lower the frame rate by itself comprises:
adjusting the lengths of HFP and HBP to adjust the period of HSYNC; and/or
The length of VFP and VBP is adjusted to adjust the period of VSYNC; and/or
Adjusting a period of an oscillator clock used in the display drive IC; and/or
The ratio of display frames to skipped frames is adjusted.
7. A display driver IC including a built-in frame buffer, comprising:
the frame rate reducing device is used for reducing the frame rate of the display drive IC when the event of changing the image does not exist in the specified duration; and
and a frame rate restoring means for immediately returning the display driving IC to the frame rate of the normal state when an event of changing the image is received.
8. The display driver IC with built-in frame buffer of claim 7, wherein the frame rate reduction means comprises a plurality of frame rate reduction sub-means connected in cascade for reducing the frame rate in a plurality of stages.
9. The display driver IC with built-in frame buffer of claim 7, wherein the frame rate reduction means comprises
The HSYNC cycle adjusting sub-device is used for adjusting the lengths of HFP and HBP so as to adjust the cycle of HSYNC; and/or
The VSYNC period adjusting sub-device is used for adjusting the lengths of the VFP and the VBP so as to adjust the period of VSYNC; and/or
A clock period adjusting sub-means for adjusting a period of an oscillator clock used in the display drive IC; and/or
And the frame proportion adjusting sub-device is used for adjusting the proportion of the display frame to the frame skipping.
10. A display system comprising an application processor, a display driver IC with a built-in frame buffer, and a display panel, wherein the display driver IC is the display driver IC as claimed in any one of claims 7 to 9, and the frame rate reduction means and the frame rate restoration means detect data inputted from the application processor and adjust a frame rate at which image data is transmitted to the display panel.
CN202210843449.9A 2022-07-18 2022-07-18 Display drive IC containing frame buffer, display system and frame rate control method Pending CN115273719A (en)

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CN202210843449.9A CN115273719A (en) 2022-07-18 2022-07-18 Display drive IC containing frame buffer, display system and frame rate control method

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CN202210843449.9A CN115273719A (en) 2022-07-18 2022-07-18 Display drive IC containing frame buffer, display system and frame rate control method

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