CN110416311B - Asymmetric channel dielectric ring field effect transistor - Google Patents

Asymmetric channel dielectric ring field effect transistor Download PDF

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Publication number
CN110416311B
CN110416311B CN201910634807.3A CN201910634807A CN110416311B CN 110416311 B CN110416311 B CN 110416311B CN 201910634807 A CN201910634807 A CN 201910634807A CN 110416311 B CN110416311 B CN 110416311B
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channel
drain
extension region
silicon
electrode
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CN110416311A (en
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唐雅欣
田明
王昌锋
廖端泉
曹永峰
孙亚宾
李小进
石艳玲
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Shanghai Huali Microelectronics Corp
East China Normal University
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Shanghai Huali Microelectronics Corp
East China Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Abstract

The invention discloses an asymmetric channel dielectric ring field effect transistor, which comprises a source electrode, a drain electrode, a source electrode expansion region, a drain electrode expansion region, a channel, a grid electrode, a substrate, an insulating isolation layer in the substrate and an insulating dielectric ring arranged at the periphery of a nanowire channel close to the drain electrode expansion region. The insulating dielectric ring structure has larger dielectric constant and forbidden bandwidth, so that the tunneling probability of a current carrier at a drain end is reduced, the leakage current of a grid-caused drain electrode is effectively reduced, and the on-state current is hardly influenced. And the structure is embedded in the gate oxide layer, the gate surrounding capacitance cannot be increased, and the dynamic characteristic of the structure cannot be influenced. Therefore, on the premise of keeping the dynamic performance of the gate-all-around device not damaged, the GIDL leakage of the device is reduced, the current switching ratio of the device is improved, and the performance of the integrated circuit is improved.

Description

Asymmetric channel dielectric ring field effect transistor
Technical Field
The invention belongs to digital logic and storage devices in a CMOS (complementary metal-oxide-semiconductor transistor) very large integrated circuit (VLSI), and particularly relates to an asymmetric channel dielectric ring field effect transistor which can effectively reduce gate-induced drain leakage current of a semiconductor device.
Background
According to moore's law, the performance of an integrated circuit with the same area chip every 18 months will double. Therefore, as the device size decreases, a gate-all-around field effect transistor (GAA MOSFET), with its excellent gate control capability, can effectively reduce short channel effects, but at the same time results in severe gate-to-drain leakage current. Gate Induced Drain Leakage (GIDL), in which the device is in the off condition, i.e. the voltage on the Gate is at a small bias voltage around 0V and the Drain is connected to the forward voltage drop, the overlap between the Gate and the Drain results in the conventional lateral band-to-band tunneling (traditional band-to-band tunneling), and on the other hand, the overlap of the channel and the source/Drain results in the longitudinal band-to-band tunneling (longitudinal band-to-band tunneling). As the size of the gate-all-around transistor is reduced to deep nanometer level, the gate-induced drain leakage current has increasingly serious influence on the static power consumption, reliability and other aspects of the gate-all-around MOS device. It also has a serious impact on the erase and write operations of Memory devices such as Electrically Erasable Programmable Read-Only Memory (EEPROM).
In a conventional structure of the gate-all-around transistor, a Nanowire Channel (Nanowire Channel), a Source (Source), a Drain (Drain), a Source Extension (Source Extension), and a Drain Extension (Drain Extension) are made of semiconductor materials such as silicon, germanium, silicon germanium, and the like, and doping of the Source Extension and the Drain Extension near one end of the Channel is in a gaussian distribution manner. And a dielectric layer side wall (Spacer) is adopted outside the source/drain extension region to electrically isolate the grid electrode, the source electrode and the drain electrode. Consistent with the working principle of the conventional MOSFET, for an N-type device, when a forward bias is given to a grid electrode, a channel reaches an inversion state, and the device starts to be conducted. The gate-all-around device has excellent gate control capability due to the structure that the channel is completely surrounded by the gate, so that the gate-all-around device has better sub-threshold characteristics and can effectively reduce short-channel effects. However, in the conventional gate-all-around transistor structure, the gate-induced drain leakage current becomes more significant under the condition that the device is turned off. When the gate voltage is at 0V and a small negative bias, the leakage current generated by the longitudinal band-to-band tunneling effect is an important component of the total off-state current. When the size of the gate-all-around transistor is reduced to a deep nanometer level, a parasitic diode exists between a channel and a drain due to the strong gate control capability of the gate-all-around transistor, once energy bands of the channel and the drain are overlapped, a carrier can jump between the energy bands to cause gate-induced drain leakage current, and the gate-induced drain leakage current in an off state seriously influences the static power consumption, the reliability and the like of the gate-all-around MOS device.
Disclosure of Invention
The invention aims to solve the problem that the gate-induced drain leakage current of the existing traditional ring gate transistor is serious, and provides a novel asymmetric channel medium ring field effect transistor for reducing the off-state current of a device and reducing the static power consumption.
The specific technical scheme for realizing the aim of the invention is as follows;
an asymmetric channel dielectric ring field effect transistor is characterized in that the transistor comprises a channel; a source extension region disposed at one end of the channel and a drain extension region disposed at the other end; the insulating medium ring is arranged at the outer sides of the channel and the drain electrode expansion region end; a source electrode arranged at one end of the source electrode expansion region; a drain electrode disposed at one end of the drain extension region; a gate oxide disposed outside the channel; a gate electrode disposed at a periphery of the gate oxide; the side walls are arranged at the outer sides of the source electrode expansion region and the drain electrode expansion region and are used for electrically isolating the grid electrode from the source electrode and the drain electrode respectively; the substrate insulating layer is arranged on the bottom surfaces of the source electrode, the drain electrode, the side wall and the grid electrode, and the substrate is arranged on the bottom surface of the substrate insulating layer; wherein:
the channel, the source electrode extension region and the drain electrode extension region are silicon nanowires, germanium-silicon nanowires, gallium arsenide nanowires, gallium nitride nanowires, indium phosphide nanowires or carbon nanotubes;
the gate oxide is formed by depositing and stacking one or more of silicon dioxide, hafnium oxide and silicon oxynitride on the outer side of the channel;
the source electrode is composed of one or a combination of a plurality of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride which are deposited at one end of the source electrode extension region;
the drain electrode is composed of one or a combination of a plurality of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride which are deposited at one end of the drain electrode extension region;
the grid is formed by depositing aluminum, copper, polycrystalline silicon or titanium nitride which is formed by wrapping the outer side of a grid oxide through photoetching and etching;
the side wall is formed by air, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass which is deposited on the outer sides of the source electrode extension region, the drain electrode extension region and the channel, between the grid electrode and the source electrode end face and between the grid electrode and the drain electrode end face;
the substrate insulating layer is composed of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass deposited on the bottom surfaces of the source electrode and the drain electrode;
the substrate is composed of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride or tantalum nitride deposited on the bottom surface of the insulating layer of the substrate.
The insulating dielectric ring is formed by silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass which is deposited on the outer side of the channel and at the end of the drain extension region.
The width of the insulating medium ring is smaller than the radius of the channel, the length extending along the axial direction of the channel is smaller than the length of the channel, and the length extending along the drain electrode expansion region is the length reaching the drain electrode expansion region; and the outer ring radius of the insulating dielectric ring is equal to the channel radius.
The carrier transition that generates the gate-induced drain leakage current has a edge effect, i.e. the transition ratio is significantly increased at the position of the nanowire near the surface. The invention deposits a layer of insulating medium ring on the periphery of one end of the channel close to one end of the drain electrode extension region, thereby blocking the probability of carrier transition to a certain extent, reducing the influence of parasitic diode behavior and effectively reducing the tunneling current between longitudinal bands. Meanwhile, the annular medium in the channel and the gate oxide layer are made of the same material, and the influence of gate-surrounding parasitic capacitance on the dynamic characteristics of the device cannot be increased. Therefore, on the premise of not influencing the dynamic characteristics of the device, the GIDL current is effectively reduced, the static power consumption is reduced, the on-off ratio of the device is improved, and the reliability of the device is enhanced.
Due to the reduction of the gate-induced drain leakage current, the off-state current of the gate-induced drain leakage current is reduced, the static power consumption is reduced, and a CMOS circuit consisting of the gate-all-around transistors has more excellent low-power consumption performance and reliability.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1;
FIG. 4 is a graph of transfer characteristics of a general symmetric gate-all-around transistor (GAA MOSFET) and the present invention;
FIG. 5 is a graph of the switching ratio of a general symmetric gate-all-around transistor (GAA MOSFET) and the present invention;
FIG. 6 is a schematic diagram of the carrier tunneling ratio of a generic symmetric gate-all-around transistor (GAA MOSFET) and the present invention where the channel is surrounded by a dielectric ring;
FIG. 7 is a schematic view of a manufacturing process of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and examples.
Referring to fig. 1-3, the invention includes a nanowire channel 1, a gate oxide 2, a source extension region 4, a drain extension region 5, a source 6, a drain 7, a gate 9, a sidewall 8, a substrate insulating layer 10 and a substrate 11, wherein a dielectric ring 3 made of an insulating medium extends to the axial direction of the channel 1 or the radial direction of the drain extension region 5 for a certain length and a certain thickness to the channel 1 at the periphery of the nanowire channel 1 near one end of the drain extension region 5, and the diameter of the outer circle of the dielectric ring 3 is equal to the diameter of the nanowire in the channel 1.
A novel asymmetric channel dielectric ring gate field effect transistor is characterized in that a source electrode expansion region 4 and a source electrode 6, a drain electrode expansion region 5 and a drain electrode 7 are arranged at one end of a channel 1, a dielectric ring 3 is arranged at one end, close to the drain electrode expansion region 5, of the channel 1, a gate electrode oxide 2 is arranged on the outer sides of the channel 1 and the dielectric ring 3, a gate electrode 9 is respectively arranged on the outer sides of the gate electrode oxide 2, a side wall 8 is used for controlling the grid electrode 9, the source electrode 6 and the drain electrode 7 to be electrically isolated, and a substrate 11 and a substrate insulating layer 10 are arranged on the bottom surface of the transistor.
The channel 1, the source extension region 4 and the drain extension region 5 are formed into a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire, a gallium nitride nanowire, an indium phosphide nanowire or a carbon nanotube; the source 6, the drain 7 and the substrate 11 are made of silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, indium phosphide or carbon; the gate oxide 2 is silicon dioxide, hafnium oxide, silicon oxynitride or a combination stack of the above materials which are deposited and wrapped on the outer side of the channel 1; the grid 9 is formed by depositing aluminum, copper, polysilicon or titanium nitride on the outer side of the grid oxide 2 after photoetching and etching; the side wall 8 is made of air, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, borophosphosilicate glass and the like; the substrate insulating layer 10 is made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, or the like; the channel dielectric ring 3 is formed by silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphosilicate glass, borophosphosilicate glass or the like which is deposited on the outer side of the channel 1.
In the asymmetric channel dielectric ring transistor structure, when the device is closed, the probability of carrier transition is blocked to a certain extent by the larger forbidden band width of the dielectric ring, the influence of parasitic diode behavior is reduced, and the tunneling current between longitudinal bands is effectively reduced. Meanwhile, the annular medium in the channel is positioned in the gate oxide layer, and the influence of the gate-surrounding parasitic capacitance on the dynamic characteristics of the device is not increased. Therefore, on the premise of not influencing the dynamic characteristics of the device, the GIDL current is effectively reduced, the static power consumption is reduced, the on-off ratio of the device is improved, and the reliability of the device is enhanced.
Referring to fig. 4, a non-local band to band model is added in the simulation process, when the gate voltage is near 0V, that is, the device is in an off state, the leakage current of the asymmetric channel dielectric ring structure of the present invention is 7.237 e-12A, compared with the leakage current of the conventional symmetric structure of 9.24 e-11A, the leakage current of the device can be reduced by one order of magnitude by applying the channel dielectric ring, and the change of the on-state current is very small. And referring to fig. 5, the switching ratio of the asymmetric dielectric ring device of the present invention is improved by about 2 times to 1.5e7 compared with the conventional gate-all-around device. Therefore, the novel asymmetric channel dielectric ring structure can effectively reduce the leakage current of a gate-all-around device, improve the switching ratio of the device and better reduce the static power consumption.
The invention can effectively reduce electric leakage, can show better electrical characteristics, and can be explained from a carrier tunneling probability density comparison diagram in figure 6. The asymmetric channel is close to the insulating medium ring structure of the drain electrode extension region, and is embedded in the position where the longitudinal tunneling probability is the largest in the transistor due to the larger dielectric constant and forbidden bandwidth, so that the tunneling potential barrier of the current carrier close to the surface of the channel at the edge of the channel is greatly increased, and the tunneling probability of the current carrier at the drain end is greatly reduced. Therefore, the behavior of a parasitic diode at the channel is effectively inhibited, and the tunneling leakage current between longitudinal bands is greatly reduced, so that the off-state current of the device is reduced.
Examples
Referring to fig. 7, the manufacturing process of this embodiment:
in the figure (a), a silicon nanowire channel 1 is prepared by an epitaxial process;
in the figure (b), photoetching is carried out on one end, close to the drain electrode extension region, of the nanowire channel 1 by adopting a multiple mask technology or an extreme ultraviolet exposure technology, and the nanowire channel 1 exposed by the photoresist is removed by adopting reactive ion etching;
in the figure (c), an atomic layer deposition technology is adopted to grow a silicon dioxide insulating medium ring 3, and photoetching and reactive ion etching are carried out;
in the figure (d), a grid oxide layer 2 stacked by silicon dioxide and hafnium oxide is grown by adopting an atomic layer deposition technology, and photoetching and reactive ion etching are carried out;
in the figure (e), the aluminum metal gate electrode 9 is formed by physical vapor deposition, multiple mask technology or extreme ultraviolet exposure technology photoetching and reactive ion etching technology;
in the figure (f), an epitaxial process is adopted to prepare a silicon nanowire source extension region 4 and a silicon nanowire drain extension region 5;
in figure (g), the silicon dioxide sidewall 8 is deposited using high plasma chemical vapor deposition;
in the figure (h), a silicon material source electrode 6 and a silicon material drain electrode 7 are prepared by an epitaxial process;
in (i), silicon dioxide is prepared by a wet process, the insulating substrate layer 10 is formed, and rapid thermal annealing is performed.
In (j), the silicon substrate 11 is prepared by an epitaxial process;
after the device is prepared, the grid electrode, the source electrode, the drain electrode and the substrate are led out through the tungsten plug, so that the function of an electrical switch can be realized; the four electrodes are leveled by using chemical mechanical polishing, and the devices of the invention are connected together by metal connecting wires by adopting a post Damascus process of a CMOS (complementary metal oxide semiconductor) super-large scale circuit.

Claims (1)

1. An asymmetric channel dielectric ring field effect transistor, characterized in that the transistor comprises a channel (1);
a source extension region (4) disposed at one end of the channel and a drain extension region (5) disposed at the other end; the insulating medium ring (3) is arranged at the outer sides of the channel (1) and the drain electrode expansion region (5); a source electrode (6) arranged at one end of the source electrode expansion region (4); a drain (7) disposed at one end of the drain extension region (5); a gate oxide (2) disposed outside the channel (1); a gate (9) disposed at a periphery of the gate oxide (2); side walls (8) arranged outside the source extension region (4) and the drain extension region (5) and used for electrically isolating the grid (9) from the source electrode (6) and the drain electrode (7) respectively; a substrate insulating layer (10) arranged on the bottom surfaces of the source electrode (6), the drain electrode (7), the side wall (8) and the grid electrode (9) and a substrate (11) arranged on the bottom surface of the substrate insulating layer (10); wherein:
the channel (1), the source electrode extension region (4) and the drain electrode extension region (5) are silicon nanowires, germanium-silicon nanowires, gallium arsenide nanowires, gallium nitride nanowires, indium phosphide nanowires or carbon nanotubes;
the grid oxide (2) is formed by depositing and wrapping one or a plurality of combined stacks of silicon dioxide, hafnium oxide and silicon oxynitride outside the channel (1);
the source electrode (6) is formed by one or a combination of a plurality of kinds of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride which are deposited at one end of the source electrode extension region (4);
the drain electrode (7) is formed by one or a combination of a plurality of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride which are deposited at one end of the drain electrode extension region (5);
the grid (9) is formed by depositing aluminum, copper, polysilicon or titanium nitride which is formed by photoetching and etching and wraps the outer side of the grid oxide (2);
the side wall (8) is formed by air, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass which are deposited between the outer sides of the source electrode extension region (4), the drain electrode extension region (5) and the channel (1), the end surfaces of the grid electrode (9) and the source electrode (6) and the end surfaces of the grid electrode (9) and the drain electrode (7);
the substrate insulating layer (10) is formed by silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass which are deposited on the bottom surfaces of the source electrode (6) and the drain electrode (7);
the substrate (11) is composed of silicon, germanium, titanium silicide, nickel silicide, cobalt silicide, titanium nitride or tantalum nitride deposited on the bottom surface of the substrate insulating layer (10);
the insulating dielectric ring (3) is formed by silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass which is deposited at the outer side of the channel (1) and the end of the drain extension region (5);
the width of the insulating medium ring (3) is smaller than the radius of the channel, the length extending along the axial direction of the channel (1) is smaller than the length of the channel, and the length extending along the drain extension region (5) is 0 to the length of the drain extension region (5); and the radius of the outer ring of the insulating medium ring (3) is equal to that of the channel (1).
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