CN110415636B

CN110415636B - Shifting register, driving method thereof and grid driving circuit

Info

Publication number: CN110415636B
Application number: CN201910749658.5A
Authority: CN
Inventors: 王光兴; 董殿正; 张强; 王海旭; 林万; 许文鹏; 王雷阳; 黄海琴
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2019-08-14
Filing date: 2019-08-14
Publication date: 2022-08-16
Anticipated expiration: 2039-08-14
Also published as: CN110415636A

Abstract

A shift register, a driving method thereof and a gate driving circuit are applied to a touch display panel, wherein the shift register comprises: the node control subcircuit is used for providing a signal of the first clock signal end or the second power end for the first pull-up node and providing a signal of the signal input end for the second pull-up node under the control of the first power end, the second power end, the first clock signal end, the second clock signal end and the signal input end; the output sub-circuit is used for providing a signal of the first power supply end or the second clock signal end for the signal output end under the control of the first pull-up node and the second pull-up node; the touch latch sub-circuit is used for providing a signal of the second power supply end for the second pull-up node under the control of the signal input end, the second clock signal end, the third clock signal end and the second power supply end in the touch stage. The technical scheme provided by the application can ensure that the shift register normally outputs in the display stage, and the display effect of the touch display panel is improved.

Description

Shifting register, driving method thereof and grid driving circuit

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.

Background

In recent years, with the development of science and technology, a Gate Panel (GIP) technology in which a Gate driving circuit of a display Panel is directly formed on a substrate by a mask plating technology has appeared. The gate driving circuit based on the GIP technology is that a plurality of cascaded shift registers are arranged on a substrate, and the shift registers control the gating and closing of horizontal grid lines, so that the cost and the thickness of a display panel are greatly reduced.

The inventor researches and discovers that in the related art, the gate driving circuit based on the GIP technology needs to turn off the input in the touch control stage, so that the potential of the gate of the transistor for outputting cannot be kept for a long time, the shift register cannot normally output in the display stage, and the display effect of the display panel is further influenced.

Disclosure of Invention

The application provides a shift register, a driving method thereof and a grid driving circuit, which can keep the electric potential of a grid of a transistor for output in a touch control stage, further ensure that the shift register can normally output in a display stage, and improve the display effect of a touch control display panel.

In a first aspect, the present application provides a shift register, which is applied to a touch display panel, where the touch display panel includes: the shift register comprises a display stage and a touch stage, wherein the shift register comprises: the touch control circuit comprises a node control sub-circuit, an output sub-circuit and a touch latch sub-circuit;

the node control subcircuit is respectively connected with the first power supply end, the second power supply end, the first clock signal end, the second clock signal end, the signal input end, the first pull-up node and the second pull-up node, and is used for providing the signal of the first clock signal end or the second power supply end for the first pull-up node and providing the signal of the signal input end for the second pull-up node under the control of the first power supply end, the second power supply end, the first clock signal end, the second clock signal end and the signal input end;

the output sub-circuit is respectively connected with the first pull-up node, the second pull-up node, the first power end, the second clock signal end and the signal output end, and is used for providing signals of the first power end or the second clock signal end for the signal output end under the control of the first pull-up node and the second pull-up node;

the touch latch sub-circuit is respectively connected with the signal input end, the second power end, the grounding end, the second clock signal end, the third clock signal end and the second pull-up node, and is used for providing a signal of the second power end for the second pull-up node under the control of the signal input end, the second clock signal end, the third clock signal end and the second power end in the touch control stage.

Optionally, the node control sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

a control electrode of the first transistor is connected with the first pull-up node, a first electrode of the first transistor is connected with a first power supply end, and a second electrode of the first transistor is connected with a first electrode of the fourth transistor;

the control electrode of the second transistor is connected with the second node, the first electrode of the second transistor is connected with the first node, and the second electrode of the second transistor is connected with the first pull-up node;

a control electrode of the third transistor is connected with the first node, a first electrode of the third transistor is connected with the first pull-up node, and a second electrode of the third transistor is connected with the second power supply end;

a control electrode of the fourth transistor is connected with the second clock signal end, and a second electrode of the fourth transistor is connected with the second node;

a control electrode of the fifth transistor is connected with the first clock signal end, a first electrode of the fifth transistor is connected with the second node, and a second electrode of the fifth transistor is connected with the signal input end;

a control electrode of the sixth transistor is connected with the second power supply terminal, a first electrode of the sixth transistor is connected with the second node, and a second electrode of the sixth transistor is connected with the second pull-up node.

Optionally, the output sub-circuit comprises: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

a control electrode of the seventh transistor is connected with the first pull-up node, a first electrode of the seventh transistor is connected with the first power supply end, and a second electrode of the seventh transistor is connected with the signal output end;

a control electrode of the eighth transistor is connected with the second pull-up node, a first electrode of the eighth transistor is connected with the signal output end, and a second electrode of the eighth transistor is connected with the second clock signal end;

the first pull-up node of the first end of the first capacitor is connected, and the second end of the first capacitor is connected with the first power supply end;

the first end of the second capacitor is connected with the second pull-up node, and the second end of the second capacitor is connected with the signal output end.

Optionally, the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a third capacitor;

a control electrode of the ninth transistor is connected with the signal input end, a first electrode of the ninth transistor is connected with the second power supply end or the signal input end, and a second electrode of the ninth transistor is connected with the third node;

a control electrode of the tenth transistor is connected with the third node, a first electrode of the tenth transistor is connected with the second power supply end, and a second electrode of the tenth transistor is connected with the second pull-up node;

a control electrode of the eleventh transistor is connected with the second clock signal end, a first electrode of the eleventh transistor is connected with the third clock signal end, and a second electrode of the eleventh transistor is connected with the third node;

the first end of the third capacitor is connected with the third node, and the second end of the third capacitor is connected with the grounding end.

Optionally, the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor;

a control electrode of the tenth transistor is connected with the fourth node, a first electrode of the tenth transistor is connected with the second power supply end, and a second electrode of the tenth transistor is connected with the second pull-up node;

a control electrode of the eleventh transistor is connected with the second clock signal end, a first electrode of the eleventh transistor is connected with the third clock signal end, and a second electrode of the eleventh transistor is connected with the fourth node;

a control electrode of the twelfth transistor is connected with the third clock signal end, a first electrode of the twelfth transistor is connected with the third node, and a second electrode of the twelfth transistor is connected with the fourth node;

Optionally, the node control sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the output sub-circuit includes: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a third capacitor;

a control electrode of the second transistor is connected with the second node, a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with the first pull-up node;

a control electrode of the sixth transistor is connected with the second power supply end, a first electrode of the sixth transistor is connected with the second node, and a second electrode of the sixth transistor is connected with the second pull-up node;

the first end of the second capacitor is connected with the second pull-up node, and the second end of the second capacitor is connected with the signal output end;

Optionally, the node control sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the output sub-circuit includes: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor;

Optionally, in the touch stage, the third clock signal terminal provides an active level, and in the display stage, the third clock signal terminal provides an inactive level.

In a second aspect, the present application also provides a gate driving circuit, including: a plurality of cascaded shift registers;

and the signal output end of the Nth-stage shift register is connected with the signal input end of the (N + 1) th-stage shift register.

In a third aspect, the present application further provides a driving method of a shift register, applied to the shift register,

in a display phase, the method comprises:

under the control of a first power supply end, a second power supply end, a first clock signal end, a second clock signal end and a signal input end, the node control sub-circuit provides a signal of the first clock signal end or the second power supply end for the first pull-up node and provides a signal of the signal input end for the second pull-up node;

under the control of the first pull-up node and the second pull-up node, the output sub-circuit provides a signal of the first power supply end or the second clock signal end to the signal output end;

in a touch stage, the method comprises the following steps:

under the control of the signal input end, the second clock signal end, the third clock signal end and the second power end, the touch latch sub-circuit provides a signal of the second power end to the second pull-up node.

The application provides a shift register, a driving method thereof and a grid driving circuit, which are applied to a touch display panel, wherein the touch display panel comprises: the display stage and the touch stage, wherein, shift register includes: the touch control circuit comprises a node control sub-circuit, an output sub-circuit and a touch latch sub-circuit; the node control subcircuit is respectively connected with the first power supply end, the second power supply end, the first clock signal end, the second clock signal end, the signal input end, the first pull-up node and the second pull-up node, and is used for providing the signal of the first clock signal end or the second power supply end for the first pull-up node and providing the signal of the signal input end for the second pull-up node under the control of the first power supply end, the second power supply end, the first clock signal end, the second clock signal end and the signal input end; the output sub-circuit is respectively connected with the first pull-up node, the second pull-up node, the first power end, the second clock signal end and the signal output end and is used for providing signals of the first power end or the second clock signal end for the signal output end under the control of the first pull-up node and the second pull-up node; and the touch latch sub-circuit is respectively connected with the signal input end, the second power end, the grounding end, the second clock signal end, the third clock signal end and the second pull-up node, and is used for providing the signal of the second power end for the second pull-up node under the control of the signal input end, the second clock signal end, the third clock signal end and the second power end in the touch control stage. According to the embodiment of the application, the touch latch sub-circuit is arranged, so that the voltage stability of the grid electrode of the transistor for outputting can be ensured in the touch stage, the shift register can normally output in the display stage, and the display effect of the display panel is improved.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present application;

fig. 2 is an equivalent circuit diagram of a node control sub-circuit provided in an embodiment of the present application;

FIG. 3 is an equivalent circuit diagram of an output sub-circuit provided in an embodiment of the present application;

fig. 4A is a first equivalent circuit diagram of a touch latch sub-circuit according to an embodiment of the disclosure;

fig. 4B is an equivalent circuit diagram of a touch latch sub-circuit according to an embodiment of the present disclosure;

fig. 4C is a third equivalent circuit diagram of the touch latch sub-circuit according to the embodiment of the present disclosure;

fig. 4D is an equivalent circuit diagram of a touch latch sub-circuit according to an embodiment of the present disclosure;

fig. 5A is a first equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 5B is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 5C is a third equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 5D is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 6 is a timing diagram of an operation of a shift register according to an embodiment of the present application.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein may also be combined with any conventional features or elements to form unique inventive aspects as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, the second electrode may be a drain or a source, and the gate of the transistor is referred to as a control electrode.

In the related art, the embedded touch display panel has the advantages of being lighter, thinner and more attractive than the attached touch display panel, the touch display panel can simultaneously realize display and touch, the cost is greatly saved, and touch electrodes used for realizing touch and display in the touch display panel are multiplexed. In order to ensure normal display and touch control, the touch display panel needs to ensure that no output is generated in a shift register arranged on the touch display panel at the touch control stage, so as to prevent interference of other signals on the multiplexing electrode.

However, after all input signals are set to an invalid level in the touch stage, signals of the gates of the transistors for output have electric leakage, and cannot hold the electric potential for a long time, so that the on-voltage of the gates of the transistors for output is insufficient in the display stage of the shift register, and the shift register cannot normally output in the display stage, thereby affecting the display effect of the display panel.

Some embodiments of the present disclosure provide a shift register, which is applied to a touch display panel, where the touch display panel includes: fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present application, and as shown in fig. 1, the shift register provided in the embodiment of the present application includes: the touch control circuit comprises a node control sub-circuit, an output sub-circuit and a touch latch sub-circuit.

Specifically, the node control sub-circuit is respectively connected to the first power supply terminal VGH, the second power supply terminal VGL, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the signal INPUT terminal INPUT, the first pull-up node PU1 and the second pull-up node PU2, and is configured to provide a signal of the first clock signal terminal CLK1 or the second power supply terminal VGL to the first pull-up node PU1 and a signal of the signal INPUT terminal INPUT to the second pull-up node PU2 under the control of the first power supply terminal VGH, the second power supply terminal VGL, the first clock signal terminal CLK1, the second clock signal terminal CLK2 and the signal INPUT terminal INPUT; an OUTPUT sub-circuit, respectively connected to the first pull-up node PU1, the second pull-up node PU2, the first power source terminal VGH, the second clock signal terminal CLK2 and the signal OUTPUT terminal OUTPUT, for providing a signal of the first power source terminal VGH or the second clock signal terminal CLK2 to the signal OUTPUT terminal OUTPUT under the control of the first pull-up node PU1 and the second pull-up node PU 2; and a touch latch sub-circuit respectively connected to the signal INPUT terminal INPUT, the second power terminal VGL, the ground terminal GND, the second clock signal terminal CLK2, the third clock signal terminal CLK3 and the second pull-up node PU2, and configured to provide a signal of the second power terminal VGL to the second pull-up node PU2 under the control of the signal INPUT terminal INPUT, the second clock signal terminal CLK2, the third clock signal terminal CLK3 and the second power terminal VGL in a touch phase.

It should be noted that, the touch latch sub-circuit provided in the embodiment of the present application is configured to provide a signal at the second power source terminal to the second pull-up node in the touch phase, so as to ensure that the voltage of the transistor for outputting is stable, and thus the shift register can output the signal normally in the display phase. The node control sub-circuit and the output sub-circuit provided by the embodiment of the application are used for ensuring the output of the shift register in the display stage, so that the consistency of the brightness between rows is ensured on the premise that the touch time is not reduced.

Alternatively, the first power source terminal VGH and the second power source terminal VGL are opposite phase signals to each other. Specifically, the method comprises the following steps. The first power source terminal VGH may continuously supply a high level and may also continuously supply a low level, and the second power source terminal VGL continuously supplies a low level when the first power source terminal VGH continuously supplies the high level and the second power source terminal VGL continuously supplies the high level when the first power source terminal VGH continuously supplies the low level.

Alternatively, during the display period, the signal of the second clock terminal CLK2 is at an inactive level when the signal of the first clock terminal CLK1 is at an active level, and the signal of the first clock terminal CLK1 is at an inactive level when the signal of the second clock terminal CLK2 is at an active level.

Optionally, during the touch phase, the signals of the first clock signal terminal CLK1, the second clock signal terminal CLK2 and the signal INPUT terminal INPUT are at inactive levels.

The shift register provided by the embodiment of the application is applied to a touch display panel, and the touch display panel comprises: touch-control stage and display stage, shift register includes: the touch control circuit comprises a node control sub-circuit, an output sub-circuit and a touch latch sub-circuit; the node control subcircuit is respectively connected with the first power supply end, the second power supply end, the first clock signal end, the second clock signal end, the signal input end, the first pull-up node and the second pull-up node, and is used for providing the signal of the first clock signal end or the second power supply end for the first pull-up node and providing the signal of the signal input end for the second pull-up node under the control of the first power supply end, the second power supply end, the first clock signal end, the second clock signal end and the signal input end; the output sub-circuit is respectively connected with the first pull-up node, the second pull-up node, the first power end, the second clock signal end and the signal output end and is used for providing signals of the first power end or the second clock signal end for the signal output end under the control of the first pull-up node and the second pull-up node; and the touch latch sub-circuit is respectively connected with the signal input end, the second power end, the grounding end, the second clock signal end, the third clock signal end and the second pull-up node, and is used for providing the signal of the second power end for the second pull-up node under the control of the signal input end, the second clock signal end, the third clock signal end and the second power end in the touch control stage. According to the embodiment of the application, the voltage stability of the transistor for output can be ensured in the touch control stage by setting the touch control latch sub-circuit, so that the shift register can normally output in the display stage, and the display effect of the display panel is improved.

Optionally, the third clock signal terminal CLK3 provides an active level during the touch phase and the third clock signal terminal CLK3 provides an inactive level during the display phase.

In the application, the third clock signal terminal only provides an effective level in the touch control stage, so that the potential of the second pull-up node PU2 is not compensated in the display stage, and the potential of the second pull-up node PU2 is compensated in the touch control stage, so that the normal display of the touch control display panel is ensured.

Optionally, fig. 2 is an equivalent circuit diagram of the node control sub-circuit provided in the embodiment of the present application, and as shown in fig. 2, the node control sub-circuit provided in the embodiment of the present application includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

Specifically, a control electrode of the first transistor M1 is connected to the first pull-up node PU1, a first electrode of the first transistor M1 is connected to the first power supply terminal VGH, and a second electrode of the first transistor M1 is connected to a first electrode of the fourth transistor M4; a control electrode of the second transistor M2 is connected to the second node N2, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to the first pull-up node PU 1; a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the first pull-up node PU1, and a second electrode of the third transistor M3 is connected to the second power source terminal VGL; a control electrode of the fourth transistor M4 is connected to the second clock signal terminal CLK2, and a second electrode of the fourth transistor M4 is connected to the second node N2; a control electrode of the fifth transistor M5 is connected to the first clock signal terminal CLK1, a first electrode of the fifth transistor M5 is connected to the second node N2, and a second electrode of the fifth transistor M5 is connected to the signal INPUT terminal INPUT; a control electrode of the sixth transistor M6 is connected to the second power source terminal VGL, a first electrode of the sixth transistor M6 is connected to the second node N2, and a second electrode of the sixth transistor M6 is connected to the second pull-up node PU 2.

In the present embodiment, an exemplary structure of the node control sub-circuit is specifically shown in fig. 2. It is easily understood by those skilled in the art that the implementation of the node control sub-circuit is not limited thereto as long as the function thereof can be achieved.

Optionally, fig. 3 is an equivalent circuit diagram of an output sub-circuit provided in the embodiment of the present application, and as shown in fig. 3, the output sub-circuit provided in the embodiment of the present application includes: a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

Specifically, a control electrode of the seventh transistor M7 is connected to the first pull-up node PU1, a first electrode of the seventh transistor M7 is connected to the first power source terminal VGH, and a second electrode of the seventh transistor M7 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the eighth transistor M8 is connected to the second pull-up node PU2, a first electrode of the eighth transistor M8 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eighth transistor M8 is connected to the second clock signal terminal CLK 2; a first pull-up node PU1 of a first terminal of the first capacitor C1 is connected, and a second terminal of the first capacitor C1 is connected to a first power supply terminal VGH; a first terminal of the second capacitor C2 is connected to the second pull-up node PU2, and a second terminal of the second capacitor C2 is connected to the signal OUTPUT terminal OUTPUT.

In the present embodiment, an exemplary structure of the output sub-circuit is specifically shown in fig. 3. Those skilled in the art will readily appreciate that the implementation of the output sub-circuit is not limited thereto as long as its function can be achieved.

Optionally, as an implementation manner, fig. 4A is a first equivalent circuit diagram of the touch latch sub-circuit provided in the embodiment of the present application, and fig. 4B is a second equivalent circuit diagram of the touch latch sub-circuit provided in the embodiment of the present application, as shown in fig. 4A to 4B, the touch latch sub-circuit provided in the embodiment of the present application includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a third capacitor C3.

Specifically, a control electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT, a first electrode of the ninth transistor M9 is connected to the second power source terminal VGL or the signal INPUT terminal INPUT, and a second electrode of the ninth transistor M9 is connected to the third node N3; a control electrode of the tenth transistor M10 is connected to the third node N3, a first electrode of the tenth transistor M10 is connected to the second power source terminal VGL, and a second electrode of the tenth transistor M10 is connected to the second pull-up node PU 2; a control electrode of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, a first electrode of the eleventh transistor M11 is connected to the third clock signal terminal CLK3, and a second electrode of the eleventh transistor M11 is connected to the third node N3; a first terminal of the third capacitor C3 is connected to the third node N3, and a second terminal of the third capacitor C3 is connected to the ground GND.

In fig. 4A, the first pole of the ninth transistor M9 is connected to the second power source terminal VGL, and in fig. 4B, the first pole of the ninth transistor M9 is connected to the signal INPUT terminal INPUT.

It should be noted that, in this embodiment, the ninth transistor M9 and the tenth transistor M10 are turned on when the signal INPUT terminal INPUT INPUTs an active level, so as to ensure that the signal of the second power source terminal VGL can enter the control electrode of the eighth transistor M8, compensate for the leakage of the eighth transistor M8 in the touch phase, and the third capacitor C3 is used as a holding capacitor of the tenth transistor M10, so as to stabilize the on state of the tenth transistor M10.

Optionally, as another embodiment, fig. 4C is a third equivalent circuit diagram of the touch latch sub-circuit provided in the embodiment of the present application, and fig. 4D is a fourth equivalent circuit diagram of the touch latch sub-circuit provided in the embodiment of the present application, and as shown in fig. 4C to 4D, the touch latch sub-circuit provided in the embodiment of the present application includes: the touch latch sub-circuit includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a third capacitor C3.

Specifically, a control electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT, a first electrode of the ninth transistor M9 is connected to the second power source terminal VGL or the signal INPUT terminal INPUT, and a second electrode of the ninth transistor M9 is connected to the third node N3; a control electrode of the tenth transistor M10 is connected to the fourth node N4, a first electrode of the tenth transistor M10 is connected to the second power source terminal VGL, and a second electrode of the tenth transistor M10 is connected to the second pull-up node PU 2; a control electrode of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, a first electrode of the eleventh transistor M11 is connected to the third clock signal terminal CLK3, and a second electrode of the eleventh transistor M11 is connected to the fourth node N4; a control electrode of the twelfth transistor M12 is connected to the third clock signal terminal CLK3, a first electrode of the twelfth transistor M12 is connected to the third node N3, and a second electrode of the twelfth transistor M12 is connected to the fourth node N4; a first terminal of the third capacitor C3 is connected to the third node N3, and a second terminal of the third capacitor C3 is connected to the ground GND.

In fig. 4C, the first electrode of the ninth transistor M9 is connected to the second power source terminal VGL, and in fig. 4D, the first electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT.

It should be noted that, in this embodiment, the ninth transistor M9 is turned on when the signal INPUT terminal INPUT INPUTs an active level, so as to ensure that the signal of the second power supply terminal VGL can enter the third capacitor C3, the third capacitor C3 serves as a holding capacitor of the tenth transistor M10, so as to stabilize the on state of the tenth transistor M10, the twelfth transistor M12 can effectively control the influence of the third capacitor C3 on the tenth transistor M10, so as to prevent the influence on the second pull-up node PU2 after the touch phase, and further ensure the normal display of the touch display panel.

In the present embodiment, an exemplary structure of the touch latch sub-circuit is specifically illustrated in fig. 4A to 4D. Those skilled in the art will readily understand that the implementation of the touch latch sub-circuit is not limited thereto as long as the function thereof can be realized.

Optionally, fig. 5A is a first equivalent circuit diagram of a shift register provided in the embodiment of the present application, and fig. 5B is a second equivalent circuit diagram of a shift register provided in the embodiment of the present application, and as shown in fig. 5A to 5B, the node control sub-circuit provided in the embodiment of the present application includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; the output sub-circuit includes: a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2; the touch latch sub-circuit includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a third capacitor C3.

Specifically, a control electrode of the first transistor M1 is connected to the first pull-up node PU1, a first electrode of the first transistor M1 is connected to the first power supply terminal VGH, and a second electrode of the first transistor M1 is connected to a first electrode of the fourth transistor M4; a control electrode of the second transistor M2 is connected to the second node N2, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to the first pull-up node PU 1; a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the first pull-up node PU1, and a second electrode of the third transistor M3 is connected to the second power source terminal VGL; a control electrode of the fourth transistor M4 is connected to the second clock signal terminal CLK2, and a second electrode of the fourth transistor M4 is connected to the second node N2; a control electrode of the fifth transistor M5 is connected to the first clock signal terminal CLK1, a first electrode of the fifth transistor M5 is connected to the second node N2, and a second electrode of the fifth transistor M5 is connected to the signal INPUT terminal INPUT; a control electrode of the sixth transistor M6 is connected to the second power source terminal VGL, a first electrode of the sixth transistor M6 is connected to the second node N2, and a second electrode of the sixth transistor M6 is connected to the second pull-up node PU 2; a control electrode of the seventh transistor M7 is connected to the first pull-up node PU1, a first electrode of the seventh transistor M7 is connected to the first power source terminal VGH, and a second electrode of the seventh transistor M7 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the eighth transistor M8 is connected to the second pull-up node PU2, a first electrode of the eighth transistor M8 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eighth transistor M8 is connected to the second clock signal terminal CLK 2; a first pull-up node PU1 of a first terminal of the first capacitor C1 is connected, and a second terminal of the first capacitor C1 is connected to a first power supply terminal VGH; a first end of the second capacitor C2 is connected to the second pull-up node PU2, and a second end of the second capacitor C2 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT, a first electrode of the ninth transistor M9 is connected to the second power source terminal VGL or the signal INPUT terminal INPUT, and a second electrode of the ninth transistor M9 is connected to the third node N3; a control electrode of the tenth transistor M10 is connected to the third node N3, a first electrode of the tenth transistor M10 is connected to the second power source terminal VGL, and a second electrode of the tenth transistor M10 is connected to the second pull-up node PU 2; a control electrode of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, a first electrode of the eleventh transistor M11 is connected to the third clock signal terminal CLK3, and a second electrode of the eleventh transistor M11 is connected to the third node N3; a first terminal of the third capacitor C3 is connected to the third node N3, and a second terminal of the third capacitor C3 is connected to the ground GND.

In fig. 5A, the first pole of the ninth transistor M9 is connected to the second power source terminal VGL, and in fig. 5B, the first pole of the ninth transistor M9 is connected to the signal INPUT terminal INPUT.

Optionally, fig. 5C is a third equivalent circuit diagram of the shift register provided in the embodiment of the present application, and fig. 5D is a fourth equivalent circuit diagram of the shift register provided in the embodiment of the present application, and as shown in fig. 5C to 5D, the node control sub-circuit provided in the embodiment of the present application includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; the output sub-circuit includes: a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2; the touch latch sub-circuit includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a third capacitor C3.

Specifically, a control electrode of the first transistor M1 is connected to the first pull-up node PU1, a first electrode of the first transistor M1 is connected to the first power supply terminal VGH, and a second electrode of the first transistor M1 is connected to a first electrode of the fourth transistor M4; a control electrode of the second transistor M2 is connected to the second node N2, a first electrode of the second transistor M2 is connected to the first node N1, and a second electrode of the second transistor M2 is connected to the first pull-up node PU 1; a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to the first pull-up node PU1, and a second electrode of the third transistor M3 is connected to the second power source terminal VGL; a control electrode of the fourth transistor M4 is connected to the second clock signal terminal CLK2, and a second electrode of the fourth transistor M4 is connected to the second node N2; a control electrode of the fifth transistor M5 is connected to the first clock signal terminal CLK1, a first electrode of the fifth transistor M5 is connected to the second node N2, and a second electrode of the fifth transistor M5 is connected to the signal INPUT terminal INPUT; a control electrode of the sixth transistor M6 is connected to the second power source terminal VGL, a first electrode of the sixth transistor M6 is connected to the second node N2, and a second electrode of the sixth transistor M6 is connected to the second pull-up node PU 2; a control electrode of the seventh transistor M7 is connected to the first pull-up node PU1, a first electrode of the seventh transistor M7 is connected to the first power source terminal VGH, and a second electrode of the seventh transistor M7 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the eighth transistor M8 is connected to the second pull-up node PU2, a first electrode of the eighth transistor M8 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eighth transistor M8 is connected to the second clock signal terminal CLK 2; a first pull-up node PU1 of a first terminal of the first capacitor C1 is connected, and a second terminal of the first capacitor C1 is connected to a first power supply terminal VGH; a first end of the second capacitor C2 is connected to the second pull-up node PU2, and a second end of the second capacitor C2 is connected to the signal OUTPUT terminal OUTPUT; a control electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT, a first electrode of the ninth transistor M9 is connected to the second power source terminal VGL or the signal INPUT terminal INPUT, and a second electrode of the ninth transistor M9 is connected to the third node N3; a control electrode of the tenth transistor M10 is connected to the fourth node N4, a first electrode of the tenth transistor M10 is connected to the second power source terminal VGL, and a second electrode of the tenth transistor M10 is connected to the second pull-up node PU 2; a control electrode of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, a first electrode of the eleventh transistor M11 is connected to the third clock signal terminal CLK3, and a second electrode of the eleventh transistor M11 is connected to the fourth node N4; a control electrode of the twelfth transistor M12 is connected to the third clock signal terminal CLK3, a first electrode of the twelfth transistor M12 is connected to the third node N3, and a second electrode of the twelfth transistor M12 is connected to the fourth node N4; a first terminal of the third capacitor C3 is connected to the third node N3, and a second terminal of the third capacitor C3 is connected to the ground GND.

In addition, fig. 5C illustrates an example in which the first electrode of the ninth transistor M9 is connected to the second power source terminal VGL, and fig. 5D illustrates an example in which the first electrode of the ninth transistor M9 is connected to the signal INPUT terminal INPUT.

In the embodiment, the transistors M1 to M12 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, the process can be reduced, and the yield of the product can be improved. The thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as a switching function can be achieved.

It should be noted that, when all the transistors are N-type thin film transistors, the first power supply terminal VGH continuously provides a low level signal, and the second power supply terminal VGL continuously provides a high level signal, and when all the transistors are P-type thin film transistors, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal.

The technical solution of the embodiment of the present application is further described below by the working process of the shift register.

Taking the transistors M1 to M11 in the shift register provided by the embodiment of the present application as an example, and fig. 6 is an operation timing diagram of the shift register provided by the embodiment of the present application, as shown in fig. 5A and fig. 6, the shift register provided by the embodiment of the present application includes 11 transistor units (M1 to M11), 3 capacitors (C1, C2, and C3), 4 signal INPUT terminals (INPUT, CLK1, CLK2, and CLK3), 1 signal OUTPUT terminal (OUTPUT), and 3 power supply terminals (VGH, VGL, and GND).

Specifically, the first power source terminal VGH continuously provides a high level signal; the second power source terminal VGL continuously supplies a low level signal. The touch display panel includes: a touch stage T and a display stage S, wherein the display stage S comprises: the first stage S1, the second stage S2, and the third stage S3 assume that the touch stage T occurs between the first stage S1 and the second stage S2.

Specifically, the method comprises the following steps:

a first stage S1, namely an INPUT stage, in which signals of the signal INPUT terminal INPUT and the first clock signal terminal CLK1 are at a low level, signals of the second clock signal terminal CLK2 and the third clock signal terminal CLK2 are at a high level, and since the signal of the signal INPUT terminal INPUT is at a low level, the ninth transistor M9 is turned on, a potential of the third node N3 is pulled low, the tenth transistor M10 is turned on, a potential of the second pull-up node PU2 is pulled low, the eighth transistor M8 is turned on, and the second capacitor C2 is charged; since the signal of the first clock signal terminal CLK1 is at a low level, the third transistor M3 and the fifth transistor M5 are turned on to pull down the potentials of the first node N1 and the second node N2, the second transistor M2 is turned on, the potential of the first pull-up node PU1 is pulled down, the seventh transistor M7 is turned on, and since the signals of the first power source terminal VGH and the second clock signal terminal CLK2 are at a high level, the signal OUTPUT terminal OUTPUT OUTPUTs a high level at this stage.

In the touch sensing stage T, the signals of the signal INPUT terminal INPUT, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are at high level, the signal of the third clock signal terminal CLK3 is at low level, the third transistor M3, the fifth transistor M5 and the ninth transistor M9 are turned off, under the action of the third capacitor C3, the third node N3 is kept at a low level, the tenth transistor M10 is turned on, the potential of the second pull-up node PU2 is continuously pulled down, the eighth transistor M8 is turned on, since the signal at the second clock signal terminal CLK2 is at the high level, the potential at the signal OUTPUT terminal OUTPUT is pulled high, since the signal of the second power source terminal VGL is low, the sixth transistor M6 is turned on, the potential of the second node N2 is pulled low, the second transistor M2 is turned on, since the signal at the first clock signal terminal CLK1 is at a high level, the potential of the first pull-up node PU1 is pulled high, the seventh transistor M7 is turned off, and the OUTPUT signal at the signal OUTPUT terminal OUTPUT is at a high level at this stage.

In the second stage S2, the signal at the second clock signal terminal CLK2 is low, the signals at the signal INPUT terminal INPUT, the first clock signal terminal CLK1 and the third clock signal terminal CLK3 are high, since the signal of the second clock signal terminal CLK2 is low, the fourth transistor M4 and the eleventh transistor M11 are turned on, since the eleventh transistor M11 is turned on, the potential of the third node N3 is pulled high, the tenth transistor M10 is turned off, the second pull-up node PU2 is maintained at a low level by the second capacitor C2, the eighth transistor M8 is turned on, the low level signal of the second clock signal terminal CLK2 is supplied to the signal OUTPUT terminal OUTPUT, since the signal of the second power source terminal VGL is at a low level, the sixth transistor M6 is turned on, the potential of the second node N2 is pulled low, the second transistor M2 is turned on, the first pull-up node PU1 is continuously pulled high, and the seventh transistor M7 is turned off, at which stage, the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a low level.

In the third stage S3, the signal at the first clock signal terminal CLK1 is at a low level, the signals at the signal INPUT terminal INPUT, the second clock signal terminal CLK2, and the third clock signal terminal CLK3 are at a high level, and since the signal at the first clock signal terminal CLK1 is at a low level, the third transistor M3 and the fifth transistor M5 are turned on, the potential of the first pull-up node PU1 is pulled low, the seventh transistor M7 is turned on, the potential of the second node N2 is pulled high, and since the sixth transistor M6 is turned on, the second pull-up node PU2 is pulled high by the signal at the second node N2, and the eighth transistor M8 is turned off, and the signal at the first power supply terminal VGH is OUTPUT to the signal OUTPUT terminal OUTPUT.

By arranging the touch latch sub-circuit, the embodiment of the application has the advantages that the output of the shift register in the display stage is not influenced, the shift register is not output in the touch stage, and the low potential of the second pull-up node PU2 is kept, so that the shift register can normally output in the display stage, and the display effect of the display panel is improved.

It should be noted that the operation timing of the shift register provided in fig. 5B is the same as the operation timing of the shift register provided in fig. 5A. The shift register provided in fig. 5B is different from the shift register provided in fig. 5A in the connection manner of the first pole of the ninth transistor M9. For the shift register provided in fig. 5B, in the first stage S1, the signals of the first clock signal terminal CLK1 and the signal INPUT terminal INPUT are at low level, and the ninth transistor M9 is turned on, which is the same as the shift register provided in fig. 5A, and it is also ensured that the signal of the third node N3 is pulled low, and further ensured that the potential of the second pull-up node PU2 is continuously pulled low under the action of the third capacitor C3 in the touch stage.

Taking the transistors M1 to M12 in the shift register provided by the embodiment of the present application as P-type thin film transistors as an example, as shown in fig. 5C and fig. 6, the shift register provided by the embodiment of the present application includes 12 transistor units (M1 to M12), 3 capacitors (C1, C2, and C3), 4 signal INPUT terminals (INPUT, CLK1, CLK2, and CLK3), 1 signal OUTPUT terminal (OUTPUT), and 3 power supply terminals (VGH, VGL, and GND).

Specifically, the method comprises the following steps:

the first stage S1, i.e., the INPUT stage, the signals of the signal INPUT terminal INPUT and the first clock signal terminal CLK1 are low, the signals of the second clock signal terminal CLK2 and the third clock signal terminal CLK2 are high, since the signal at the signal INPUT terminal INPUT is at a low level, the ninth transistor M9 is turned on, the potential of the third node N3 is pulled low, since the signal of the first clock signal terminal CLK1 is at a low level, the third transistor M3 and the fifth transistor M5 are turned on, the potential of the second node N2 is pulled low, since the sixth transistor M6 is turned on, the signal at the second pull-up node PU2 is pulled low, the eighth transistor M8 is turned on, the second capacitor C2 is charged, the second transistor M2 is turned on, the signal at the first pull-up node PU1 is pulled low, the seventh transistor M7 is turned on, since the signals of the first power source terminal VGH and the second clock signal terminal CLK2 are at a high level, the signal OUTPUT terminal OUTPUT OUTPUTs a high level at this stage.

In the touch sensing stage T, the signal of the third clock signal terminal CLK3 is at a low level, the signal of the signal INPUT terminal INPUT, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 is at a high level, the third transistor M3, the fifth transistor M5 and the ninth transistor M9 are turned off, the third node N3 is kept at a low level by the third capacitor C3, the twelfth transistor M12 is turned on because the signal of the third clock signal terminal CLK3 is at a low level, the potential of the fourth node N4 is pulled low, the tenth transistor M10 is turned on, the potential of the second pull-up node PU2 is continuously pulled low, the eighth transistor M8 is turned on because the signal of the second clock signal terminal CLK2 is at a high level, the potential of the signal OUTPUT terminal OUTPUT is pulled high, the potential of the second VGL is at a low level, the sixth transistor M6 is turned on because the signal of the second node N2 is pulled low level, the potential of the second clock signal terminal CLK2 is at a high level, and the signal terminal CLK1 is turned on, the potential of the first pull-up node PU1 is pulled high, the seventh transistor M7 is turned off, and the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a high level at this stage.

In a second stage S2, the signal of the second clock signal terminal CLK2 is at a low level, the signals of the signal INPUT terminal INPUT, the first clock signal terminal CLK1 and the third clock signal terminal CLK3 are at a high level, the fourth transistor M4 and the eleventh transistor M11 are turned on because the signal of the second clock signal terminal CLK2 is at a low level, the potential of the fourth node N4 is pulled high by the signal of the third clock signal terminal CLK3 because the eleventh transistor M11 is turned on, the tenth transistor M10 is turned off, the second pull-up node PU2 is kept at a low level by the second capacitor C2, the eighth transistor M8 is turned on, the low-level signal of the second clock signal terminal CLK2 is supplied to the signal OUTPUT terminal OUTPUT, the sixth transistor M6 is turned on because the signal of the second power supply terminal VGL is at a low level, the potential of the second node N2 is pulled low, the second transistor M2 is turned on, the first pull-up node 1 is continuously pulled high, the seventh transistor PU 7, at this stage, the OUTPUT signal of the signal OUTPUT terminal OUTPUT is at a low level.

In the third stage S3, the signal at the first clock signal terminal CLK1 is at a low level, the signals at the signal INPUT terminal INPUT, the second clock signal terminal CLK2 and the third clock signal terminal CLK3 are at a high level, the signal at the first clock signal terminal CLK1 is at a low level, the third transistor M3 and the fifth transistor M5 are turned on, the potential of the first pull-up node PU1 is pulled down, the seventh transistor M7 is turned on, the potential of the second node N2 is pulled up, the sixth transistor M6 is turned on, the second pull-up node PU2 is pulled up by the signal at the second node N2, the eighth transistor M8 is turned off, and the signal at the first power supply terminal VGH is OUTPUT to the signal OUTPUT terminal OUTPUT.

By arranging the touch latch sub-circuit, the embodiment of the application does not affect the output of the shift register in the display stage on the one hand, and on the other hand, can ensure that the shift register is not output in the touch stage, and keeps the low potential of the second pull-up node PU2, so that the shift register can normally output in the display stage, and the display effect of the display panel is improved.

It should be noted that the operation timing of the shift register provided in fig. 5D is the same as the operation timing adopted by the shift register provided in fig. 5C. The shift register provided in fig. 5D is different from the shift register provided in fig. 5C in the connection manner of the first pole of the ninth transistor M9. For the shift register provided in fig. 5D, in the first stage S1, the signals of the first clock signal terminal CLK1 and the signal INPUT terminal INPUT are at low level, and the ninth transistor M9 is turned on, so as to ensure that the signal of the third node N3 is pulled low, and further ensure that the potential of the second pull-up node PU2 is continuously pulled low under the action of the third capacitor C3 and the third clock signal terminal CLK3 in the touch stage.

Based on the same inventive concept, an embodiment of the present application further provides a gate driving circuit, including: a plurality of cascaded shift registers.

Specifically, the signal output end of the nth stage shift register is connected with the signal input end of the (N + 1) th stage shift register.

It should be noted that the signal input terminal of the first stage shift register is connected to the initial signal terminal.

The shift register is provided in the embodiments of the present application, and the implementation principle and the implementation effect are similar, which are not described herein again.

Based on the same inventive concept, the embodiment of the application also provides a driving method of the shift register, which is applied to the shift register.

In the display stage, the driving method provided by the embodiment of the application specifically includes the following steps:

step 100, under the control of the first power end, the second power end, the first clock signal end, the second clock signal end and the signal input end, the node control sub-circuit provides the signal of the first clock signal end or the second power end to the first pull-up node and provides the signal of the signal input end to the second pull-up node.

Step 200, under the control of the first pull-up node and the second pull-up node, the output sub-circuit provides the signal of the first power end or the second clock end to the signal output end.

In a touch stage, the driving method provided by the embodiment of the application includes: under the control of the signal input end, the second clock signal end, the third clock signal end and the second power end, the touch latch sub-circuit provides a signal of the second power end to the second pull-up node.

The shift register provided in the foregoing embodiments has similar implementation principles and implementation effects, and is not described herein again.

The drawings of the embodiments of the present application relate only to the structures related to the embodiments of the present application, and other structures may refer to general designs.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A shift register is applied to a touch display panel, and the touch display panel comprises: the shift register comprises a display stage and a touch stage, wherein the shift register comprises: the touch control circuit comprises a node control sub-circuit, an output sub-circuit and a touch latch sub-circuit;

2. The shift register of claim 1, wherein the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

3. The shift register of claim 1, wherein the output sub-circuit comprises: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

4. The shift register of claim 1, wherein the touch latch subcircuit comprises: a ninth transistor, a tenth transistor, an eleventh transistor, and a third capacitor;

5. The shift register of claim 1, wherein the touch latch subcircuit comprises: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor;

6. The shift register of claim 1, wherein the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the output sub-circuit includes: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a third capacitor;

7. The shift register of claim 1, wherein the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the output sub-circuit includes: a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the touch latch sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor;

8. The shift register of claim 1, wherein the third clock signal terminal provides an active level during a touch phase and provides an inactive level during a display phase.

9. A gate drive circuit, comprising: a plurality of cascaded shift registers according to any one of claims 1 to 8;

10. A method for driving a shift register, which is applied to the shift register according to any one of claims 1 to 8,

in a display phase, the method comprises:

in a touch stage, the method comprises the following steps: