CN110391201A - 具有间隔件的倒装芯片集成电路封装 - Google Patents

具有间隔件的倒装芯片集成电路封装 Download PDF

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Publication number
CN110391201A
CN110391201A CN201910303953.8A CN201910303953A CN110391201A CN 110391201 A CN110391201 A CN 110391201A CN 201910303953 A CN201910303953 A CN 201910303953A CN 110391201 A CN110391201 A CN 110391201A
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semiconductor substrate
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photoresist
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J·R·M·巴埃洛
R·J·L·格瓦拉
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请的实施例涉及一种用于倒装芯片封装式集成电路的装置及方法。在所描述实例中，一种设备(图4，400)包含半导体衬底(403)及形成于所述半导体衬底(403)的作用表面上的至少两个柱状凸块(405)，所述至少两个柱状凸块(405)延伸远离所述作用表面且具有与所述半导体衬底间隔开的端，其中在所述至少两个柱状凸块的所述端处具有焊接材料(413)。至少一个间隔件(411)形成于所述半导体衬底的所述作用表面上，所述至少一个间隔件从所述半导体衬底的所述作用表面延伸预定距离。封装衬底(409)具有在第一表面上的裸片安装区，所述裸片安装区包含接纳所述至少两个柱状凸块的所述端且接纳所述至少一个间隔件的端的若干部分。模制化合物(433)覆盖所述半导体衬底、所述至少两个柱状凸块、所述至少一个间隔件及所述半导体衬底的至少一部分。

Description

具有间隔件的倒装芯片集成电路封装
技术领域
本发明一般来说涉及具有柱状凸块以用于倒装芯片连接到衬底的封装式集成电路，且更特定来说涉及一种用于倒装芯片封装式集成电路的装置及方法。
背景技术
在装配集成电路中，使用半导体处理在半导体晶片上形成装置。一旦处理到完成阶段，便可将个别集成电路装置彼此分开或“单个化”。所述个别装置可被称为“裸片”或被称为“集成电路裸片”。在完成在裸片上形成电路的半导体过程期间，形成端子以用于给裸片内的电路提供信号及电力电连接。举例来说，所述裸片可具有在装置的作用表面或“面”上的铝接合垫或铜接合垫，所述铝接合垫或铜接合垫为端子。提供封装式集成电路以用于表面安装到系统板或模块的最近封装类型包含安置于模制封装内的引线框组合件上的“倒装芯片”。在倒装芯片集成电路封装中，所述集成电路具有形成于作用表面上的接合垫上且延伸远离裸片的作用表面的支柱或柱。所述柱可具有铜。在柱的端上形成焊料以形成柱状凸块。所述柱为导电的且所述柱状凸块形成到接合垫的电连接。
接着通过单个化将个别集成电路从半导体晶片移除以形成集成电路裸片。在装配中，所述集成电路裸片经定位使得集成电路装置的作用表面在裸片安装区中面对封装衬底(举例来说，引线框)的表面。封装衬底中的导体可具有与柱状凸块对应的导电焊盘以用于进行与裸片的电及物理连接。使用热回流过程将柱状凸块的焊料接合到封装衬底。在热回流过程中，施加足以使焊料熔融的热。焊料回流到衬底(举例来说，引线框)上，且接着形成将集成电路裸片物理地接合且电连接到封装衬底的焊料接头。在柱状凸块的端处的大小不均匀的支柱或柱及/或焊料厚度不均匀的焊接材料可在形成于封装式集成电路的装配期间的焊料接头中形成不均匀接合线厚度。
发明内容
在所描述实例中，一种设备包含：半导体衬底，其具有作用表面，所述作用表面具有接合垫；至少两个柱状凸块，其形成于所述接合垫中的至少两者上，所述至少两个柱状凸块延伸远离所述作用表面且具有与所述半导体衬底间隔开的端，其中在所述至少两个柱状凸块的所述端处具有焊料材料。至少一个间隔件形成于所述半导体衬底的所述作用表面上且延伸远离所述半导体衬底，所述至少一个间隔件从所述半导体衬底的所述作用表面延伸预定距离。封装衬底具有在第一表面上用于安装所述半导体衬底的裸片安装区，所述裸片安装区包含接纳所述至少两个柱状凸块的所述端且接纳所述至少一个间隔件的端的若干部分。模制化合物覆盖所述半导体衬底、所述至少两个柱、所述至少一个间隔件及所述半导体衬底的至少一部分。
附图说明
图1是具有柱状凸块的半导体衬底的横截面视图。
图2是在柱状凸块安装于封装衬底上的情况下集成电路裸片的横截面视图。
图3是包含具有安装于封装衬底的表面上的间隔件的集成电路裸片的布置的横截面视图。
图4是在安装到封装衬底之后的包含具有柱状凸块及间隔件的集成电路裸片的布置的横截面视图。
图5A到5D是用于在半导体衬底上形成柱状凸块及间隔件的方法的流程图。
图6A到N是图解说明例如图5A到5D中所展示的用于形成布置的方法的结果的横截面视图。
图7A到7B在平面图中图解说明供与若干布置一起使用的柱状凸块的实例性凸块特征形状。
图8A到8B各自图解说明用于在具有锁结构的封装衬底上安装具有间隔件的集成电路裸片的布置。
图9是图解说明在间隔件位于锁结构中的情况下安装于引线框的表面上的集成电路裸片的布置的横截面。
图10是图解说明封装式集成电路布置的横截面。
图11是供与其中指示间隔件位置的布置一起使用的引线框的平面图。
具体实施方式
除非另有指示，否则不同图中的对应编号及符号一般是指对应部件。所述图未必按比例绘制。如下文中进一步描述，特定结构及表面被描述为彼此“平行”。出于本发明的目的，当两个元件打算位于在延伸时将不相交的平面中时，所述元件是“平行的”。然而，如本文中所使用的术语“平行”还包含由于制造公差而可在方向上稍微有偏差的表面。如果两个表面一般位于间隔开且在无限延伸时将不交叉(如果在不具有这些偏差的情况下制成所述表面)的平面中，那么这些表面也是平行的。
如下文中进一步描述，特定结构及表面被描述为彼此“垂直”。出于本发明的目的，当两个元件元件打算在交叉点处形成90度角时，所述元件是“垂直的”。然而，如本文中所使用的术语“垂直”还包含由于制造公差而可稍微偏离90度的表面。如下文中进一步描述，包含柱状凸块的集成电路裸片可安装到“封装衬底”的表面。如本文中所使用，封装衬底为用于在封装集成电路时安装集成电路裸片的衬底且可为(举例来说)：引线框；模制互连衬底；预模制引线框；预镀引线框，铜衬底；印刷电路板(PCB)；上面形成有导体的膜；上面形成有导体的带条；在表面上且在不同层处具有导体的多层衬底；或上面有导体的层压材料。
图1是半导体衬底(例如半导体晶片)的部分(或个别集成电路裸片)100的横截面视图，所述部分具有形成于表面上的柱或支柱。取决于半导体衬底上的集成电路的功能性及由所述集成电路接收或从所述集成电路发射的信号数目，可存在一个柱、两个柱、至少两个柱或许多柱。在图1中，在作用表面面朝上或“面向上”的情况下定向半导体衬底103，如图1中所定向且展示。半导体衬底103可具有形成于半导体衬底内或形成于半导体衬底103的作用表面104上或上方的有源或无源装置。在实例中，在半导体制造过程中形成例如晶体管或二极管的有源装置及/或例如电感器、电容器或电阻器的无源装置。可使用光学光刻及离子植入技术在半导体衬底中形成P型及N型区域以界定晶体管或二极管的p-n结。可在半导体衬底或晶片的作用表面上方热生长或沉积例如氧化物、氮化物、氮氧化物及其它电介质的电介质材料。电介质可形成隔离材料，形成晶体管的栅极氧化物，或可形成电容器电介质。电介质还可电隔离在半导体衬底的作用表面上方形成的导电材料层。可使用包含金属或合金的导电材料层且使用用以界定导体图案的光学光刻来形成互连导体。可使用化学机械抛光(CMP)过程及金属纹饰镶嵌过程或铜镀覆形成铜导体。可使用导电导通孔或导电插头在导体层之间进行垂直连接。可使用溅射层及无电沉积或电镀形成铝导体。半导体制作过程在半导体衬底的作用表面上形成通过划割线彼此分开的多个完全相同的集成电路裸片。可使用单分方法将完整集成电路裸片彼此分开以穿过划割线进行切割或划割且因此形成个别集成电路裸片。
在图1中，展示半导体衬底103或其一部分，其中支柱或柱105形成于作用表面104上。柱105具有在远离半导体衬底103的作用表面104的端处形成的焊料凸块107。具有焊料凸块的完整柱通常被称为“柱状凸块”。由于柱的材料通常为在半导体制作中频繁使用的铜，因此完整结构110有时被称为“铜柱状凸块”。使用铜是比较实惠的，铜具有低电阻并且可形成低电阻电连接。然而，可使用其它导电材料来形成柱105。如图1中所展示，柱大小或形状的偏差以及过程条件及材料的偏差可致使柱105的柱高度不一致(其中高度为延伸远离半导体衬底103的作用表面104的距离)。柱可在作用表面上的不同位置中具有变化直径或形状，此可在形成柱时产生不同高度。焊接材料还可以不同大小及高度来沉积，且在后续热回流期间可在柱与衬底之间形成不同厚度焊料接头。如下文中进一步描述，当在焊料回流过程中使用柱状凸块来将集成电路裸片安装到封装衬底时此高度偏差可导致不对准或装置故障。故障可包含在热焊料回流期间封装衬底上的镀覆材料不润湿，且柱状凸块与衬底的对准可受影响，从而导致不对准。在测试期间，焊料接头可能会出故障或被发现为高电阻接头。封装衬底可为引线框。所述引线框可具有用于焊接的预镀焊盘，所述预镀焊盘包含薄可焊镀覆层，例如镍、金、银及钯。可在引线框上使用银点镀覆。使用铜引线框上的金或镍金涂层。柱状凸块需要对准到镀覆到引线框上的点或焊盘。在替代方案中，可使用覆盖所有表面或引线框的仅一部分的总体预镀涂层。
图2在横截面视图200中图解说明将具有柱状凸块的集成电路安装到封装衬底。在图2中，为了清晰，针对与图1中的元件类似的元件使用类似参考编号。举例来说，柱205对应于图1中的柱105。在图2中，集成电路裸片203经展示为面朝下而定向，或“翻转的”，以用于装配为倒装芯片装置。(在图1中，相比之下，半导体衬底103经展示为面向上。)
在图2中所展示的操作中，集成电路裸片203(其为从完整半导体衬底或晶片获得的单个集成电路装置)经展示为对准的以倒装芯片安装到封装衬底209。在一个布置中，封装衬底209可为具有与柱状凸块210的位置对应的导电焊盘(未展示)的引线框。柱状凸块210包含柱205及焊料凸块207。引线框可具有铜或另一导电材料。举例来说，例如合金42(镍铁合金，其为42％镍且具有良好电导率及低热膨胀且用于半导体封装的引线框)的合金可用作引线框。在额外替代方案中，还可使用其它金属及导电金属及合金来形成引线框。在替代布置中，封装衬底209可为印刷电路板(PCB)、模制互连衬底、预模制引线框或用于将被表面安装的电组件的另一衬底。在这些替代方案中，封装衬底可具有与柱状凸块210的位置对应地布置的导电焊盘。可用辅助可焊性的材料镀覆所述导电焊盘，举例来说，所述焊盘可具有镍、金或钯涂层及这些的组合，其包含：无电镍浸金(ENIG)、无电镍、无电钯、浸金(ENEPIG)及在用焊料接头对组件进行表面安装时用于可焊性的其它涂层。这些涂层是非常薄的，例如几微米，且因此未在各图中展示。在替代方法中，引线框的裸铜部分用于焊盘。在再一替代方法中，引线框具有在整个裸片安装表面上方形成以用于倒装芯片安装中的预镀层。此预镀层可为辅助将柱状凸块焊接到引线框的材料，举例来说，镍与钯、ENIG、ENEPIG或镍、钯及金的其它组合可用作预镀层。在另一替代方案中，可用例如OSP(“有机可焊性防腐剂”)的有机涂层来涂覆裸铜引线框以通过阻止铜表面的氧化而维持可焊性。
如图2中所展示，当柱205具有变化高度“D”(高度为柱延伸远离集成电路裸片203的作用表面204的距离)时，在后续焊料热回流过程中形成的焊料接合线将具有变化厚度或尺寸。在一些情形中，集成电路裸片203可甚至在热焊料回流过程期间倾斜远离水平位置。如果柱205之间的高度变化足够大，那么柱状凸块210的高度的变化可致使在焊料回流之后形成开口或弱焊料接头。如果由于高度变化而形成高电阻焊料接头，那么当焊料接头在封装测试中暴露于电流时或稍后当电流流动同时穿过焊料接头(当在操作中使用集成电路裸片时)时可发生例如焊料接头破裂的现场故障。如果当焊料在热回流期间处于熔融状态中时裸片倾斜导致裸片的运动，那么可在柱状凸块210与封装衬底209上的焊盘之间或在焊料回流期间发生不对准。
图3在横截面视图300中图解说明包含集成电路裸片303的布置，集成电路裸片303具有形成柱状凸块310的柱305及焊料凸块307。在图3中，为了清晰，与图2中所展示的元件类似的元件的参考编号为类似的。举例来说，图2的集成电路裸片203对应于集成电路裸片303。间隔件311也从集成电路裸片303的作用表面延伸到从集成电路裸片303的表面304测量的高度D1。间隔件311在间隔件端312上不具有焊料，因为在所述布置中，间隔件不用于将电信号从集成电路裸片303耦合到衬底309，替代地，这些间隔件311用于在安装集成电路裸片303之后控制集成电路裸片303的作用表面与封装衬底309的表面之间的间隔。封装衬底309的一部分为裸片安装区(未展示)，其中集成电路裸片303将安装到封装衬底309。在实例中，间隔件311可由与柱305相同的材料形成。间隔件311将具有彼此相等的大小，但未必为与柱305相同的形状、大小或直径。在一个实例中，在镀覆过程中同时形成间隔件311及柱305。然而，在替代布置中，可在独立于形成柱305的过程的过程中形成间隔件311。在实例中，柱305及间隔件311可由铜形成。在替代方案中，柱及间隔件311可由另一导电材料形成。在又另一替代实例中，间隔件311及柱305可由不同材料形成。在替代方案中，间隔件由另一非可回流金属形成。铜为间隔件的便利材料，因为柱通常也由铜便利地形成。可使用镍及钯或镍与钯镀层。这些材料通常也用作镀层且因此可用于所述过程。间隔件311不需要为导电的，尽管间隔件可由为导电的材料形成。间隔件311在包含热回流的后续过程期间不应变形。
图4在横截面视图400中图解说明包含集成电路裸片403的布置，集成电路裸片403具有形成柱状凸块的柱405及柱405上的焊料413。用模制化合物433覆盖所述布置，模制化合物433覆盖集成电路裸片、柱405及焊料接头421及封装衬底409的一部分。在图4中，为了清晰，与图2中所展示的元件类似的元件的参考编号为类似的。举例来说，集成电路裸片403对应于图2中的203。在图4中，展示使用焊料回流过程将具有间隔件411及带有焊料接头421的柱405的集成电路裸片403安装到封装衬底409的结果。在作用表面面对封装衬底的情况下对集成电路裸片进行倒装芯片安装。焊料413在热回流过程致使焊料熔融且接合到封装衬底409的表面(封装衬底409的上表面，如图4中所定向)之后经展示以形成焊料接头421。间隔件411的端接触封装衬底409的表面且提供为间隔件411的高度的预定距离D1的间隔。由于间隔件411具有共同且固定高度D1(归因于非可回流材料的使用且通过在间隔件当中使用相同特征大小)，因此距离D1为集成电路裸片403的作用表面与封装衬底409的表面之间的受控制间隔。此受控制预定间隔还确定在焊料凸块413的焊料回流之后产生的焊料接合线厚度且达成作为过程参数的预定焊料接合线厚度。通过使用布置的间隔件而消除或减少与使用如图2中所展示的柱状凸块的倒装芯片安装式集成电路的非均匀焊料接合线厚度相关联的问题。在装配之后，施加例如环氧树脂的模制化合物以覆盖半导体裸片、间隔件411、柱状凸块410及封装衬底409的一部分以完成封装式集成电路。
图5A到5D在流程图中图解说明用于形成布置(图5A)的间隔件及柱状凸块的主要步骤以及用于形成柱、焊料凸块及间隔件(图5B到5D)的详细过程步骤。图6A到6N在横截面中图解说明图5A到5D的流程图的各种步骤的结果，如下文中进一步描述。
图5A在流程图中图解说明用于形成布置的主要步骤。在步骤501中，在半导体衬底的作用表面上形成柱及间隔件的第一部分。在步骤503中，在柱上形成焊料凸块。焊料凸块以及柱形成柱状凸块。在步骤505中，使间隔件延伸到预定距离(图4中的D1，举例来说)，所述预定距离为间隔件从半导体衬底的表面延伸的完整高度。在图6A到6N中的横截面600中展示这些步骤的结果，如下文进一步描述。
在图5B中，在另一流程图中展示步骤501(在图5A中)的细节。还在图6A到6E中所展示的横截面600中展示这些步骤的结果。在步骤5011中，在半导体衬底的作用表面上溅射晶种层或凸块下材料(UBM)。如图6A的横截面600中所展示，半导体衬底603具有保护外涂层621。保护外涂层621可为氮化物、氧化物、氮氧化物或其它电介质层。接合垫623经展示在半导体衬底603的表面处(在此实例中，接合垫623为铝(Al))。可使用其它金属及合金作为接合垫，举例来说，可使用铜。在图6A的实例中，在接合垫623上方形成再分布层(RDL)627。在实例中，通过在铝接合垫上方形成铜层而使用铝上铜(COA)RDL。在钝化层625中形成RDL层627。在实例中，钝化层625可为聚酰亚胺(PI)。如图6A中所展示，通过钝化层625中的开口暴露层627的一部分。在半导体衬底的表面上形成晶种层631且晶种层631覆盖RDL层627及钝化层625。
返回到图5B，方法在用第一光致抗蚀剂633涂覆半导体衬底603的作用表面的步骤5013处继续。光致抗蚀剂633可为正性或负性光致抗蚀剂。光致抗蚀剂633位于晶种层631上方。
返回到图5B，方法继续到步骤5015，其中图案化第一光致抗蚀剂以界定用于柱及间隔件两者的开口636、637。图案化且暴露光致抗蚀剂。在图5B中，在步骤5017处，使光致抗蚀剂显影。在图6C的横截面中展示此步骤的结果，其中第一光致抗蚀剂633形成有开口，从而在用于形成柱的在层627上方的位置636中且在层625及晶种层631上方的第二位置637(将在其中形成间隔件)中暴露晶种层631。
返回到图5B，在步骤5019处，执行镀覆操作以形成布置的柱及间隔件的一部分。在图6D的横截面中展示镀覆操作的结果。在本文中所描述的实例中，在此阶段处，像晶种层631一样，柱641及间隔件643也由铜形成。镀覆可为电镀过程。在替代方案中，可执行无电镀覆操作。镀覆操作用材料填充第一光致抗蚀剂633中的开口以形成柱641及间隔件643的第一部分。
在图5B中，方法继续到步骤5021，其中移除第一光致抗蚀剂层(图6D中的633)。在图6E中展示步骤的结果。在图6E中，现在暴露晶种层631，因为移除了光致抗蚀剂633(在图6D中)。在实例性过程中，使用光致抗蚀剂剥离过程。在图6E中展示结果，其中在移除光致抗蚀剂之后展示柱641及间隔件643。
返回到图5A，在图5C的流程图中详述在柱的端处形成焊接材料以形成柱状凸块的下一主要步骤503，且在图6F到6I中所图解说明的横截面中展示所述步骤的结果。在图5C中，方法从图5B中的最后步骤5021继续到步骤5031。在步骤5031处，形成涂覆半导体晶片的作用表面的第二光致抗蚀剂。在图6F的横截面中展示此步骤的结果。展示涂覆柱641及间隔件643的第二光致抗蚀剂层635。
图5C的方法在步骤5033处继续，其中在保护间隔件的同时图案化第二光致抗蚀剂(图6F中的635)以界定与柱对应的开口。在步骤5035处，使第二光致抗蚀剂显影以暴露柱的端。在图6G中的横截面中展示这些步骤的结果。暴露柱641的端以进行进一步处理，同时第二光致抗蚀剂635保护间隔件643。
图5C的方法在步骤5037处继续，其中在柱上形成焊接材料以形成柱状凸块。在图6H的横截面中展示此步骤的结果，其中焊料层645经展示为形成于柱641的端上方。在柱641的端上方镀覆焊料。在实例中，镀覆锡-银(SnAg)组合物的无铅焊料。可使用例如锡银铜(SnAgCu或“SAC”)的其它无铅焊料。在替代方案中，可使用例如PbSn的含铅焊料。在柱641上方形成但不在间隔件643上方形成焊料层645。
图5C的方法在步骤5039处继续，其中移除第二光致抗蚀剂层。图6I中的横截面展示此步骤的结果，其中所形成的柱状凸块610包含柱641及焊料层645。
返回到图5A，执行形成额外间隔件材料的步骤505。在图5D中的流程图中详述步骤505的过程。在步骤5051处开始，用第三光致抗蚀剂层涂覆半导体晶片。在图6J的横截面中展示步骤5051的结果，其中第三光致抗蚀剂层661经展示为形成于柱641及间隔件643上方。
图5D的方法在步骤5053及5055处继续，其中使用光学光刻步骤及光掩模图案化第三光致抗蚀剂层661，且使经图案化光致抗蚀剂显影以形成暴露间隔件的端的开口。在图6K处的横截面中展示这些步骤的结果，其中开口651经展示位于间隔件643上方，同时保留覆盖由柱641及焊料层645形成的柱状凸块的第三光致抗蚀剂层。
图5D的方法在步骤5057处继续。在步骤5057处，通过间隔件材料的额外电镀或无电镀覆使间隔件延伸。在实例中，间隔件材料为铜且镀覆额外铜以使间隔件延伸到延伸远离半导体晶片的表面的所要高度。在实例中，间隔件高度确定预定距离。在完成图5A到D的方法且将包含柱状凸块及间隔件的集成电路裸片倒装芯片安装到封装衬底(如上文中所描述)之后，至少两个柱中的任一者的长度与在选定柱的端与封装衬底的表面之间形成的焊料接头的厚度相加所得与预定距离相差不超过10％。在替代方案中，额外间隔件材料可为镀覆在间隔件上的另一材料，例如镍、钯或有益于电镀或无电镀覆的其它材料。在图6L中展示此步骤的结果，其中间隔件643具有镀覆到经暴露端上的额外部分653(图6K中所展示)。
图5D的方法在步骤5059处继续，其中移除第三光致抗蚀剂层661(在图6L中)，如图6M中所展示。暴露完整柱状凸块(610)及由部分643、653形成的完整间隔件(611)。间隔件611从半导体晶片的表面延伸到预定距离D1(参见图6N)。通过在间隔件形成过程期间调整过程条件，可控制预定距离D1，此在集成电路裸片稍后在倒装芯片布置中安装到封装衬底(如图4中所展示且上文中所描述)时提供对半导体表面与封装衬底之间的间隔的控制。
在图5D中的步骤5061处完成所述方法，其中移除UBM材料。在图6N的横截面中展示此步骤的结果，其中晶种层631(在图6M中)经展示为被移除。在实例性过程中，执行灰化(蚀刻)步骤以移除UBM。如图6N中所展示，以不同高度形成包含柱641及焊料层645的完整柱状凸块610以及完整间隔件611。距离D1为间隔件611的预定距离。由于控制且可在预定距离处形成间隔件高度，因此可使用距离D1控制在后续倒装芯片装配及热焊料回流过程期间达成的焊料接合线厚度。间隔件形成对经装配布置的机械支撑及间隔控制。
图7A及7B在两个平面图中图解说明两个大小不同的柱状凸块的凸块特征大小。在图7A中，圆形柱状凸块特征751经展示具有“X”的直径。在实例中，直径在50到150微米的范围内。在图7B中，椭圆形凸块特征753经展示具有大约100微米的宽度“Y”及大约300微米的长度“Z”。在额外实例中，椭圆形凸块特征可具有介于50与200微米之间的宽度；及介于100与400微米之间的长度。可使用其它形状，且可使用其它大小。在确定柱状凸块特征时，大小及形状的选择可由将由柱状凸块携载以用于来自(或去往)集成电路的特定信号的电流来确定。间隔件还可具有不同于柱的形状的大小及形状，但在特定布置中间隔件应针对给定集成电路裸片全部具有相同大小及形状。在实例中，第一间隔件具有第一横截面形状及面积，且其余间隔件具有第一横截面形状及面积。通过针对所有间隔件使用相同大小及形状，可维持完整间隔件的共面性。以此方式，所获得的间隔距离及在焊料回流之后形成的焊料接合线厚度在稍后安装于封装衬底上时跨越集成电路裸片为均匀的。
图8A及8B在两个横截面视图中图解说明其中锁定特征设置于封装衬底中的两个额外布置。在图8A中，集成电路裸片803(在图8A中展示803的一部分)具有间隔件811，而且集成电路裸片803具有额外间隔件及柱状凸块(未展示)。封装衬底809具有锁结构819，锁结构819为经配置以在集成电路裸片803倒装芯片安装到封装衬底809时接纳间隔件端的开口或狭槽。锁结构819为组合件提供对准导引件，使得集成电路裸片803在间隔件811与锁结构819对准且插入到锁结构819中时恰当地经定位。在图8A中，可通过蚀刻封装衬底809而形成锁。在实例中，封装衬底809为铜引线框。
图8B在横截面中图解说明其中以与图8A的方式类似的方式形成锁结构819的替代布置，然而，使用压印或冲压操作来形成封装衬底809中的锁结构819。再次，集成电路裸片803具有在使得达成如下情况的位置中的间隔件811：当间隔件端插入到锁结构819中时，包含将耦合到封装衬底809上的焊盘(也未展示)的柱状凸块(图8A到8B中未展示)的集成电路裸片处于正确对准中以用于将倒装芯片集成电路裸片装配到封装衬底。使用包含锁特征的封装衬底减少或消除对衬底上的焊盘进行预镀以提供柱状凸块与衬底之间的对准的需要。在其中封装衬底包含锁特征的布置中，通过使用锁及间隔件(其中若干部分定位于锁中)来维持在焊料回流期间的对准。举例来说，在与间隔件一起使用铜引线框及锁特征的应用中可不需要对用作封装衬底的引线框上的引线上的焊盘进行预镀。当锁特征控制倒装芯片集成电路与封装衬底之间的对准时可在不具有预镀焊盘的情况下形成在正确位置中的可靠焊料接头。在实例中，在装配之前可在整个引线框上方提供薄预镀涂层，而不形成与特定柱状凸块接合的特定焊盘。
图9在横截面中图解说明其中集成电路裸片903装配到封装衬底909的布置。在图9中，为了清晰，针对如图4中所展示的类似元件使用类似元件符号。举例来说，封装衬底909对应于图4中的封装衬底409。在图9中，在回流之后展示柱状凸块910。在图9中，在将间隔件911放置为延伸到锁结构919中之后，集成电路裸片903的表面与封装衬底909之间的间隔为预定距离D2。如通过将此图与图8A到8B进行比较所见，距离D2小于间隔件的长度D1，因为在此布置中间隔件延伸到封装衬底909中的锁结构919中。在布置中，间隔件的高度减去锁结构的深度形成集成电路的作用表面与封装衬底的表面之间的预定间隔D2。锁结构919可经蚀刻到封装衬底909中(如在图8A中)或可经压印到封装衬底中(如在图8B中)。可通过控制间隔件911的长度而调整间隔距离D2。
图10在横截面视图中图解说明包含布置的封装式集成电路1000。为了清晰，图10的参考标记对应于图9中的类似元件，举例来说，集成电路裸片1003对应于图9中的裸片903。在图10中，具有柱状凸块1010及间隔件1011的集成电路裸片1003倒装芯片安装到封装衬底1009，举例来说，铜引线框。展示锁1019，其中间隔件1011插入到锁1019中。模制化合物1033形成完整封装且环绕集成电路裸片1003、柱状凸块1010及间隔件1011以及封装衬底1009的一部分。因此，模制化合物、集成电路裸片及封装衬底的组合形成封装式集成电路。封装衬底1109(其在此实例中为铜引线框)的其它部分形成用于完整封装的外部端子或热垫且这些部分(未展示)未被覆盖在模制化合物1033中。模制化合物1033可为在块压模机中形成的环氧、树脂或热固性环氧树脂。模制过程可被称为“囊封”过程，即使在“囊封”完成之后封装衬底1009的若干部分将无模制化合物。在实例性过程中，在模制包含接纳数个个别集成电路装置的数个引线框的引线框条带之后，通过切穿引线框材料及模制化合物以形成封装的锯切或激光操作来将个别封装式集成电路彼此分开。引线框的若干部分未被模制化合物覆盖，而是保持暴露，这些经暴露引线框部分形成封装式集成电路的外部端子。在另一实例中，完整封装可为方扁形无引线(QFN)封装以用于表面安装到系统板。
图11在平面图中图解说明封装衬底1109，其中引线1121经图案化且焊盘用于接纳集成电路裸片的柱状凸块(举例来说，参见图9中的903)。应注意，图9及10的实例性横截面不对应于图11中的额外实例性封装衬底的平面图。在图11中，椭圆形焊盘1141布置于封装衬底1109上以接纳椭圆形柱状凸块，而圆形焊盘1143经布置以接纳圆形柱状凸块。
在图11中，封装衬底1109具有经指示为1135的裸片安装区及识别将安装到衬底1109的在集成电路裸片上的间隔件的可能位置的部分1131。应注意，未在图11中展示间隔件，替代地，位置1131指示可使用间隔件的地方。图11中的裸片安装区部分1135的轮廓指示将安装于衬底1109上的集成电路的位置及大小。在一个实例中，间隔件放置于集成电路裸片的外部隅角处。举例来说，第一间隔件可放置于集成电路裸片的第一隅角中，且额外间隔件可放置于其余三个隅角处，使得集成电路裸片的四个隅角中的每一者中存在将安装到衬底1109的间隔件。在经标记为1131的额外替代实例中，无柱状凸块的内部位置还可在所述位置处具有用以在热回流期间提供额外机械支撑且提供焊料接合线厚度控制的间隔件。由于集成电路裸片及引线框图案随不同集成电路设计变化，因此间隔件位置也将取决于集成电路裸片的可用空间及大小而变化。可通过针对较大集成电路裸片使用额外间隔件而避免或减少不对准、裸片翘曲及裸片倾斜。
修改在所描述布置中为可能的，且其它替代布置在权利要求书的范围内为可能的。

Claims (23)

1.一种设备，其包括：
半导体衬底，其具有上面有接合垫的作用表面；
至少两个柱状凸块，其形成于所述接合垫中的至少两者上，所述至少两个柱状凸块延伸远离所述作用表面且具有与所述半导体衬底间隔开的端，其中在所述至少两个柱状凸块的所述端处具有焊接材料；
至少一个间隔件，其形成于所述半导体衬底的所述作用表面上且延伸远离所述半导体衬底，所述至少一个间隔件从所述半导体衬底的所述作用表面延伸预定距离；
封装衬底，其具有在第一表面上用于安装所述半导体衬底的裸片安装区，所述裸片安装区包含接纳所述至少两个柱状凸块的所述端且接纳所述至少一个间隔件的端的若干部分；及
模制化合物，其覆盖所述半导体衬底、所述至少两个柱状凸块、所述至少一个间隔件及所述封装衬底的至少一部分。
2.根据权利要求1所述的设备，其中在所述至少两个柱状凸块的所述端处的所述焊接材料在所述封装衬底的所述裸片安装区上形成焊料接头。
3.根据权利要求2所述的设备，其中在所述至少两个柱状凸块与所述封装衬底的所述裸片安装区之间形成的所述焊料接头的厚度由所述至少一个间隔件的所述预定距离确定。
4.根据权利要求1所述的设备，其中所述至少一个间隔件的所述预定距离确定所述封装衬底的所述第一表面与所述半导体衬底的所述作用表面之间的间隔。
5.根据权利要求1所述的设备，其中所述至少两个柱状凸块为选自铜及其合金中的一者的材料。
6.根据权利要求1所述的设备，其中所述焊接材料为选自基本上由以下各项组成的群组的一者：锡及银；锡、银及铜；以及锡及铅。
7.根据权利要求1所述的设备，其中所述半导体衬底为具有四个隅角的集成电路裸片，所述至少一个间隔件位于所述四个隅角中的一者处，且所述设备进一步包括在所述集成电路裸片的所述作用表面上放置于其余三个隅角处的额外间隔件。
8.根据权利要求1所述的设备，其中所述至少一个间隔件为导电材料。
9.根据权利要求8所述的设备，其中所述导电材料为铜。
10.根据权利要求1所述的设备，其中所述至少一个间隔件及所述至少两个柱状凸块进一步包括铜。
11.一种方法，其包括：
在半导体衬底的作用表面上形成至少两个柱及至少一个间隔件；
在所述至少两个柱的端处形成焊接材料以形成至少两个柱状凸块；
添加额外材料以使所述至少一个间隔件远离所述半导体衬底的所述作用表面延伸到预定距离；
将所述半导体衬底安装到封装衬底，其中所述至少两个柱状凸块的所述焊接材料在所述封装衬底的表面上形成焊料接头且所述至少一个间隔件的端接触所述封装衬底使得所述半导体衬底与所述封装衬底间隔开所述预定距离；及
用模制化合物覆盖所述半导体衬底、所述至少两个柱状凸块、所述至少一个间隔件及所述封装衬底的一部分。
12.根据权利要求11所述的方法，其中形成所述至少两个柱及所述至少一个间隔件进一步包括：
将晶种层溅射到所述半导体衬底的所述作用表面上；
用光致抗蚀剂涂覆所述半导体衬底的所述作用表面；
图案化所述光致抗蚀剂以在与所述半导体衬底的所述作用表面上的接合垫对应的位置处界定所述至少两个柱且在间隔件位置处界定所述至少一个间隔件；
使所述光致抗蚀剂显影以在所述位置处暴露所述晶种层；
在所述位置处将材料镀覆到所述晶种层上以形成所述至少两个柱及所述至少一个间隔件；及
移除所述光致抗蚀剂。
13.根据权利要求12所述的方法，其中所述光致抗蚀剂为第一光致抗蚀剂，且形成焊接材料进一步包括：
用第二光致抗蚀剂涂覆所述作用表面；
在使所述至少一个间隔件被覆盖的同时图案化所述第二光致抗蚀剂以界定与所述至少两个柱对应的开口；
将所述光致抗蚀剂暴露；
使所述光致抗蚀剂显影以在所述第二光致抗蚀剂中形成暴露所述至少两个柱的所述端的开口；
将焊接材料镀覆到所述至少两个柱的所述端上；及
移除所述第二光致抗蚀剂。
14.根据权利要求13所述的方法，其中形成所述至少一个间隔件的所述额外材料进一步包括：
用第三光致抗蚀剂涂覆作用表面；
图案化所述第三光致抗蚀剂以形成与所述至少一个间隔件对应的至少一个开口；
使所述第三光致抗蚀剂显影以在所述第三光致抗蚀剂中形成用以暴露所述至少一个间隔件的开口；及
在所述至少一个间隔件上镀覆额外材料以使所述至少一个间隔件延伸远离所述作用表面以在距所述作用表面所述预定距离处形成间隔件端。
15.根据权利要求14所述的方法，其中所述至少一个间隔件具有第一横截面形状及面积，且所述方法进一步包含在所述半导体衬底的所述作用表面上形成具有所述第一横截面形状及面积的额外间隔件。
16.根据权利要求15所述的方法，其中所述至少两个柱中的任一者的长度与在所述至少两个柱中的选定一者的端与所述封装衬底的所述表面之间形成的焊料接头的厚度相加所得与所述预定距离相差不超过10％。
17.根据权利要求11所述的方法，其中所述半导体衬底为集成电路裸片且所述模制化合物与所述集成电路裸片及所述封装衬底一起形成封装式集成电路。
18.一种设备，其包括：
引线框，其具有在第一表面上的裸片安装区且具有从所述第一表面延伸到所述引线框中的锁结构；及
半导体衬底，其具有作用表面，所述半导体衬底进一步包括：
至少两个柱，其在所述半导体衬底的所述作用表面上的接合垫上，所述至少两个柱延伸远离所述作用表面且具有安置于所述至少两个柱的端上以形成至少两个柱状凸块的焊接材料；及
至少一个间隔件，其从所述半导体衬底的所述作用表面延伸成与所述半导体衬底的所述作用表面相距预定距离且具有间隔件端；
其中所述半导体衬底、所述至少两个柱状凸块及所述至少一个间隔件倒装芯片安装到所述引线框的所述裸片安装区，所述焊接材料在所述引线框的所述第一表面与所述至少两个柱状凸块之间形成焊料接头，且所述间隔件端及所述至少一个间隔件的一部分定位于延伸到所述引线框中的所述锁结构中的选定一者中。
19.根据权利要求18所述的设备，其中所述锁结构经蚀刻到所述引线框的所述第一表面中。
20.根据权利要求18所述的设备，其中所述锁结构是通过压印所述引线框而形成的。
21.根据权利要求18所述的设备，其中所述间隔件的长度减去所述锁结构的深度形成所述半导体衬底的所述作用表面与所述引线框的所述第一表面之间的预定间隔。
22.根据权利要求18所述的设备，其进一步包括覆盖所述半导体衬底、所述至少两个柱状凸块、所述至少一个间隔件及所述引线框的若干部分的模制化合物。
23.根据权利要求22所述的设备，其中所述半导体衬底为集成电路裸片，且所述模制化合物与所述引线框及所述集成电路裸片一起形成封装式集成电路。
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